On Tue, Sep 23, 2014 at 2:43 PM, Matt Turner wrote:
> On Sat, Sep 20, 2014 at 10:22 AM, Jason Ekstrand wrote:
>> This series does a bunch of refactoring of the i965 fs backend IR to add
>> concepts of register width and instruction execution size. There's more to
>> be done yet, but this gets us
On Tue, Sep 23, 2014 at 11:43 AM, Matt Turner wrote:
> On Sat, Sep 20, 2014 at 10:22 AM, Jason Ekstrand
> wrote:
> > This series does a bunch of refactoring of the i965 fs backend IR to add
> > concepts of register width and instruction execution size. There's more
> to
> > be done yet, but thi
On Sat, Sep 20, 2014 at 10:22 AM, Jason Ekstrand wrote:
> This series does a bunch of refactoring of the i965 fs backend IR to add
> concepts of register width and instruction execution size. There's more to
> be done yet, but this gets us most of the way there. It also removes the
> assumption
One more quick note. If you find it nicer, the whole thing can be found
here:
http://cgit.freedesktop.org/~jekstrand/mesa/tree/?h=kill-mrf-v1
On Sat, Sep 20, 2014 at 10:22 AM, Jason Ekstrand
wrote:
> This series does a bunch of refactoring of the i965 fs backend IR to add
> concepts of registe
This series does a bunch of refactoring of the i965 fs backend IR to add
concepts of register width and instruction execution size. There's more to
be done yet, but this gets us most of the way there. It also removes the
assumption that scalar values are always 1 register in SIMD8 and 2
registers
