On Fri, Oct 13, 2017 at 2:24 PM, Mike Lothian wrote:
> Hi
>
> Have you ran any benchmarks against these?
No I haven't.
For the IB placement, I measured the decrease in CP stalls using
performance counters, but generally CP isn't memory-bound on radeonsi
due to our optimized packet ordering.
For
Hi
Have you ran any benchmarks against these?
Cheers
Mike
On Fri, 13 Oct 2017 at 13:04 Marek Olšák wrote:
> Hi,
>
> This series:
> - switches IB placement to GTT WC
> - uses SPI_SHADER_USER_DATA_COMMON on GFX9
> - combines setting of 2 per-stage descriptor pointers into 1 SET_SH_REG
> packet
Hi,
This series:
- switches IB placement to GTT WC
- uses SPI_SHADER_USER_DATA_COMMON on GFX9
- combines setting of 2 per-stage descriptor pointers into 1 SET_SH_REG packet
- if there is only 1 constant buffer and 0 shader and atomic buffers,
the constant buffer pointer is directly set into SI_S
