On 30 January 2018 at 02:26, Matthew Nicholls
wrote:
> This can lead to a situation where cache flushes could get conditionally
> disabled while still clearing the flush_bits, and thus flushes due to
> application pipeline barriers may never get executed.
Thanks I've pushed this now.
Dave.
_
This can lead to a situation where cache flushes could get conditionally
disabled while still clearing the flush_bits, and thus flushes due to
application pipeline barriers may never get executed.
Cc: mesa-sta...@lists.freedesktop.org
---
src/amd/vulkan/radv_cmd_buffer.c | 2 +-
src/amd/vulkan/r
