On 26 Jan. 2018 01:10, "Matthew Nicholls"
wrote:
Otherwise cache flushes could get conditionally disabled while still
clearing
the flush_bits, and thus flushes due to application pipeline barriers may
never
get executed.
I wonder would we better not predicating flushes. I added that as an extra
Otherwise cache flushes could get conditionally disabled while still clearing
the flush_bits, and thus flushes due to application pipeline barriers may never
get executed.
Cc: mesa-sta...@lists.freedesktop.org
---
src/amd/vulkan/radv_meta_fast_clear.c | 2 ++
1 file changed, 2 insertions(+)
diff