Re: [Mesa-dev] [PATCH] intel: Fix stencil buffer to be W tiled

2011-07-19 Thread Eric Anholt
On Mon, 18 Jul 2011 17:00:54 -0700, Chad Versace wrote: > On 07/18/2011 08:57 AM, Eric Anholt wrote: > > On Mon, 18 Jul 2011 00:55:03 -0700, Chad Versace > > wrote: > >> diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c > >> b/src/mesa/drivers/dri/intel/intel_fbo.c > >> index 1669af2..507cc33

[Mesa-dev] [PATCH] intel: Fix stencil buffer to be W tiled

2011-07-18 Thread Chad Versace
Until now, the stencil buffer was allocated as a Y tiled buffer, because in several locations the PRM states that it is. However, it is actually W tiled. From the PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Format: W-Major Tile Format is used for separate stencil. The GTT

Re: [Mesa-dev] [PATCH] intel: Fix stencil buffer to be W tiled

2011-07-18 Thread Chad Versace
On 07/18/2011 08:57 AM, Eric Anholt wrote: > On Mon, 18 Jul 2011 00:55:03 -0700, Chad Versace wrote: >> diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c >> b/src/mesa/drivers/dri/intel/intel_fbo.c >> index 1669af2..507cc33 100644 >> --- a/src/mesa/drivers/dri/intel/intel_fbo.c >> +++ b/src/mes

Re: [Mesa-dev] [PATCH] intel: Fix stencil buffer to be W tiled

2011-07-18 Thread Ian Romanick
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 07/18/2011 02:24 PM, Chad Versace wrote: > On 07/18/2011 02:02 PM, Ian Romanick wrote: >> On 07/18/2011 01:54 PM, Chad Versace wrote: >>> On 07/18/2011 11:49 AM, Ian Romanick wrote: On 07/18/2011 12:55 AM, Chad Versace wrote: > Until now, t

Re: [Mesa-dev] [PATCH] intel: Fix stencil buffer to be W tiled

2011-07-18 Thread Chad Versace
On 07/18/2011 02:02 PM, Ian Romanick wrote: > On 07/18/2011 01:54 PM, Chad Versace wrote: >> On 07/18/2011 11:49 AM, Ian Romanick wrote: >>> On 07/18/2011 12:55 AM, Chad Versace wrote: Until now, the stencil buffer was allocated as a Y tiled buffer, because in several locations the PRM st

Re: [Mesa-dev] [PATCH] intel: Fix stencil buffer to be W tiled

2011-07-18 Thread Chad Versace
On 07/18/2011 08:57 AM, Eric Anholt wrote: > On Mon, 18 Jul 2011 00:55:03 -0700, Chad Versace wrote: >> diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c >> b/src/mesa/drivers/dri/intel/intel_fbo.c >> index 1669af2..507cc33 100644 >> --- a/src/mesa/drivers/dri/intel/intel_fbo.c >> +++ b/src/mes

Re: [Mesa-dev] [PATCH] intel: Fix stencil buffer to be W tiled

2011-07-18 Thread Ian Romanick
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 07/18/2011 01:54 PM, Chad Versace wrote: > On 07/18/2011 11:49 AM, Ian Romanick wrote: >> On 07/18/2011 12:55 AM, Chad Versace wrote: >>> Until now, the stencil buffer was allocated as a Y tiled buffer, because >>> in several locations the PRM state

Re: [Mesa-dev] [PATCH] intel: Fix stencil buffer to be W tiled

2011-07-18 Thread Chad Versace
On 07/18/2011 11:49 AM, Ian Romanick wrote: > On 07/18/2011 12:55 AM, Chad Versace wrote: >> Until now, the stencil buffer was allocated as a Y tiled buffer, because >> in several locations the PRM states that it is. However, it is actually >> W tiled. From the PRM, 2011 Sandy Bridge, Volume 1, Par

Re: [Mesa-dev] [PATCH] intel: Fix stencil buffer to be W tiled

2011-07-18 Thread Ian Romanick
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 07/18/2011 12:55 AM, Chad Versace wrote: > Until now, the stencil buffer was allocated as a Y tiled buffer, because > in several locations the PRM states that it is. However, it is actually > W tiled. From the PRM, 2011 Sandy Bridge, Volume 1, Part

Re: [Mesa-dev] [PATCH] intel: Fix stencil buffer to be W tiled

2011-07-18 Thread Eric Anholt
On Mon, 18 Jul 2011 00:55:03 -0700, Chad Versace wrote: > diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c > b/src/mesa/drivers/dri/intel/intel_fbo.c > index 1669af2..507cc33 100644 > --- a/src/mesa/drivers/dri/intel/intel_fbo.c > +++ b/src/mesa/drivers/dri/intel/intel_fbo.c > @@ -173,6 +173,9

[Mesa-dev] [PATCH] intel: Fix stencil buffer to be W tiled

2011-07-18 Thread Chad Versace
Until now, the stencil buffer was allocated as a Y tiled buffer, because in several locations the PRM states that it is. However, it is actually W tiled. From the PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Format: W-Major Tile Format is used for separate stencil. The GTT

[Mesa-dev] [PATCH] intel: Fix stencil buffer to be W tiled

2011-07-18 Thread Chad Versace
Chad Versace (2): xf86-video-intel dri: Do not tile stencil buffer src/intel_dri.c | 16 mesa intel: Fix stencil buffer to be W tiled src/mesa/drivers/dri/intel/intel_clear.c |6 ++ src/mesa/drivers/dri/intel/intel_context.c |9 ++-