Re: [Mesa-dev] [PATCH] i965: Implement a CS stall workaround on Broadwell.

2014-02-19 Thread Ian Romanick
Reviewed-by: Ian Romanick On 02/19/2014 04:28 PM, Kenneth Graunke wrote: > According to the latest documentation, any PIPE_CONTROL with the > "Command Streamer Stall" bit set must also have another bit set, > with five different options: > >- Render Target Cache Flush >- Depth Cache Flus

[Mesa-dev] [PATCH] i965: Implement a CS stall workaround on Broadwell.

2014-02-19 Thread Kenneth Graunke
According to the latest documentation, any PIPE_CONTROL with the "Command Streamer Stall" bit set must also have another bit set, with five different options: - Render Target Cache Flush - Depth Cache Flush - Stall at Pixel Scoreboard - Post-Sync Operation - Depth Stall I chose "St