Re: [Mesa-dev] [PATCH] i965/vec4: Opportunistically coalesce SIMD8 instructions

2015-02-17 Thread Kenneth Graunke
On Tuesday, February 17, 2015 04:59:37 PM Matt Turner wrote: > On Tue, Feb 17, 2015 at 4:44 PM, Ben Widawsky > wrote: > > With scalar VS, it so happens that many vertex shaders will line up in a > > such a > > way that two SIMD8 instructions can be collapsed into 1 SIMD16 instruction. > > For >

Re: [Mesa-dev] [PATCH] i965/vec4: Opportunistically coalesce SIMD8 instructions

2015-02-17 Thread Ben Widawsky
On Tue, Feb 17, 2015 at 04:59:37PM -0800, Matt Turner wrote: > On Tue, Feb 17, 2015 at 4:44 PM, Ben Widawsky > wrote: > > With scalar VS, it so happens that many vertex shaders will line up in a > > such a > > way that two SIMD8 instructions can be collapsed into 1 SIMD16 instruction. > > For >

Re: [Mesa-dev] [PATCH] i965/vec4: Opportunistically coalesce SIMD8 instructions

2015-02-17 Thread Matt Turner
On Tue, Feb 17, 2015 at 4:44 PM, Ben Widawsky wrote: > With scalar VS, it so happens that many vertex shaders will line up in a such > a > way that two SIMD8 instructions can be collapsed into 1 SIMD16 instruction. > For > example > > The following two MOVs > mov(8) g124<1>Fg6<8

[Mesa-dev] [PATCH] i965/vec4: Opportunistically coalesce SIMD8 instructions

2015-02-17 Thread Ben Widawsky
With scalar VS, it so happens that many vertex shaders will line up in a such a way that two SIMD8 instructions can be collapsed into 1 SIMD16 instruction. For example The following two MOVs mov(8) g124<1>Fg6<8,8,1>F { align1 1Q compacted }; mov(8) g