Re: [Mesa-dev] [PATCH] i965/gen6: Fix GPU hang when using stencil buffer without depth

2011-11-23 Thread Chad Versace
On 11/23/2011 10:26 AM, Kenneth Graunke wrote: > On 11/23/2011 10:11 AM, Chad Versace wrote: >> Set the "Tiled Surface" bit in 3DSTATE_DEPTH_BUFFER. From the BSpec: > > I believe you mean > "From the Sandybridge PRM, Volume 2, Part 1, section 7.5.5.1.1:" > >>[DevGT+]: This field must be set t

Re: [Mesa-dev] [PATCH] i965/gen6: Fix GPU hang when using stencil buffer without depth

2011-11-23 Thread Kenneth Graunke
On 11/23/2011 10:11 AM, Chad Versace wrote: > Set the "Tiled Surface" bit in 3DSTATE_DEPTH_BUFFER. From the BSpec: I believe you mean "From the Sandybridge PRM, Volume 2, Part 1, section 7.5.5.1.1:" >[DevGT+]: This field must be set to TRUE. Also, do we want to set this bit when emitting 3DS

[Mesa-dev] [PATCH] i965/gen6: Fix GPU hang when using stencil buffer without depth

2011-11-23 Thread Chad Versace
Set the "Tiled Surface" bit in 3DSTATE_DEPTH_BUFFER. From the BSpec: [DevGT+]: This field must be set to TRUE. Fixes GPU hangs on following the Piglit tests: hiz-stencil-test-fbo-d0-s8 hiz-stencil-read-fbo-d0-s8 Signed-off-by: Chad Versace --- src/mesa/drivers/dri/i965/brw_misc_state.c