On Thu, Oct 2, 2014 at 4:16 PM, Jason Ekstrand wrote:
> Before, we were hard-coding the base_mrf based on dispatch width not number
> of registers spilled at a time. This caused us to emit instructions with a
> base_mrf or 14 and a mlen of 3 so we used the magical non-existant m16
> register. Th
Before, we were hard-coding the base_mrf based on dispatch width not number
of registers spilled at a time. This caused us to emit instructions with a
base_mrf or 14 and a mlen of 3 so we used the magical non-existant m16
register. This fixes the problem.
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src/mesa/drivers/dri/i965/brw_fs_reg
