Reviewed-by: Marek Olšák
Marek
On Tue, Feb 27, 2018 at 6:49 AM, Timothy Arceri wrote:
> radeonsi, i965 and anv all treat fdd{x,y} opcodes the same as
> fdd{x,y}_coarse by default. The SPIR-V spec lets the implementation
> decide how it should be handled and radv was previously going
> for the h
Reviewed-by: Dave Airlie
Though I suspect the test should handle getting either.
Dave.
On 27 February 2018 at 15:49, Timothy Arceri wrote:
> radeonsi, i965 and anv all treat fdd{x,y} opcodes the same as
> fdd{x,y}_coarse by default. The SPIR-V spec lets the implementation
> decide how it shoul
radeonsi, i965 and anv all treat fdd{x,y} opcodes the same as
fdd{x,y}_coarse by default. The SPIR-V spec lets the implementation
decide how it should be handled and radv was previously going
for the higher quality option. Here we change the shared amd
code to match how nir_op_fdd{x,y} is expected
