It seems reset is not required for setting the max_wm_threads to 80 gen6 GT2.
Signed-off-by: Zou Nan hai
---
src/mesa/drivers/dri/i965/brw_context.c |6 +-
1 files changed, 1 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
b/src/mesa/drivers/dri/i965
on gen6+, PIPE_CONTROL reported time stamp are 64 bits
value (high 32 bits MBZ on snb), toggles every 80 ns.
Signed-off-by: Zou Nan hai
---
src/mesa/drivers/dri/i965/brw_queryobj.c | 17 -
1 files changed, 12 insertions(+), 5 deletions(-)
diff --git a
on gen6+, render engine PIPE_CONTROL reported time stamp is a 64 bits
value (high 32 bits MBZ on snb), toggles every 80 ns.
Signed-off-by: Zou Nan hai
---
src/mesa/drivers/dri/i965/brw_queryobj.c | 17 -
1 files changed, 12 insertions(+), 5 deletions(-)
diff --git a
on gen6+, PIPE_CONTROL reported timestamp counter is a
64 bits value, toggles every 80 ns
Signed-off-by: Zou Nan hai
---
src/mesa/drivers/dri/i965/brw_queryobj.c | 17 -
1 files changed, 12 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965
PIPE_CONTROL reported time stamp is a 64 bits value,
toggles every 80ns.
Signed-off-by: Zou Nan hai
---
src/mesa/drivers/dri/i965/brw_queryobj.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_queryobj.c
b/src/mesa/drivers
---
src/mesa/drivers/dri/intel/intel_batchbuffer.c | 11 ++-
1 files changed, 10 insertions(+), 1 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c
b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
index 767c903..7654261 100644
--- a/src/mesa/drivers/dri/intel/int
