[Mesa-dev] [PATCH 31/47] (0031) i965/fs: Extend thread payload layout to SIMD32.

From: Kevin Rogovin And handle 32-wide payload register reads in fetch_payload_reg(). Change-Id: I7d6b8d5c2fe59d10cf4f0cc5e77455776851d519 --- src/intel/compiler/brw_fs.cpp| 14 +++--- src/intel/compiler/brw_fs.h | 41 +--- src/intel/compiler

[Mesa-dev] [PATCH 21/47] (0021) i965/fs: Remove program key argument from generator.

From: Kevin Rogovin Change-Id: I2689f20b6b217dae853898a72cfb2c716c7ab6b6 --- src/intel/compiler/brw_fs.cpp | 4 ++-- src/intel/compiler/brw_fs.h| 2 -- src/intel/compiler/brw_fs_generator.cpp| 3 +-- src/intel/compiler/brw_shader.cpp | 2 +- src/intel/co

[Mesa-dev] [PATCH 45/47] (0043) intel/blorp: State setup for SIMD32 fragment shaders.

From: Francisco Jerez Change-Id: I00ec9f7bc89b1cd7aea9d4572c75eacd09443dc8 --- src/intel/blorp/blorp_genX_exec.h | 19 +++ 1 file changed, 19 insertions(+) diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h index 593521b..af591c7 100644 --- a/src

[Mesa-dev] [PATCH 01/47] (0001) HACK: i965/fs: Disable SIMD32 dispatch for fragment with discard.

From: Kevin Rogovin Change-Id: I860701f7cc0d7d8698a67102f25d41c4d4aed095 --- src/intel/compiler/brw_fs_nir.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 9698a01..1705cd6 100644 --- a/src/intel/compiler/brw_f

[Mesa-dev] [PATCH 15/47] (0016) i965/fs: Fix FB write message control codegen for SIMD32.

From: Kevin Rogovin Change-Id: I1fc99c9726269fc5da982d91bd7216228a111b1a --- src/intel/compiler/brw_fs_generator.cpp | 50 + 1 file changed, 32 insertions(+), 18 deletions(-) diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_genera

[Mesa-dev] [PATCH 44/47] (0042) i965: State setup for SIMD32 fragment shaders.

From: Kevin Rogovin Change-Id: I9d8b1758ec4f02c86a7982c518c01a0d17fa3c62 --- Notes.txt | 26 +++ src/mesa/drivers/dri/i965/genX_state_upload.c | 37 +++ 2 files changed, 63 insertions(+) diff --git a/Notes.txt b/Notes.t

[Mesa-dev] [PATCH 40/47] (0038) i965/fs: Fix unlit centroid workaround for SIMD32.

From: Francisco Jerez Change-Id: I277b2eebbdd82a9ee9cebc523c2c0574d4cb1296 --- src/intel/compiler/brw_fs_visitor.cpp | 22 -- 1 file changed, 8 insertions(+), 14 deletions(-) diff --git a/src/intel/compiler/brw_fs_visitor.cpp b/src/intel/compiler/brw_fs_visitor.cpp index c9

[Mesa-dev] [PATCH 19/47] (0019) i965/fs: Don't enable dual source blending if no fragment outputs are written.

From: Francisco Jerez Prevents a crash in spec@arb_enhanced_layouts@compiler@compile-time-consta...@index.frag. Change-Id: I0d9698733aee7769a1c4b2835fb0027dcb1eed53 --- src/intel/compiler/brw_fs_visitor.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler

[Mesa-dev] [PATCH 08/47] (0009) i965/fs: Add explicit last_rt flag to fb writes orthogonal to eot.

From: Kevin Rogovin Change-Id: I5e70a326820e1252c87af07033c1c4eec1587171 --- src/intel/compiler/brw_fs.cpp | 7 +++ src/intel/compiler/brw_fs_generator.cpp | 6 +- src/intel/compiler/brw_fs_visitor.cpp | 2 ++ src/intel/compiler/brw_ir_fs.h | 2 ++ 4 files changed, 1

[Mesa-dev] [PATCH] Forces color writes to simd32. Original patch from Toni Lönnberg

From: valtteri rantala Change-Id: I9fcac17e609b8647e786f9bd81ec9246b167bbac --- src/intel/compiler/brw_fs.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index c847acd..993d947 100644 --- a/src/intel/comp

[Mesa-dev] [PATCH 41/47] (0039) i965/fs: Fix fs_builder::sample_mask_reg() for 32-wide FS dispatch.

From: Francisco Jerez Change-Id: I29db4abf960d785a4d9eedcf5676cf9b20e07df2 --- src/intel/compiler/brw_fs_builder.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/intel/compiler/brw_fs_builder.h b/src/intel/compiler/brw_fs_builder.h index 4203c8c..7bee2aa 100644 --

[Mesa-dev] [PATCH 09/47] (0010) i965/fs: Fix Gen4-5 FB write AA data payload munging for non-EOT writes.

From: Kevin Rogovin Change-Id: I4404441edead66ed32b7945e4f7d48d1b41fb693 --- src/intel/compiler/brw_fs_generator.cpp | 23 +-- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp in

[Mesa-dev] [PATCH 35/47] (0033) i965/fs: Fix Gen7 compressed source region alignment restriction for SIMD32.

From: Kevin Rogovin Change-Id: I1534c82cdd9c410ce83f7b185dc235569cc3cb3d --- src/intel/compiler/brw_fs.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 5f35a58..b4eb012 100644 --- a/src/intel/compiler/br

[Mesa-dev] [PATCH 47/47] (0044b) Patch fixes

From: Kevin Rogovin Change-Id: Ie24a3406b0f6330dc07426deddfbecadd281ea80 --- Notes.txt | 3 +++ src/intel/blorp/blorp_blit.c | 2 +- src/intel/compiler/brw_fs.cpp | 2 +- 3 files changed, 5 insertions(+), 2 deletions(-) diff --git a/Notes.txt b/Notes.txt index dcb394f..cd62

[Mesa-dev] [PATCH 30/47] (0030) i965/fs: Wrap FS payload register look-up in a helper function.

From: Kevin Rogovin Change-Id: Idb7f7841ee50ce603b7dde750e7051ad67baf37f --- src/intel/compiler/brw_fs.cpp | 10 +- src/intel/compiler/brw_fs.h | 14 ++ src/intel/compiler/brw_fs_visitor.cpp | 12 +--- 3 files changed, 24 insertions(+), 12 deletions(

[Mesa-dev] [PATCH 26/47] (0026) i965/fs: Disable opt_sampler_eot() in 32-wide dispatch.

From: Kevin Rogovin Change-Id: I277c38e136d2f562b8b19d368aa125c44d4e95f8 --- src/intel/compiler/brw_fs.cpp | 2 +- src/intel/compiler/brw_fs_generator.cpp | 5 + 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.

[Mesa-dev] [PATCH 17/47] (0018) i965/fs: Rework FB write header setup for SIMD32 and better scheduling.

From: Kevin Rogovin Change-Id: If4f218fafc95e1e8ddae94d8a22e74c3471f05f8 --- Notes.txt | 3 + src/intel/compiler/brw_fs.cpp | 109 ++-- src/intel/compiler/brw_fs_generator.cpp | 81 +++- 3 files changed, 1

[Mesa-dev] [PATCH 27/47] (0027) i965: Add plumbing for shader time in 32-wide FS dispatch mode.

From: Kevin Rogovin Change-Id: I39b29a5350bd9b0454285ea35c5e87d1e126db3a --- src/intel/blorp/blorp.c | 2 +- src/intel/compiler/brw_compiler.h | 1 + src/intel/compiler/brw_fs.cpp | 2 +- src/intel/vulkan/anv_pipeline.c | 2 +- src/mesa/drivers/dri/i965/br

[Mesa-dev] [PATCH 23/47] (0023) i965/ir: Expose multiple flag registers to the IR.

From: Kevin Rogovin Change-Id: I90414e75eabd3c4dbdd85547543e0ab12338107d Signed-off-by: valtteri rantala --- src/intel/compiler/brw_fs_generator.cpp | 2 ++ src/intel/compiler/brw_reg.h| 5 ++--- src/intel/compiler/brw_shader.h | 4 ++-- 3 files changed, 6 insertions(+), 5 d

[Mesa-dev] [PATCH 37/47] (0035) i965/fs: Fix Gen4-5 interpolation setup for SIMD32.

From: Francisco Jerez Change-Id: Ic287fb614350f12b629b38c6b0dedb0ec28684ea --- src/intel/compiler/brw_fs_visitor.cpp | 44 +-- 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/src/intel/compiler/brw_fs_visitor.cpp b/src/intel/compiler/brw_fs_visito

[Mesa-dev] [PATCH 39/47] (0037) i965/fs: Fix the MOV_DISPATCH_TO_FLAGS instruction for SIMD32.

From: Kevin Rogovin Change-Id: I9f434efa2197239ccff165e8d7aaae0dd833e966 Signed-off-by: valtteri rantala --- src/intel/compiler/brw_fs_generator.cpp | 23 ++- 1 file changed, 10 insertions(+), 13 deletions(-) diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel

[Mesa-dev] [PATCH 43/47] (0041) i965/fs: Build 32-wide FS shaders.

From: Kevin Rogovin Change-Id: Ic93cbc5a6e7d2ae76b733078231731ee6ccb523c Signed-off-by: valtteri rantala --- src/intel/compiler/brw_compiler.h | 4 ++ src/intel/compiler/brw_fs.cpp | 80 +-- 2 files changed, 64 insertions(+), 20 deletions(-) diff --git

[Mesa-dev] [PATCH 29/47] (0029) i965/fs: Use fs_regs instead of brw_regs in the unlit centroid workaround.

From: Francisco Jerez Change-Id: I3b9bda911b04eb3046f359b5aea688a8f8e974ec --- src/intel/compiler/brw_fs_visitor.cpp | 24 src/intel/compiler/brw_ir_fs.h| 1 - 2 files changed, 12 insertions(+), 13 deletions(-) diff --git a/src/intel/compiler/brw_fs_visitor.cpp

[Mesa-dev] [PATCH 33/47] (0032b) Fixes to compile

From: Kevin Rogovin Change-Id: Ifff2bb9d7daa0243af532baefafa29a10c679ea1 --- Notes.txt | 3 +++ src/intel/compiler/brw_fs.cpp | 6 +++--- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/Notes.txt b/Notes.txt index 8be39d9..1142bf7 100644 --- a/Notes.txt +++ b/N

[Mesa-dev] [PATCH 34/47] (0018) notes on why fix needed

From: Kevin Rogovin Change-Id: I8f57950867ab82b28838b5423dc90724ad5e1fb6 --- Notes.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Notes.txt b/Notes.txt index 1142bf7..e1ad8dc 100644 --- a/Notes.txt +++ b/Notes.txt @@ -6,7 +6,8 @@ Patch 0011 i965/eu: Emit JMPI with exec

[Mesa-dev] [PATCH 42/47] (0040) i965/fs: Fix nir_intrinsic_load_helper_invocation for SIMD32.

From: Francisco Jerez Change-Id: I66c027d15ad40ae8f9a34151c949cdff18711104 --- src/intel/compiler/brw_fs_nir.cpp | 14 +- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 704c90e..8e47a1a 100644

[Mesa-dev] [PATCH 32/47] (0032) i965/fs: Implement 32-wide FS payload setup on Gen6+.

From: Kevin Rogovin Change-Id: I4736a030a96cc97f2b65efd09c62eddbc47144b2 --- src/intel/compiler/brw_fs.cpp | 124 +++--- 1 file changed, 57 insertions(+), 67 deletions(-) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index b8bbdce

[Mesa-dev] [PATCH 28/47] (0028) i965/fs: Simplify fs_visitor::emit_samplepos_setup.

From: Francisco Jerez Change-Id: Ifd4b1b94ca896445f83855bb7b074be5bda5b6a2 --- src/intel/compiler/brw_fs.cpp | 25 ++--- 1 file changed, 6 insertions(+), 19 deletions(-) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 5e2610c..230460c 100644

[Mesa-dev] [PATCH 13/47] (0014) i965/fs: Fix fs_inst::flags_written() for Gen4-5 FB writes

From: Kevin Rogovin Change-Id: I827f83105515957355409f7b924aea3532d6e37c Signed-off-by: valtteri rantala --- src/intel/compiler/brw_fs.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index be5583f..d834d0d 100644 --- a/src/in

[Mesa-dev] [PATCH 38/47] (0036) i965/fs: Fix Gen6+ interpolation setup for SIMD32.

From: Francisco Jerez Change-Id: Iba97ac69265e4ea186bccd064d157e580c33d8a1 --- src/intel/compiler/brw_fs_visitor.cpp | 106 +- 1 file changed, 54 insertions(+), 52 deletions(-) diff --git a/src/intel/compiler/brw_fs_visitor.cpp b/src/intel/compiler/brw_fs_visito

[Mesa-dev] [PATCH 14/47] (0015) i965/fs: Fix implied_mrf_writes() for headerless FB writes.

From: Francisco Jerez Change-Id: Idde69db6d4e4a9c30060dd7e0c4f9a9da2d6dcda --- src/intel/compiler/brw_fs.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index d834d0d..ac0dee0 100644 --- a/src/intel/compiler/

[Mesa-dev] [PATCH 24/47] (0024) i965/fs: interpolateAt fixes for SIMD32.

From: Kevin Rogovin Change-Id: Ibbaf9618e489d0c891e2bb27024597105665c461 Signed-off-by: valtteri rantala --- src/intel/compiler/brw_fs.cpp | 3 ++- src/intel/compiler/brw_fs_generator.cpp | 7 --- src/intel/compiler/brw_fs_nir.cpp | 18 ++ 3 files changed,

[Mesa-dev] [PATCH 12/47] (0013) i965/eu: Return new instruction to caller from brw_fb_WRITE().

From: Francisco Jerez Change-Id: Ia8bc29079b2ce74352498555ca4509105f57e557 --- src/intel/compiler/brw_eu.h | 20 ++-- src/intel/compiler/brw_eu_emit.c | 24 +--- 2 files changed, 23 insertions(+), 21 deletions(-) diff --git a/src/intel/compiler/brw_eu.h

[Mesa-dev] [PATCH 16/47] (0017) i965/fs: Fix logical FB write lowering for SIMD32.

From: Francisco Jerez Change-Id: I660a7b68549d60dfdd44fc83bcb74f4aeee86af8 --- src/intel/compiler/brw_fs.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index ac0dee0..edf0b74 100644 --- a/src/intel/compil

[Mesa-dev] [PATCH 03/47] (0004) i965/eu: Remove brw_codegen::compressed_stack.

From: Kevin Rogovin Change-Id: I816321578c74c21cd6ef24a5219ef05cc9085fd4 --- src/intel/compiler/brw_eu.h | 1 - 1 file changed, 1 deletion(-) diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h index 120a74f..2655cdb 100644 --- a/src/intel/compiler/brw_eu.h +++ b/src/intel/co

[Mesa-dev] [PATCH 10/47] (0011) i965/eu: Emit JMPI with exec_size 1.

From: Kevin Rogovin Change-Id: I058bbd6ffba3a0356164c4443f101e9f9b65895c --- Notes.txt | 6 ++ 1 file changed, 6 insertions(+) create mode 100644 Notes.txt diff --git a/Notes.txt b/Notes.txt new file mode 100644 index 000..2038eb8 --- /dev/null +++ b/Notes.txt @@ -0,0 +1,6 @@ +Patch 00

[Mesa-dev] [PATCH 36/47] (0034) i965/fs: Fix sample id setup for SIMD32.

From: Kevin Rogovin Change-Id: Ib78ee6ea9b3d7a743bb3f58e65deda977fda9347 --- src/intel/compiler/brw_fs.cpp | 27 ++- 1 file changed, 18 insertions(+), 9 deletions(-) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index b4eb012..683c63a 100644

[Mesa-dev] [PATCH 05/47] (0006) i965/fs: Fix codegen of FS_OPCODE_SET_SAMPLE_ID for SIMD32.

From: Kevin Rogovin Change-Id: Iaf57c6a08c07984ac887329fb794ac9f50bb00dd --- src/intel/compiler/brw_fs_generator.cpp | 24 +--- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp i

[Mesa-dev] [PATCH 11/47] (0012) i965/fs: Fix fs_inst::size_read() for send-from-MRF FB writes.

From: Francisco Jerez Change-Id: I12f4844c513ab7241859cb65cf74a53f2f7dcb7e --- src/intel/compiler/brw_fs.cpp | 9 + 1 file changed, 9 insertions(+) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 7e72024..be5583f 100644 --- a/src/intel/compiler/brw_fs.cp

[Mesa-dev] [PATCH 02/47] (0002) i965/fs: Replace CINTERP virtual opcode with ATTR file.

From: Kevin Rogovin Change-Id: Ie75461470039c0fc04fbd5a4a2f65c7c6d623c21 Signed-off-by: valtteri rantala --- src/intel/compiler/brw_eu_defines.h | 1 - src/intel/compiler/brw_fs.cpp | 27 +-- src/intel/compiler/brw_fs.h | 2 +- src/intel/compi

[Mesa-dev] [PATCH 25/47] (0025) i965/fs: Mark LINTERP opcode as writing accumulator implicitly on pre-Gen7.

From: Francisco Jerez Change-Id: I2baf1b2e407b1034a0d23b4e558f7caf9aa10248 --- src/intel/compiler/brw_shader.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_shader.cpp b/src/intel/compiler/brw_shader.cpp index 954f8b0..8e016f2 100644 --- a/src/in

[Mesa-dev] [PATCH 04/47] (0005) i965/eu: Fix pixel interpolator queries for SIMD32.

From: Kevin Rogovin Change-Id: I9fe96ce365496e9f40da0ed9ae1ebbe66349ac05 --- src/intel/compiler/brw_eu_emit.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c index ee5a048..1a8c008 100644 --- a/src/intel/co

[Mesa-dev] [PATCH 18/47] (0018b) Fix for Patch 0018; I have no idea if this is a real fix or not

From: Kevin Rogovin Change-Id: Ic5948415e0b4d6799b6a88ac507c1999ccb1df39 --- src/intel/compiler/brw_fs.cpp | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 121f9f8..b089b79 100644 --- a/src/intel/compiler

[Mesa-dev] [PATCH 06/47] (0007) i965/fs: Fix up PIXEL_X/Y.

From: Kevin Rogovin Change-Id: I5b0fe731c2a6f96190d3058c4f30d1f9f5201e1a Signed-off-by: valtteri rantala --- src/intel/compiler/brw_fs_generator.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp index cb3

[Mesa-dev] [PATCH 07/47] (0008) i965/fs: Prevent SIMD32 compilation on Gen4-6 with nonuniform control flow.

From: Francisco Jerez The hardware's control flow logic is 16-wide so we're out of luck here. Change-Id: I788fd3d2cc74b53ce3304e250f709b82f95624d8 --- src/intel/compiler/brw_fs_nir.cpp | 8 1 file changed, 8 insertions(+) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/com

[Mesa-dev] [PATCH 22/47] (0022) i965/fs: Fix FB read header setup for SIMD32.

From: Francisco Jerez Change-Id: Ic167e704a5eeed8f398e5cf63feaa030b95ac84f --- src/intel/compiler/brw_fs.cpp | 16 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 1fdde34..7aeaf3b 100644 --- a/src

[Mesa-dev] [PATCH 20/47] (0020) i965/fs: Don't assume that payload is a VGRF in EOT send high-reg hack.

From: Francisco Jerez Change-Id: I7ead239b57bf959a25de5d591dfecfa0e672ea8c --- src/intel/compiler/brw_fs_reg_allocate.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_fs_reg_allocate.cpp b/src/intel/compiler/brw_fs_reg_allocate.cpp index ec8e116..82

[Mesa-dev] [PATCH 46/47] (0044) HACK: i965/fs: Enable SIMD32 codegen for BLORP fragment shaders.

From: Francisco Jerez And init blorp blit shader info name. Change-Id: I8e835ae618338f85f0e11a0c44f6e903fc9c96ee --- src/intel/blorp/blorp_blit.c | 1 + src/intel/compiler/brw_fs.cpp | 4 +++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/src/intel/blorp/blorp_blit.c b/src/inte