[Mesa-dev] [PATCH] ac/nir: fix txf_ms with an offset

Seems to fix some hair artifacts in Max Payne 3: https://github.com/daniel-schuermann/mesa/issues/76 Signed-off-by: Rhys Perry Fixes: f4e499ec791 ('radv: add initial non-conformant radv vulkan driver') --- src/amd/common/ac_nir_to_llvm.c | 4 ++-- 1 file changed, 2 insertions(+), 2

Re: [Mesa-dev] [PATCH] ac/nir: mark some texture intrinsics as convergent

r than that: > > Reviewed-by: Marek Olšák > > Marek > > On Fri, May 31, 2019 at 11:53 AM Rhys Perry wrote: >> >> Otherwise LLVM can sink them and their texture coordinate calculations >> into divergent branches. >> >> v2: simplify the conditions on whic

[Mesa-dev] [PATCH] ac/nir: mark some texture intrinsics as convergent

Otherwise LLVM can sink them and their texture coordinate calculations into divergent branches. v2: simplify the conditions on which the intrinsic is marked as convergent v3: only mark as convergent in FS and CS with derivative groups Cc: Signed-off-by: Rhys Perry --- src/amd/common

[Mesa-dev] [PATCH] ac/nir: mark some texture intrinsics as convergent

Otherwise LLVM can sink them and their texture coordinate calculations into divergent branches. v2: simplify the conditions on which the intrinsic is marked as convergent Cc: Signed-off-by: Rhys Perry Reviewed-By: Bas Nieuwenhuizen --- src/amd/common/ac_nir_to_llvm.c | 12 1

Re: [Mesa-dev] [PATCH] ac/nir: mark some texture intrinsics as convergent

s implicitly always 0. > > On Thu, May 30, 2019 at 2:26 PM Bas Nieuwenhuizen > wrote: > > > > On Thu, May 30, 2019 at 6:50 PM Rhys Perry wrote: > > > > > > Otherwise LLVM can sink them and their texture coordinate calculations > > > into

[Mesa-dev] [PATCH] ac/nir: mark some texture intrinsics as convergent

Otherwise LLVM can sink them and their texture coordinate calculations into divergent branches. Cc: Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 29 + 1 file changed, 29 insertions(+) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common

[Mesa-dev] [PATCH] radv: fix some compiler warnings

Fixes -Woverflow warnings with GCC 9.1.1 Signed-off-by: Rhys Perry --- src/amd/vulkan/si_cmd_buffer.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c index aae8d578c10..d87c00b94e9 100644 --- a/src/amd

Re: [Mesa-dev] [PATCH 1/2] radeonsi: use new atomic LLVM helpers

The patch this depends on, "ac,ac/nir: use a better sync scope for shared atomics", has been pushed: https://gitlab.freedesktop.org/mesa/mesa/commit/bd4c661ad08e772fdccb562ffbb2f45705c4fec8 On Fri, 26 Apr 2019 at 21:41, Marek Olšák wrote: > > From: Marek Olšák > > This depends on "ac,ac/nir: use

[Mesa-dev] [PATCH v3] radv: fix set_output_usage_mask() with composite and 64-bit types

omp != 0 v3: fix 64-bit variables when comp != 0, again Signed-off-by: Rhys Perry Cc: 19.0 --- src/amd/vulkan/radv_shader_info.c | 21 + 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/src/amd/vulkan/radv_shader_info.c b/src/amd/vulkan/radv_shader_info.c index

[Mesa-dev] [PATCH v2] radv: fix set_output_usage_mask() with composite and 64-bit types

n comp != 0 Signed-off-by: Rhys Perry Cc: 19.0 --- src/amd/vulkan/radv_shader_info.c | 23 +++ 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/src/amd/vulkan/radv_shader_info.c b/src/amd/vulkan/radv_shader_info.c index 932a1852266..63ee25ab7c9 100644 --- a/src

[Mesa-dev] [PATCH] radv: fix set_output_usage_mask() with composite and 64-bit types

It previously used var->type instead of deref_instr->type and didn't handle 64-bit outputs. This fixes lots of transform feedback CTS tests involving transform feedback and geometry shaders (mostly dEQP-VK.transform_feedback.fuzz.random_geometry.*) Signed-off-by: Rhys Perry Cc: 19.

[Mesa-dev] [PATCH] ac, ac/nir: use a better sync scope for shared atomics

+0.0%) RotTR/tomb (4K, VeryHigh settings, FXAA), avg FPS : 42.5 -> 43.0 (+1.17%) RotTR/valley (4K, VeryHigh settings, FXAA), avg FPS : 40.7 -> 41.6 (+2.21%) Warhammer II/fallen, avg FPS : 31.63 -> 31.83 (+0.63%) Warhammer II/skaven

[Mesa-dev] [PATCH] nir,ac/nir: fix cube_face_coord

Seems it was missing the "/ ma + 0.5" and the order was swapped. Fixes: a1a2a8dfda7b9cac7e ('nir: add AMD_gcn_shader extended instructions') Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 11 +-- src/compiler/nir/nir_opcodes.py | 21 ++

Re: [Mesa-dev] [PATCH 00/38] radv, ac: 16-bit and 8-bit arithmetic and 8-bit storage

dle 64-bit varyings. So not all of them would work even if VK_FORMAT_R64_SFLOAT was a implemented vertex format. On Mon, 18 Feb 2019 at 08:53, Samuel Pitoiset wrote: > > > On 2/16/19 1:21 AM, Rhys Perry wrote: > > This series add support for: > > - VK_KHR_shader_float16_int8 >

Re: [Mesa-dev] [PATCH v2 06/41] ac/nir: fix 16-bit ssbo stores

s this fix anything know? There is a 16-bit version of tbuffer.store, > maybe we should use it? > > On 2/16/19 1:21 AM, Rhys Perry wrote: > > Signed-off-by: Rhys Perry > > --- > > src/amd/common/ac_nir_to_llvm.c | 2 ++ > > 1 file changed, 2 insertions(+) >

[Mesa-dev] [PATCH v2 31/41] ac/nir: implement 16-bit pack/unpack opcodes

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 24 1 file changed, 24 insertions(+) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index bad1c2a990e..f6ad1aa7e77 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd

[Mesa-dev] [PATCH v2 32/41] ac/nir: add 8-bit types to glsl_base_to_llvm_type

v2: remove 16-bit additions and rebase Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index f6ad1aa7e77..defbfdf4297 100644 --- a/src/amd/common

[Mesa-dev] [PATCH v2 25/41] nir: make bitfield_reverse and ifind_msb work with all integers

Signed-off-by: Rhys Perry --- src/compiler/nir/nir_opcodes.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/compiler/nir/nir_opcodes.py b/src/compiler/nir/nir_opcodes.py index dc4cd9ac63d..0f40bd6c548 100644 --- a/src/compiler/nir/nir_opcodes.py +++ b/src/compiler

[Mesa-dev] [PATCH v2 33/41] ac/nir, radv: create an array of varying output types

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 68 +++ src/amd/common/ac_shader_abi.h| 1 + src/amd/vulkan/radv_nir_to_llvm.c | 3 ++ 3 files changed, 72 insertions(+) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common

[Mesa-dev] [PATCH v2 35/41] radv: store all fragment shader inputs as f32

v2: rebase Signed-off-by: Rhys Perry --- src/amd/vulkan/radv_nir_to_llvm.c | 14 -- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c index 2002a744545..01b8b097ea1 100644 --- a/src/amd/vulkan

Re: [Mesa-dev] [PATCH v2 37/41] radv, ac: implement 16-bit interpolation

This patch can be ignored. I forgot to delete it and it ended up getting sent. "[PATCH v2 37/41] WIP: radv, ac: implement 16-bit interpolation" is the correct one. On Sat, 16 Feb 2019 at 00:23, Rhys Perry wrote: > > v2: add to patch series > > Signed-off-by: Rhys Perry &

[Mesa-dev] [PATCH v2 34/41] ac/nir: store all outputs as f32

v2: rebase v2: fix 64-bit visit_load_var() Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 14 ++ src/amd/vulkan/radv_nir_to_llvm.c | 22 +- 2 files changed, 19 insertions(+), 17 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src

[Mesa-dev] [PATCH v2 37/41] WIP: radv, ac: implement 16-bit interpolation

v2: add to patch series Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 33 +--- src/amd/common/ac_llvm_build.h | 3 ++- src/amd/common/ac_nir_to_llvm.c | 14 +++--- src/amd/vulkan/radv_nir_to_llvm.c| 27

[Mesa-dev] [PATCH v2 37/41] radv, ac: implement 16-bit interpolation

v2: add to patch series Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 33 +--- src/amd/common/ac_llvm_build.h | 3 ++- src/amd/common/ac_nir_to_llvm.c | 14 +++--- src/amd/vulkan/radv_nir_to_llvm.c| 27

[Mesa-dev] [PATCH v2 38/41] WIP: ac, radv: run LLVM's SLP vectorizer

v2: rebase v2: move LLVMAddSLPVectorizePass to after LLVMAddEarlyCSEMemSSAPass v2: run unconditionally on GFX9 and later v2: mark as WIP because it can make 32-bit code much worse Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_util.c | 8 ++-- 1 file changed, 6 insertions(+), 2

[Mesa-dev] [PATCH v2 39/41] ac/nir: generate better code for nir_op_f2f16_rtz

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 939b8eb13de..8bfc63958ca 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/common

[Mesa-dev] [PATCH v2 41/41] radv, docs: expose float16, int16 and int8 features and extensions

v2: rebase v2: mark VK_KHR_8bit_storage as DONE in features.txt Signed-off-by: Rhys Perry --- docs/features.txt | 2 +- src/amd/vulkan/radv_device.c | 17 + src/amd/vulkan/radv_extensions.py | 4 src/amd/vulkan/radv_shader.c | 3 +++ 4 files

[Mesa-dev] [PATCH v2 40/41] ac/nir: have nir_op_f2f16 round to zero

In the hope that one day LLVM will then be able to generate code with vectorized v_cvt_pkrtz_f16_f32 instructions. Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common

[Mesa-dev] [PATCH v2 28/41] ac/nir: implement 8 and 16 bit ac_build_imsb

v2: fix C++ style comment Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 4 1 file changed, 4 insertions(+) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index ec87a7b9343..c986f800fa4 100644 --- a/src/amd/common/ac_llvm_build.c +++ b/src/amd

[Mesa-dev] [PATCH v2 10/41] ac/nir: make ac_build_clamp work on all bit sizes

v2: don't use ac_get_zerof() and ac_get_onef() Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 13 + 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index b53d9c7ff8c..667f9700764 1

[Mesa-dev] [PATCH v2 14/41] ac/nir: make ac_build_fdiv support 16-bit floats

v2: don't use ac_get_onef() Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index 23e454385d7..fb871a47400 100644 --- a/src/amd/common/ac_llvm_bu

[Mesa-dev] [PATCH v2 21/41] ac/nir: implement 16-bit shifts

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 9 +++-- 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 75bb19031bf..bad1c2a990e 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd

[Mesa-dev] [PATCH v2 11/41] ac/nir: make ac_build_fract work on all bit sizes

Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 13 +++-- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index 667f9700764..db937eb66fb 100644 --- a/src/amd/common/ac_llvm_build.c +++ b/src/amd

[Mesa-dev] [PATCH v2 16/41] ac/nir: implement half-float nir_op_frsq

v2: don't use ac_get_onef() Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index cba0cec3e8f..8b0e07d2930 100644 --- a/src/amd/c

[Mesa-dev] [PATCH v2 15/41] ac/nir: implement half-float nir_op_frcp

v2: don't use ac_get_onef() Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 741059b5f1a..cba0cec3e8f 100644 --- a/src/amd/c

[Mesa-dev] [PATCH v2 18/41] radv: lower 16-bit flrp

Signed-off-by: Rhys Perry --- src/amd/vulkan/radv_shader.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index 1dcb0606246..adba730ad8b 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -53,6 +53,7

[Mesa-dev] [PATCH v2 17/41] ac/nir: implement half-float nir_op_ldexp

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 8b0e07d2930..0e5946dfdb3 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/common

[Mesa-dev] [PATCH v2 26/41] ac/nir: make ac_find_lsb work on all bit sizes

v2: don't use ac_get_zero() and ac_int_of_size() Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 33 ++--- 1 file changed, 6 insertions(+), 27 deletions(-) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index aa92c5

[Mesa-dev] [PATCH v2 12/41] ac/nir: make ac_build_isign work on all bit sizes

v2: don't use ac_get_zero(), ac_get_one() and ac_int_of_size() Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 27 --- 1 file changed, 4 insertions(+), 23 deletions(-) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c

[Mesa-dev] [PATCH v2 19/41] ac/nir: support half floats in emit_b2f

This seems to generate fine code, even though the IR is a bit ugly. Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 14 ++ 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index

[Mesa-dev] [PATCH v2 27/41] ac/nir: make ac_build_umsb work on all bit sizes

v2: don't use ac_get_zero() and ac_int_of_size() Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 38 +++--- 1 file changed, 7 insertions(+), 31 deletions(-) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index 61085d

[Mesa-dev] [PATCH v2 24/41] ac/nir: implement 8 and 16 bit ac_build_readlane

v2: don't use ac_int_of_size() Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 12 +++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index 71eaac4b7bd..aa92c55c822 100644 --- a/src/amd/c

[Mesa-dev] [PATCH v2 30/41] ac/nir: make ac_build_bitfield_reverse work on all bit sizes

Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 26 ++ 1 file changed, 6 insertions(+), 20 deletions(-) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index 46738faea9d..dff369aae7f 100644 --- a/src/amd/common/ac_llvm_build.c

[Mesa-dev] [PATCH v2 23/41] ac/nir: implement 16-bit ac_build_ddxy

v2: rebase Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 20 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index fb871a47400..71eaac4b7bd 100644 --- a/src/amd/common

[Mesa-dev] [PATCH v2 29/41] ac/nir: make ac_build_bit_count work on all bit sizes

Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 33 +++-- 1 file changed, 7 insertions(+), 26 deletions(-) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index c986f800fa4..46738faea9d 100644 --- a/src/amd/common

[Mesa-dev] [PATCH v2 36/41] radv: handle all fragment output types

Signed-off-by: Rhys Perry --- src/amd/vulkan/radv_nir_to_llvm.c | 55 --- 1 file changed, 35 insertions(+), 20 deletions(-) diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c index 01b8b097ea1..c46eabf3656 100644 --- a/src/amd/vulkan

[Mesa-dev] [PATCH v2 22/41] compiler/nir: add lowering option for 16-bit ffma

The lowering needs to be disabled for sufficient precision to pass deqp-vk's 16-bit fma test on radv. Signed-off-by: Rhys Perry --- src/broadcom/compiler/nir_to_vir.c| 1 + src/compiler/nir/nir.h| 1 + src/compiler/nir/nir_opt_algebraic.py | 4 +++- src/gallium/dr

[Mesa-dev] [PATCH v2 20/41] ac/nir: make emit_b2i work on all bit sizes

v2: don't use ac_int_of_size() Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 6 +- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index e459001c1cf..75bb19031bf 100644 --- a/src/amd/c

[Mesa-dev] [PATCH v2 05/41] ac/nir: implement 8-bit ssbo stores

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 22 -- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 17d952d1ae8..89a78b43c6f 100644 --- a/src/amd/common/ac_nir_to_llvm.c

[Mesa-dev] [PATCH v2 03/41] ac: add various helpers for float16/int16/int8

v2: remove ac_get_one(), ac_get_zero(), ac_get_onef() and ac_get_zerof() v2: remove ac_int_of_size() Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 55 ++--- src/amd/common/ac_llvm_build.h | 15 +++-- src/amd/common/ac_nir_to_llvm.c | 30

[Mesa-dev] [PATCH v2 09/41] ac/nir: fix 64-bit nir_op_f2f16_rtz

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 691d444db05..741059b5f1a 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/common/ac_nir_to_llvm.c

[Mesa-dev] [PATCH v2 02/41] radv: ensure export arguments are always float

: add support for 16bit input/output') Signed-off-by: Rhys Perry --- src/amd/vulkan/radv_nir_to_llvm.c | 6 +- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c index a8268c44ecf..d3795eec403 100644 --- a/src/

[Mesa-dev] [PATCH v2 07/41] ac/nir: implement 8-bit nir_load_const_instr

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 4 1 file changed, 4 insertions(+) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index b260142c177..f39232b91a1 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/common

[Mesa-dev] [PATCH v2 13/41] ac/nir: make ac_build_fsign work on all bit sizes

v2: don't use ac_get_zerof() and ac_get_onef() Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 16 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index 3b2257e8bf0..23e454385d7 1

[Mesa-dev] [PATCH v2 08/41] ac/nir: implement 8-bit conversions

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index f39232b91a1..691d444db05 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd

[Mesa-dev] [PATCH v2 04/41] ac/nir: implement 8-bit push constant, ssbo and ubo loads

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 37 +++-- 1 file changed, 31 insertions(+), 6 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index bed52490bad..17d952d1ae8 100644 --- a/src/amd/common

[Mesa-dev] [PATCH v2 06/41] ac/nir: fix 16-bit ssbo stores

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 89a78b43c6f..b260142c177 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/common/ac_nir_to_llvm.c

[Mesa-dev] [PATCH v2 01/41] radv: bitcast 16-bit outputs to integers

16-bit outputs are stored as 16-bit floats in the outputs array, so they have to be bitcast. Fixes: b722b29f10d ('radv: add support for 16bit input/output') Signed-off-by: Rhys Perry --- src/amd/vulkan/radv_nir_to_llvm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) di

[Mesa-dev] [PATCH 00/38] radv, ac: 16-bit and 8-bit arithmetic and 8-bit storage

v2: fix C++ style comment Rhys Perry (41): radv: bitcast 16-bit outputs to integers radv: ensure export arguments are always float ac: add various helpers for float16/int16/int8 ac/nir: implement 8-bit push constant, ssbo and ubo loads ac/nir: implement 8-bit ssbo stores ac/nir: fix 1

Re: [Mesa-dev] [PATCH 00/38] radv, ac: 16-bit and 8-bit arithmetic and 8-bit storage

itting this series in four different parts? One for every > extension? Is this doable without too much troubles? > > On 2/12/19 6:02 PM, Rhys Perry wrote: > > It currently requires review (and possibly rebasing). Marek Olšák send > > some feedback for a few of the patches but

Re: [Mesa-dev] [PATCH 00/38] radv, ac: 16-bit and 8-bit arithmetic and 8-bit storage

t wrote: > > What's the status of this? > > On 12/7/18 6:21 PM, Rhys Perry wrote: > > This series add support for: > > - VK_KHR_shader_float16_int8 > > - VK_AMD_gpu_shader_half_float > > - VK_AMD_gpu_shader_int16 > > - VK_KHR_8bit_storage > &

[Mesa-dev] [PATCH 2/2] radv: add missed situations for scissor bug workaround

Signed-off-by: Rhys Perry --- src/amd/vulkan/radv_cmd_buffer.c | 65 src/amd/vulkan/radv_private.h| 2 + 2 files changed, 43 insertions(+), 24 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index f430b4f20dd

[Mesa-dev] [PATCH 1/2] radv: pass radv_draw_info to radv_emit_draw_registers()

Signed-off-by: Rhys Perry --- src/amd/vulkan/radv_cmd_buffer.c | 118 +++ 1 file changed, 58 insertions(+), 60 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index f41d6c0b3e7..f430b4f20dd 100644 --- a/src/amd/vulkan

[Mesa-dev] [PATCH] radv: avoid context rolls when binding graphics pipelines

m the previous pipeline's. v2: ensure late scissor emission is done when radv_emit_rbplus_state() is called v2: make use of cmd_buffer->state.workaround_scissor_bug Signed-off-by: Rhys Perry --- This second version depends on the patch "radv: add missed situations for scis

[Mesa-dev] [PATCH v3 0/5] nvc0: Implement EXT_shader_image_load_formatted

p v3: rebase v3: make use of u_pipe_screen_get_param_defaults v3: move RA code into it's own function Rhys Perry (5): gallium: add support for formatted image loads mesa,glsl: add support for EXT_shader_image_load_formatted st/mesa: add support for EXT_shader_image_load_formatted nv

[Mesa-dev] [PATCH v3 5/5] nvc0, nv50/ir: enable support for formatted image loads on GM107+

v3: rebase Signed-off-by: Rhys Perry --- src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 3 +-- src/gallium/drivers/nouveau/nvc0/nvc0_screen.c| 3 ++- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen

[Mesa-dev] [PATCH v3 4/5] nv50/ir: use suld.p on GM107+

v3: rebase v3: move RA code into it's own function Signed-off-by: Rhys Perry --- src/gallium/drivers/nouveau/codegen/nv50_ir.h | 4 +++ .../nouveau/codegen/nv50_ir_emit_gm107.cpp| 34 --- .../drivers/nouveau/codegen/nv50_ir_print.cpp | 17 ++ .../drivers/no

[Mesa-dev] [PATCH v3 2/5] mesa, glsl: add support for EXT_shader_image_load_formatted

v3: rebase Signed-off-by: Rhys Perry Reviewed-by: Marek Olšák (v2) --- src/compiler/glsl/ast_to_hir.cpp | 5 + src/compiler/glsl/glsl_parser_extras.cpp | 1 + src/compiler/glsl/glsl_parser_extras.h | 7 +++ src/mesa/main/extensions_table.h | 1 + src/mesa/main

[Mesa-dev] [PATCH v3 3/5] st/mesa: add support for EXT_shader_image_load_formatted

v3: rebase Signed-off-by: Rhys Perry Reviewed-by: Marek Olšák (v2) --- src/mesa/state_tracker/st_extensions.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mesa/state_tracker/st_extensions.c b/src/mesa/state_tracker/st_extensions.c index 4628079260..b713eed969 100644 --- a/src/mesa

[Mesa-dev] [PATCH v3 1/5] gallium: add support for formatted image loads

v3: rebase v3: make use of u_pipe_screen_get_param_defaults Signed-off-by: Rhys Perry --- src/gallium/auxiliary/util/u_screen.c | 1 + src/gallium/docs/source/screen.rst | 1 + src/gallium/drivers/nouveau/nv30/nv30_screen.c | 1 + src/gallium/drivers/nouveau/nv50

Re: [Mesa-dev] [PATCH] radv: avoid context rolls when binding graphics pipelines

1%) (1 extreme from "before" run excluded) Sorry for the noise. On Wed, 16 Jan 2019 at 11:46, Rhys Perry wrote: > > Rise of the Tomb Raider from without to with the change (average of 3 runs): > SpineOfTheMountain: 73.46667 fps -> 73.56667 fps (+0.14%) > Pro

Re: [Mesa-dev] [PATCH] radv: avoid context rolls when binding graphics pipelines

n Wed, 16 Jan 2019 at 00:39, Rhys Perry wrote: > > I did a before/after comparison during development with multiple runs > but only 1 before and after run to produce the numbers I sent. They > seemed to match up well enough to the runs during development, so I > wasn't too conc

Re: [Mesa-dev] [PATCH] radv: avoid context rolls when binding graphics pipelines

do multiple runs of Rise of the Tomb Raider tomorrow and see if I get anything too different. On Wed, 16 Jan 2019 at 00:25, Bas Nieuwenhuizen wrote: > > On Mon, Jan 14, 2019 at 5:12 PM Rhys Perry wrote: > > > > I did and found small improvements in Rise of the Tomb

Re: [Mesa-dev] [PATCH] radv: prevent dirtying of dynamic state when it does not change

I misread some code and forgot to remove it. It was always unrelated to this patch. On Wed, 16 Jan 2019 at 00:22, Bas Nieuwenhuizen wrote: > > On Tue, Jan 15, 2019 at 10:59 PM Rhys Perry wrote: > > > > DXVK often sets dynamic state without actually changing it. > >

[Mesa-dev] [PATCH] radv: prevent dirtying of dynamic state when it does not change

DXVK often sets dynamic state without actually changing it. Signed-off-by: Rhys Perry --- src/amd/vulkan/radv_cmd_buffer.c | 92 ++-- 1 file changed, 76 insertions(+), 16 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c

Re: [Mesa-dev] [PATCH] radv: avoid context rolls when binding graphics pipelines

ster changes a lot more. > > Not sure if that will improve anything though, but I think it's worth to > try? > > On 1/14/19 5:12 PM, Rhys Perry wrote: > > I did and found small improvements in Rise of the Tomb Raider. I > > measured framerates ~104.3% that of witho

Re: [Mesa-dev] [PATCH] radv: avoid context rolls when binding graphics pipelines

This is with Rise of the Tomb Raider's graphics settings set to "High" by the way. On Mon, 14 Jan 2019 at 16:12, Rhys Perry wrote: > > I did and found small improvements in Rise of the Tomb Raider. I > measured framerates ~104.3% that of without the changes for the &

Re: [Mesa-dev] [PATCH] radv: avoid context rolls when binding graphics pipelines

on, 14 Jan 2019 at 16:05, Samuel Pitoiset wrote: > > Did you benchmark? > > On 1/14/19 5:01 PM, Rhys Perry wrote: > > It's common in some applications to bind a new graphics pipeline without > > ending up changing any context registers. > > > > This has

[Mesa-dev] [PATCH] radv: avoid context rolls when binding graphics pipelines

m the previous pipeline's. Signed-off-by: Rhys Perry --- src/amd/vulkan/radv_cmd_buffer.c | 46 +-- src/amd/vulkan/radv_pipeline.c | 217 --- src/amd/vulkan/radv_private.h| 2 + 3 files changed, 150 insertions(+), 115 deletions(-) diff --git a/src/

[Mesa-dev] [PATCH] nir: fix copy-paste error in nir_lower_constant_initializers

Fixes: 393b59e0772e7bf0426bdf61c740752c4e09dde1 ('nir: Rework nir_lower_constant_initializers() to handle functions') --- src/compiler/nir/nir_lower_constant_initializers.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/compiler/nir/nir_lower_constant_initializers.

Re: [Mesa-dev] [PATCH] radv: use dithered alpha-to-coverage

Seems I sent the wrong commit message. It was meant to be: This matches the behaviour of AMDVLK and hides banding. It is also seems to be allowed by the Vulkan spec. Signed-off-by: Rhys Perry On Wed, 9 Jan 2019 at 14:40, Rhys Perry wrote: > > This matches the behaviour of

[Mesa-dev] [PATCH] radv: use dithered alpha-to-coverage

This matches the behaviour of AMDVLK and hides banding TODO: run tests --- src/amd/vulkan/radv_pipeline.c | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 3561d17aaba..26ee59f11dd 100644 --- a/src/am

[Mesa-dev] [PATCH] ac/nir, radv, radeonsi/nir: use correct indices for interpolation intrinsics

Fixes artifacts in World of Warcraft when Multi-sample Alpha-Test is enabled. It also fixes various piglit interpolateAt*() tests with NIR. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106595 Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 2 +- src/amd

[Mesa-dev] [PATCH] radv: allow secondary command buffers to inherit unknown framebuffers

Fixes: f4e499ec79 ('radv: add initial non-conformant radv vulkan driver') Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107986 Signed-off-by: Rhys Perry --- src/amd/vulkan/radv_cmd_buffer.c | 59 ++-- src/amd/vulkan/radv_meta_clear.c | 8

Re: [Mesa-dev] [PATCH 01/38] ac: add various helpers for float16/int16/int8

t; On Fri, Dec 7, 2018 at 12:22 PM Rhys Perry wrote: >> >> Signed-off-by: Rhys Perry >> --- >> src/amd/common/ac_llvm_build.c | 123 ++-- >> src/amd/common/ac_llvm_build.h | 22 +- >> src/amd/common/ac_nir_to_llvm.c | 30

Re: [Mesa-dev] [PATCH 0/2] radv/query: Use 1-bit booleans in query shaders

e_if = nir_if_create(b.shader); Other than that, this looks fine and seems to work correctly on my Vega. With that change (and for what it's worth), this is: Reviewed-by: Rhys Perry On Wed, 19 Dec 2018 at 19:45, Jason Ekstrand wrote: > > When we switched over to 1-bit booleans, the r

Re: [Mesa-dev] [PATCH] nir: create 32-bit bcsel for 32-bit conditions

h I'm a bit surprised your running peephole_select > after lowering booleans. > > On December 18, 2018 18:16:46 Timothy Arceri wrote: > > > Reviewed-by: Timothy Arceri > > > > On 18/12/18 3:16 am, Rhys Perry wrote: > >> Signed-off-by: Rhys Perry > &g

[Mesa-dev] [PATCH] nir: create 32-bit bcsel for 32-bit conditions

Signed-off-by: Rhys Perry --- src/compiler/nir/nir_opt_peephole_select.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/compiler/nir/nir_opt_peephole_select.c b/src/compiler/nir/nir_opt_peephole_select.c index ad9d0abec0..241627ed99 100644 --- a/src/compiler/nir

[Mesa-dev] [PATCH] radv: don't set surf_index for stencil-only images

Fixes: f8d5b377c8b ('radv: set cb base tile swizzles for MRT speedups (v4)') Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108116 Signed-off-by: Rhys Perry --- Unfortunately I was not able to test this patch on a Polaris due to hardware issues. It fixed the deqp-vk tests mentio

[Mesa-dev] [PATCH 1/2] ac: refactor visit_load_buffer

This is so that we can split different types of loads more easily. Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 8 ++-- src/amd/common/ac_nir_to_llvm.c | 80 - src/compiler/nir/nir.h | 2 +- 3 files changed, 44 insertions(+), 46

[Mesa-dev] [PATCH 2/2] ac: split 16-bit ssbo loads that may not be dword aligned

Fixes: 7e7ee826982 ('ac: add support for 16bit buffer loads') Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108114 Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/

Re: [Mesa-dev] [PATCH 2/2] radv: ensure export arguments are always float

3 Dec 2018 at 08:38, Samuel Pitoiset wrote: > > > > On 12/6/18 3:18 PM, Rhys Perry wrote: > > ./deqp-vk > > --deqp-case=dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_int_32_to_16.scalar_uint0_frag > > should crash with something like: > &

Re: [Mesa-dev] [PATCH 2/2] radv: ensure export arguments are always float

Seems my LLVM configuration was messed up and I might have used my distro's LLVM too. On Thu, 13 Dec 2018 at 08:38, Samuel Pitoiset wrote: > > > > On 12/6/18 3:18 PM, Rhys Perry wrote: > > ./deqp-vk > > --deqp-case=dEQP-VK.spirv_

Re: [Mesa-dev] [PATCH] radv: implement VK_EXT_sample_locations

A small number of questions/concerns: - sampleLocationCoordinateRange[1] should probably be set to 0.9375, because of how the sample locations are encoded - gl_SamplePosition doesn't seem like it would return the new sample locations - R_028BD4_PA_SC_CENTROID_PRIORITY_{0,1} isn't updated. I'm

[Mesa-dev] [PATCH 29/38] ac/nir: implement 16-bit pack/unpack opcodes

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 24 1 file changed, 24 insertions(+) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index aac3330c0d..d69135cc25 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd

[Mesa-dev] [PATCH 24/38] ac/nir: make ac_find_lsb work on all bit sizes

Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 31 +-- 1 file changed, 5 insertions(+), 26 deletions(-) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index 6266058b77..754ceda89b 100644 --- a/src/amd/common

[Mesa-dev] [PATCH 38/38] radv: expose float16, int16 and int8 features and extensions

Signed-off-by: Rhys Perry --- src/amd/vulkan/radv_device.c | 17 + src/amd/vulkan/radv_extensions.py | 4 src/amd/vulkan/radv_shader.c | 3 +++ 3 files changed, 24 insertions(+) diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index

[Mesa-dev] [PATCH 31/38] ac/nir, radv: create an array of varying output types

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 68 +++ src/amd/common/ac_shader_abi.h| 1 + src/amd/vulkan/radv_nir_to_llvm.c | 3 ++ 3 files changed, 72 insertions(+) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common

[Mesa-dev] [PATCH 37/38] ac/nir: have nir_op_f2f16 round to zero

In the hope that one day LLVM will then be able to generate code with vectorized v_cvt_pkrtz_f16_f32 instructions. Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common

[Mesa-dev] [PATCH 30/38] ac/nir: add 8-bit and 16-bit types to glsl_base_to_llvm_type

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 8 1 file changed, 8 insertions(+) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index d69135cc25..e4ae85a1ae 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/common

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