make it just return NULL in that case.
Fixes: 84f764a7591 "glxglvnddispatch: Add missing dispatch for GetDriverConfig
Seems sensible to me and thank you for fixing this up after me :) :
Reviewed-by: Hans de Goede
Regards,
Hans
---
Difference between v1 and v2: just modify t
Hi,
On 17-05-17 14:57, Emil Velikov wrote:
On 16 May 2017 at 22:42, Hans de Goede wrote:
Hi,
On 05/16/2017 07:51 PM, Emil Velikov wrote:
Hi Hans
Please poke if patches fall through the cracks.
On 20 March 2017 at 11:05, Hans de Goede wrote:
Together with some fixes to xdriinfo this
Hi,
On 05/16/2017 07:51 PM, Emil Velikov wrote:
Hi Hans
Please poke if patches fall through the cracks.
On 20 March 2017 at 11:05, Hans de Goede wrote:
Together with some fixes to xdriinfo this fixes xdriinfo not working
with glvnd.
Since apps (xdriinfo) expect GetDriverConfig to work
any other dispatch function.
This patch gets the job done, but I'm not really happy with how this
patch turned out, suggestions for a better fix are welcome.
Cc: Kyle Brenneman
Signed-off-by: Hans de Goede
---
src/glx/g_glxglvnddispatchfuncs.c | 18 ++
sr
Hi,
On 22-02-17 12:24, Eric Engestrom wrote:
Signed-off-by: Eric Engestrom
---
v2: make sure the list is in the order C's strcmp uses (Ilia)
Ilia: I used LC_ALL instead of LANG, as it takes precedence
(ie. LANG=C in this script would be overridden by
LC_ALL=en_US in the
Hi Emil,
On 16-02-17 16:38, Emil Velikov wrote:
Hi Hans,
On 6 February 2017 at 13:09, Hans de Goede wrote:
Commit 8bca8d89ef3b ("glx/glvnd: Fix dispatch function names and indices")
fixed the sorting of the array initializers in g_glxglvnddispatchfuncs.c
because FindGLXFunctio
and
"Crypt of the NecroDancer" from Steam not working and possible causes
other problems too.
This commit fixes the last of the sorting errors, fixing these mentioned
games not working.
Fixes: 8bca8d89ef3b ("glx/glvnd: Fix dispatch function names and indices")
Cc: "13.0&
/winsys/kms: Move display target handle lookup to separate
function (v2)
gallium/winsys/kms: Look up the GEM handle after importing a prime FD (v2)
Series looks good to me and is:
Reviewed-by: Hans de Goede
Regards,
Hans
___
mesa-dev mailing list
Hi,
On 12-07-16 14:17, Samuel Pitoiset wrote:
Fixes: 2aa1197 ("nouveau: Add support for SV_WORK_DIM")
Signed-off-by: Samuel Pitoiset
Oops, thanks for catching this.
Reviewed-by: Hans de Goede
Regards,
Hans
---
src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp | 1
Hi,
On 29-06-16 15:41, Ilia Mirkin wrote:
On Wed, Jun 29, 2016 at 8:37 AM, Hans de Goede wrote:
Add support for SV_WORK_DIM for nvc0 and nve4.
Signed-off-by: Hans de Goede
---
Changes in v2
-Use new NVC0_CB_AUX_GRID_INFO(i) version
Changes in v1 (first non RFC posting):
-Adjust
Hi,
On 29-06-16 15:57, Samuel Pitoiset wrote:
On 06/29/2016 03:55 PM, Hans de Goede wrote:
Hi,
On 29-06-16 15:27, Ilia Mirkin wrote:
For those of us who are lazy and forgetful (i.e. me), can you remind
the difference between auto_ptr and unique_ptr? IIRC unique_ptr is
more like scoped_ptr
the patch),
I found the 2nd answer here:
http://stackoverflow.com/questions/3697686/why-is-auto-ptr-being-deprecated
To be the best / clearest explanation and I used that to choose unique_ptr
as replacement.
Regards,
Hans
On Wed, Jun 29, 2016 at 8:38 AM, Hans de Goede wrote:
Signed-off-by
this.
Signed-off-by: Hans de Goede
---
src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 4 ++--
src/gallium/drivers/nouveau/nouveau_compiler.c| 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
b
Add a new WORK_DIM SV type, this is will return the grid dimensions
(1-4) for compute (opencl) kernels.
This is necessary to implement the opencl get_work_dim() function.
Signed-off-by: Hans de Goede
---
Changes in v2:
-No changes
Changes in v1 (first non RFC):
-Document TGSI_SEMANTIC_WORK_DIM
In order to implement get_work_dim() the driver may need to know the
clEnqueueNDRangeKernel() work_dim parameter, so pass it to the driver.
Signed-off-by: Hans de Goede
---
Changes in v2:
-No changes
---
src/gallium/include/pipe/p_state.h| 7 +++
src/gallium/state_trackers
Signed-off-by: Hans de Goede
---
src/gallium/drivers/nouveau/codegen/nv50_ir_util.h | 4
1 file changed, 4 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_util.h
b/src/gallium/drivers/nouveau/codegen/nv50_ir_util.h
index 7b0de85..c619499 100644
--- a/src/gallium
This brings it inline with the other macros like NVC0_CB_AUX_UBO_INFO
and NVC0_CB_AUX_TEX_INFO.
Signed-off-by: Hans de Goede
---
Changes in v2:
-New patch in v2 of this patch-set
---
src/gallium/drivers/nouveau/nvc0/nvc0_context.h | 2 +-
src/gallium/drivers/nouveau/nvc0/nvc0_program.c | 2
gcc6 does not like the trick where we point to one entry before the
array start and then start a while with a pre-increment.
Signed-off-by: Hans de Goede
---
src/gallium/drivers/nouveau/nv30/nv30_transfer.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/src/gallium
Add support for SV_WORK_DIM for nvc0 and nve4.
Signed-off-by: Hans de Goede
---
Changes in v2
-Use new NVC0_CB_AUX_GRID_INFO(i) version
Changes in v1 (first non RFC posting):
-Adjust NVC0_CB_AUX_GRID_SIZE for the extra value in grid-info
-Use NVC0_CB_AUX_GRID_SIZE instead of a hardcoded value
Hi All,
After being busy with other stuff I'm now back to mostly working on
opencl for nouveau. So here is the long overdue v2 of my patchset for
adding WORK_DIM support. See the individual patch commit messages
for the changes from v1.
Regards,
Hans
_
Hi,
On 27-05-16 16:24, Emil Velikov wrote:
Hi Hans,
On 27 May 2016 at 15:06, Hans de Goede wrote:
Make pipe_loader_sw_probe_kms take ownership of the passed in fd,
like pipe_loader_drm_probe_fd does.
The only caller is dri_kms_init_screen which passes in a dupped fd,
just like
Make pipe_loader_sw_probe_kms take ownership of the passed in fd,
like pipe_loader_drm_probe_fd does.
The only caller is dri_kms_init_screen which passes in a dupped fd,
just like dri2_init_screen passes in a dupped fd to
pipe_loader_drm_probe_fd.
Signed-off-by: Hans de Goede
---
src/gallium
Hi,
On 26-05-16 14:43, Ilia Mirkin wrote:
On Thu, May 26, 2016 at 8:41 AM, Hans de Goede wrote:
Hi,
On 26-05-16 04:44, Ilia Mirkin wrote:
For user-supplied constbufs, fileIndex is 0. In that case, when we
subtract 1, we'll end up loading from constbuf offset -16. This is
illegal
Hi,
On 26-05-16 04:44, Ilia Mirkin wrote:
For user-supplied constbufs, fileIndex is 0. In that case, when we
subtract 1, we'll end up loading from constbuf offset -16. This is
illegal, and there are asserts to avoid it. Normally we'd just DCE it,
but no point in generating the instructions if th
as it actually explains the root cause
(I just git bisected down to this commit to get my system to work again),
so lets go with yours, and add my:
Tested-by: Hans de Goede
Regards,
Hans
Cheers,
Daniel
On Sunday, 8 May 2016, Hans de Goede mailto:hdego...@redhat.com>> wrote:
T
Make pipe_loader_sw_probe_kms take ownership of the passed in fd,
like pipe_loader_drm_probe_fd does.
The only caller is dri_kms_init_screen which passes in a dupped fd,
just like dri2_init_screen passes in a dupped fd to
pipe_loader_drm_probe_fd.
Signed-off-by: Hans de Goede
---
src/gallium
failed to add fb %d\n", ret);
return FALSE;
}
}
Signed-off-by: Hans de Goede
---
src/mesa/drivers/dri/i965/brw_meta_fast_clear.c | 4 ++--
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 10 ++
src/mesa/drivers/dri/i965/intel_mipmap_tree.h |
In order to implement get_work_dim() the driver may need to know the
clEnqueueNDRangeKernel() work_dim parameter, so pass it to the driver.
Signed-off-by: Hans de Goede
---
src/gallium/include/pipe/p_state.h| 7 +++
src/gallium/state_trackers/clover/core/kernel.cpp | 1 +
2
Add support for SV_WORK_DIM for nvc0 and nve4.
Signed-off-by: Hans de Goede
---
Changes in v1 (first non RFC posting):
-Adjust NVC0_CB_AUX_GRID_SIZE for the extra value in grid-info
-Use NVC0_CB_AUX_GRID_SIZE instead of a hardcoded value when
uploading the grid info
-Also implement SV_WORK_DIM
Add a new WORK_DIM SV type, this is will return the grid dimensions
(1-4) for compute (opencl) kernels.
This is necessary to implement the opencl get_work_dim() function.
Signed-off-by: Hans de Goede
---
Changes in v1 (first non RFC):
-Document TGSI_SEMANTIC_WORK_DIM in src/gallium/docs/source
Hi,
On 28-04-16 10:13, Pierre Moreau wrote:
On 05:43 PM - Apr 27 2016, Samuel Pitoiset wrote:
On 04/27/2016 05:24 PM, Ilia Mirkin wrote:
On Wed, Apr 27, 2016 at 11:19 AM, Hans de Goede wrote:
Hi,
On 27-04-16 16:49, Ilia Mirkin wrote:
Please add this semantic to src/gallium/docs and
gards,
Hans
Is this the equivalent of gl_LocalGroupSizeARB from
GL_ARB_compute_variable_group_size ? [which is basically the same as
gl_WorkGroupSize, but allowed to be specified at dispatch time]
On Wed, Apr 27, 2016 at 10:43 AM, Hans de Goede wrote:
Add a new WORK_DIM SV type, this is will
In order to implement get_work_dim() the driver may need to know the
clEnqueueNDRangeKernel() work_dim parameter, so pass it to the driver.
Signed-off-by: Hans de Goede
---
src/gallium/include/pipe/p_state.h| 7 +++
src/gallium/state_trackers/clover/core/kernel.cpp | 1 +
2
Add support for SV_WORK_DIM.
Note this is only implemented for nve4 for now, hence this patch
being RFC.
Signed-off-by: Hans de Goede
---
src/gallium/drivers/nouveau/codegen/nv50_ir.h | 1 +
src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 1 +
src/gallium
Add a new WORK_DIM SV type, this is will return the grid dimensions
(1-4) for compute (opencl) kernels.
This is necessary to implement the opencl get_work_dim() function.
Signed-off-by: Hans de Goede
---
src/gallium/auxiliary/tgsi/tgsi_strings.c | 1 +
src/gallium/include/pipe
it should not hurt anything
because the states are dirtied and date will get reuploaded.
Signed-off-by: Samuel Pitoiset
Good to see this cleaned up and the patch looks good to me:
Reviewed-by: Hans de Goede
Regards,
Hans
---
src/gallium/drivers/nouveau/nvc0/nvc0_compute.c | 12
Hi,
On 24-04-16 23:35, Ilia Mirkin wrote:
On Fri, Apr 22, 2016 at 7:06 AM, Hans de Goede wrote:
folding indirect add into offset ld src 0x2dda328 ind0 0x27ca558 add def0
0x27ca558 2
ref value 0x27ca558, indirect -1 -1 file 1 size 4
st u32 # g[%r70+0x0] %r38 (0)
ref value 0x27ca558
Hi,
On 22-04-16 22:11, Ilia Mirkin wrote:
Reviewed-by: Ilia Mirkin
Thanks, pushed.
What about the series to add swizzling suffix support for
the resource argument to LOAD ?
Regards,
Hans
On Fri, Apr 22, 2016 at 7:07 AM, Hans de Goede wrote:
combineLd/St would combine, i.e. :
st
loads / stores as combining indirect loads / stores may break alignment
rules.
Signed-off-by: Hans de Goede
---
Changes in v2:
-Only check for indirect loads/stores in the compute case
---
src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 7 +++
1 file changed, 7 insertions(+)
diff
Hi,
On 21-04-16 17:52, Ilia Mirkin wrote:
On Thu, Apr 21, 2016 at 11:40 AM, Hans de Goede wrote:
Hi,
On 21-04-16 17:09, Samuel Pitoiset wrote:
On 04/21/2016 04:46 PM, Hans de Goede wrote:
Hi,
On 21-04-16 16:28, Ilia Mirkin wrote:
On Thu, Apr 21, 2016 at 9:55 AM, Hans de Goede
Hi,
On 22-04-16 10:37, Marek Olšák wrote:
On Fri, Apr 22, 2016 at 9:23 AM, Hans de Goede wrote:
Hi,
On 22-04-16 09:08, Marek Olšák wrote:
On Thu, Apr 21, 2016 at 7:04 PM, Ilia Mirkin wrote:
[+radeon folk]
Marek, Nicolai, Bas - please have a look at the doc change and let us
know if you
Hi,
On 22-04-16 09:08, Marek Olšák wrote:
On Thu, Apr 21, 2016 at 7:04 PM, Ilia Mirkin wrote:
[+radeon folk]
Marek, Nicolai, Bas - please have a look at the doc change and let us
know if you think this will cause a problem for radeon.
Hans is solving the issue that he wants to swizzle the da
Hi,
On 21-04-16 17:09, Samuel Pitoiset wrote:
On 04/21/2016 04:46 PM, Hans de Goede wrote:
Hi,
On 21-04-16 16:28, Ilia Mirkin wrote:
On Thu, Apr 21, 2016 at 9:55 AM, Hans de Goede
wrote:
combineLd/St would combine, i.e. :
st u32 # g[$r2+0x0] $r2
st u32 # g[$r2+0x4] $r3
into:
st u64
Hi,
On 21-04-16 16:28, Ilia Mirkin wrote:
On Thu, Apr 21, 2016 at 9:55 AM, Hans de Goede wrote:
combineLd/St would combine, i.e. :
st u32 # g[$r2+0x0] $r2
st u32 # g[$r2+0x4] $r3
into:
st u64 # g[$r2+0x0] $r2d
But this is only valid if r2 contains an 8 byte aligned address,
which is
combining indirect loads / stores may break alignment
rules.
Signed-off-by: Hans de Goede
---
src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
b/src/gallium/drivers
LOAD loads upto 4 components from the specified resource starting at
the passed in x value of the 2nd source operand, the y, z and w
components of the address should not be used.
Signed-off-by: Hans de Goede
---
Changes in v2:
-New patch in v2 of this patch-set
---
src/gallium/drivers/nouveau
1st source
operand, which allows using:
LOAD TEMP[0].y, MEMORY[0]., TEMP[0]
And actually getting the desired behavior
Signed-off-by: Hans de Goede
---
Changes in v2:
-Tweaked commit msg a bit
-Add documentation for this to src/gallium/docs/source/tgsi.rst
---
src/gallium/docs/source
"off" later gets set to NULL when the address is immediate, so move the
fetchSrc(1) call to the non-immediate branch of the if-else. This brings
handleLOAD's offset handling inline with how it is done in handleSTORE.
Signed-off-by: Hans de Goede
---
Changes in v2:
-New patch in v
Hi,
On 15-04-16 00:29, Samuel Pitoiset wrote:
On 04/12/2016 12:04 PM, Hans de Goede wrote:
Hi,
On 08-04-16 18:14, Samuel Pitoiset wrote:
On 04/08/2016 12:17 PM, Hans de Goede wrote:
Hi,
On 23-03-16 23:10, Samuel Pitoiset wrote:
Are you sure this won't break compute shaders on
Hi,
On 17-04-16 22:27, Pierre Moreau wrote:
On 04:17 PM - Apr 17 2016, Ilia Mirkin wrote:
On Sun, Apr 17, 2016 at 4:07 PM, Pierre Moreau wrote:
Ping :-)
On 10:56 PM - Mar 19 2016, Pierre Moreau wrote:
Generating a `cvt u32 $r0 u64 $r1d` or a `cvt u64 $r0d u32 $r2` makes the GPU
unhappy. Ins
Hi,
On 15-04-16 00:01, Samuel Pitoiset wrote:
On 04/14/2016 08:03 PM, Pierre Moreau wrote:
On 01:56 AM - Apr 13 2016, Samuel Pitoiset wrote:
Similar to surfaces validation for compute shaders.
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/nvc0/nvc0_program.c | 4 +++-
Hi,
On 08-04-16 18:14, Samuel Pitoiset wrote:
On 04/08/2016 12:17 PM, Hans de Goede wrote:
Hi,
On 23-03-16 23:10, Samuel Pitoiset wrote:
Are you sure this won't break compute shaders on fermi?
Could you please double-check that?
I just checked:
lspci:
01:00.0 VGA compatible contr
Add missing PIPE_SHADER_CAP_INTEGERS for frag shaders to
nv30_screen_get_shader_param().
Signed-off-by: Hans de Goede
---
src/gallium/drivers/nouveau/nv30/nv30_screen.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/gallium/drivers/nouveau/nv30/nv30_screen.c
b/src/gallium/drivers
Hi,
On 08-04-16 18:06, Hans de Goede wrote:
Hi,
On 08-04-16 17:45, Ilia Mirkin wrote:
On Fri, Apr 8, 2016 at 11:28 AM, Hans de Goede wrote:
When dealing with non vector variables the llvm register allocator
will use TEMP[0].x then TEMP[0].y, etc.
When loading something from a global buffer
Hi,
On 08-04-16 17:45, Ilia Mirkin wrote:
On Fri, Apr 8, 2016 at 11:28 AM, Hans de Goede wrote:
When dealing with non vector variables the llvm register allocator
will use TEMP[0].x then TEMP[0].y, etc.
When loading something from a global buffer it will calculate the
address to use, and
Hi,
On 08-04-16 17:02, Ilia Mirkin wrote:
On Fri, Apr 8, 2016 at 5:27 AM, Hans de Goede wrote:
Hi,
On 07-04-16 15:58, Ilia Mirkin wrote:
That's wrong.
It used to work with the old RES[] code and if one cannot specify
a source swizzle, then how can I do something like
LOAD TEMP
der
[9/9] pass: 9 /
after:
./piglit run -o shader -t '.*arb_shader_storage_buffer_object.*' results/shader
[9/9] pass: 9 /
Signed-off-by: Hans de Goede
---
Changes in v2:
-New patch in v2 of patch-set to re-enable support for global opencl buffers
---
src/gallium/drivers/nouveau/codegen/
RY[0]., TEMP[0]
Regards,
Hans
On Thu, Apr 7, 2016 at 9:27 AM, Hans de Goede wrote:
The llvm TGSI backend does things like:
Expecting the data at address TEMP[0].x to get loaded to
TEMP[0].y. Before this commit the data at TEMP[0].x + 4 would be
loaded instead. This commit fixes this.
S
The llvm TGSI backend does things like:
LOAD TEMP[0].y, MEMORY[0]., TEMP[0].x
Expecting the data at address TEMP[0].x to get loaded to
TEMP[0].y. Before this commit the data at TEMP[0].x + 4 would be
loaded instead. This commit fixes this.
Signed-off-by: Hans de Goede
---
src/gallium
Hi Ilia
On 20-03-16 21:17, Ilia Mirkin wrote:
Hi Nicolai,
Looks like this results in uninitialized formats when parsing text, so
a shader which looks like this:
I already have a fix for this ready:
https://cgit.freedesktop.org/~jwrdegoede/mesa/commit/?id=e0e4b87dcc990fa829ca88ca4ff82881c7585
ion
due to trying to access the now always zero-sized resources vector.
Disable all the dead code.
Signed-off-by: Hans de Goede
---
Changes in v2:
-Split out assert() on getFile() != BUFFER/MEMORY into a separate patch
-Split out removal of TGSI_RESOURCE_* defines into a separate patch
---
src/galli
handeLOAD / handleSTORE / handleATOM can only handle TGSI_FILE_BUFFER
and TGSI_FILE_MEMORY. Make things fail explictly when another
register-file is used in these functions.
Signed-off-by: Hans de Goede
---
Changes in v2:
-Split out of "nouveau: codegen: Disable more old resource handling
Hi,
On 14-03-16 21:50, Samuel Pitoiset wrote:
Btw, do you need someone with commit access to push your previous
series (the tgsi thing)? I can do this for you.
Thanks for the offer. IIRC Ilia wanted some minor fixes there, so I'll do
a v2 tomorrow. Talking about commit rights, I guess it wo
These magic file-index defines where only ever used in the nouveau code
and that no longer uses them.
Signed-off-by: Hans de Goede
---
Changes in v2:
-Split out of "nouveau: codegen: Disable more old resource handling code"
---
src/gallium/include/pipe/p_shader_tokens.h | 9 ---
Add support for OpenCL global memory buffers, note this has only
been tested with regular load and stores and likely needs more work
for e.g. atomic ops.
Signed-off-by: Hans de Goede
---
Changes in v2:
-Redo on top of new "Use FILE_MEMORY_BUFFER for buffers" patch
---
src/galli
Hi,
On 16-03-16 11:45, Samuel Pitoiset wrote:
On 03/16/2016 10:23 AM, Hans de Goede wrote:
Commit c3083c7082 ("nv50/ir: add support for BUFFER accesses") disabled /
commented out some of the old resource handling code, but not all of it.
Effectively all of it is dead already,
ld be easy to make it work.
On 03/16/2016 10:23 AM, Hans de Goede wrote:
Add support for OpenCL global memory buffers, note this has only
been tested with regular load and stores and likely needs more work
for e.g. atomic ops.
Signed-off-by: Hans de Goede
---
src/gallium/drivers/nouveau
Hi,
On 15-03-16 21:55, Samuel Pitoiset wrote:
This avoids using magic numbers for the driver constbuf slot which
is always 15 except for compute shaders on gk104+ where the slot 0
is used.
For gk104+, some special compute-related values like the thread
index are uploaded to screen->parm which i
Add support for OpenCL global memory buffers, note this has only
been tested with regular load and stores and likely needs more work
for e.g. atomic ops.
Signed-off-by: Hans de Goede
---
src/gallium/drivers/nouveau/codegen/nv50_ir.h | 1 +
.../drivers/nouveau/codegen/nv50_ir_emit_gk110
Make the store offset handling in CodeEmitterGK110::emitSTORE identical
to the one in CodeEmitterGK110::emitLOAD handling.
This is just a cleanup, it does not cause any functional changes.
Signed-off-by: Hans de Goede
---
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp | 4 +---
1
handling, this will allow the later (re-)addition
of FILE_MEMORY_GLOBAL for regular global memory.
Signed-off-by: Hans de Goede
---
src/gallium/drivers/nouveau/codegen/nv50_ir.h| 2 +-
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp | 10 +-
src/gallium/drivers
r_tokens.h as those are no longer used now
(which is a good thing).
Signed-off-by: Hans de Goede
---
.../drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 42 +++---
src/gallium/include/pipe/p_shader_tokens.h | 9 -
2 files changed, 30 insertions(+), 21 deletions(-)
Use the dst temp variable which was used in the TGSI_FILE_OUTPUT
case everywhere. This makes the code somewhat easier to reads
and helps avoiding going over 80 chars with upcoming changes.
This also brings the dst handling more in line with the src
handling.
Signed-off-by: Hans de Goede
ormat to tgsi_instruction_memory")
Cc: Nicolai Hähnle
Signed-off-by: Hans de Goede
---
src/gallium/auxiliary/tgsi/tgsi_build.c | 4
1 file changed, 4 insertions(+)
diff --git a/src/gallium/auxiliary/tgsi/tgsi_build.c
b/src/gallium/auxiliary/tgsi/tgsi_build.c
index a3e659b..7e30bb6 10
Add support for clover / OpenCL kernel input parameters.
Signed-off-by: Hans de Goede
Reviewed-by: Ilia Mirkin
---
Changes in v2:
-s/local/private/
-Add: Reviewed-by: Ilia Mirkin
---
.../drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 18 +++---
1 file changed, 15 insertions
BO-s) may differ per implementation. The uploading of kernel
parameters is handled by launch_grid, "MEMORY[x], INPUT" allows drivers
to use an access mechanism for parameter reads which matches with the
upload method.
Signed-off-by: Hans de Goede
Reviewed-by: Ilia Mirkin
---
Changes in v2:
-Drop
When support for decl.Atomic and .Shared was added, tgsi_build_declaration
was not updated to propagate these properly.
Signed-off-by: Hans de Goede
Reviewed-by: Ilia Mirkin
---
Changes in v2:
-Add Reviewed-by: Ilia Mirkin
---
src/gallium/auxiliary/tgsi/tgsi_build.c | 6 ++
1 file changed
Hi,
On 14-03-16 16:41, Samuel Pitoiset wrote:
On 03/14/2016 04:28 PM, Hans de Goede wrote:
Hi,
On 14-03-16 16:05, Ilia Mirkin wrote:
There's a less hacky and more hacky way forward. The more hacky
solution is
to set file index to -1 or something and then not do the lowering when
yo
you feel that solution #1 (which was also my first hunch) is
the right one then I will go and implement that.
What I really don't want is to somehow differentiate glsl-sourced
and opencl-sourced compute programs in the backend.
Ok, understood.
Regards,
Hans
On Mar 14, 2016 6:22 AM, &q
;11.2"
Signed-off-by: Hans de Goede
---
Changes in v2:
-Drop trailing "," from struct initializer
-Add Cc: "11.2"
---
src/gallium/state_trackers/clover/core/kernel.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/state_trackers/clover/
Messed up the subject prefix, sorry. Resending with proper prefix.
On 14-03-16 15:00, Hans de Goede wrote:
After pipe_grid_info.indirect was introduced, clover was not modified
to set it causing it to pass uninitialized memory for it to launch_grid.
This commit fixes this by zero-ing the
;11.2"
Signed-off-by: Hans de Goede
---
Changes in v2:
-Drop trailing "," from struct initializer
-Add Cc: "11.2"
---
src/gallium/state_trackers/clover/core/kernel.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/state_trackers/clover/
Hi,
On 14-03-16 14:01, Samuel Pitoiset wrote:
On 03/14/2016 01:50 PM, Hans de Goede wrote:
After pipe_grid_info.indirect was introduced, clover was not modified
to set it causing it to pass uninitialized memory for it to launch_grid.
This commit fixes this by zero-ing the entire
orward with this ... ?
Signed-off-by: Hans de Goede
---
src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 4
src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 2 ++
2 files changed, 6 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_f
: Hans de Goede
---
src/gallium/state_trackers/clover/core/kernel.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/state_trackers/clover/core/kernel.cpp
b/src/gallium/state_trackers/clover/core/kernel.cpp
index 8396be9..dad66aa 100644
--- a/src/gallium
Hi,
On 10-03-16 16:35, Aaron Watry wrote:
On Thu, Mar 10, 2016 at 9:14 AM, Hans de Goede wrote:
Extend the MEMORY file support to differentiate between global, local
and shared memory, as well as "input" memory.
"MEMORY[x], INPUT" is intended to access OpenCL kernel p
10, 2016 at 10:14 AM, Hans de Goede
wrote:
Add support for clover / OpenCL kernel input parameters.
Signed-off-by: Hans de Goede
---
.../drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 18
+++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/src/gall
Hi,
Here are patches which implement the support for OpenCL kernel input
parameters we discussed. They also add the tgsi parsing bits for
adding support for global / local mem, but no implementation yet.
Regards,
Hans
___
mesa-dev mailing list
mesa-dev
Add support for clover / OpenCL kernel input parameters.
Signed-off-by: Hans de Goede
---
.../drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 18 +++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
b
When support for decl.Atomic and .Shared was added, tgsi_build_declaration
was not updated to propagate these properly.
Signed-off-by: Hans de Goede
---
src/gallium/auxiliary/tgsi/tgsi_build.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/src/gallium/auxiliary/tgsi/tgsi_build.c
b
BO-s) may differ per implementation. The uploading of kernel
parameters is handled by launch_grid, "MEMORY[x], INPUT" allows drivers
to use an access mechanism for parameter reads which matches with the
upload method.
Signed-off-by: Hans de Goede
---
src/gallium/auxiliary/tgsi/tgsi_build.c
Hi,
On 29-11-15 17:14, Samuel Pitoiset wrote:
This patch fixes the issue for me (eg.
https://bugs.freedesktop.org/show_bug.cgi?id=93091#c8).
Thanks Tom.
Tested-by: Samuel Pitoiset
I'm seeing a similar crash, but for me the problem is caused by
pipe_loader_sw_probe returning 1, but not fill
Hi,
On 13-11-15 19:51, Tom Stellard wrote:
On Fri, Nov 13, 2015 at 02:46:52PM +0100, Hans de Goede wrote:
Hi All,
So as discussed I've started working on a TGSI backend for
llvm to use as a way to get compute going on nouveau (and other gpu-s).
I'm still learning all the ins and ou
Hi,
On 13-11-15 19:51, Tom Stellard wrote:
On Fri, Nov 13, 2015 at 02:46:52PM +0100, Hans de Goede wrote:
Hi All,
So as discussed I've started working on a TGSI backend for
llvm to use as a way to get compute going on nouveau (and other gpu-s).
I'm still learning all the ins and ou
Hi All,
So as discussed I've started working on a TGSI backend for
llvm to use as a way to get compute going on nouveau (and other gpu-s).
I'm still learning all the ins and outs of llvm so I do not have
much to show yet.
I've rebased Francisco's (curro's) latest version on top of llvm
trunk, a
Hi,
On 07-11-15 01:59, Ilia Mirkin wrote:
Hi Hans,
All pushed. I made a few additional fixes and improvement to fp64
immediate handling along the way, but all your commits were fine
as-is. (Except that they enabled fp64 immediates on nv50 implicitly
which is wrong -- there are no immediate-taki
Hi,
On 06-11-15 00:51, Samuel Pitoiset wrote:
On 11/06/2015 12:43 AM, Ilia Mirkin wrote:
On Thu, Nov 5, 2015 at 6:41 PM, Samuel Pitoiset
wrote:
Altough the compute support is still not complete because textures and
surfaces need to be implemented, it allows to launch very simple compute
ker
Now that we support 64 bit immediates in insnCanLoad, we need to swap
64 bit immediate sources too for optimal effect.
Signed-off-by: Hans de Goede
---
src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/src
This allows later passes like LoadPropagation to properly deal with 64
bit immediates.
If the new 64 bit load this introduces does not get optimized away then
split64BitOpPostRA() will split this into 2 instructions again.
Signed-off-by: Hans de Goede
---
src/gallium/drivers/nouveau/codegen
.50 (8)
Signed-off-by: Hans de Goede
---
.../nouveau/codegen/nv50_ir_target_nvc0.cpp| 25 --
1 file changed, 19 insertions(+), 6 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_targe
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