On Tue, 12 Sep 2017 19:25:18 +0200, Vadim Girlin wrote:
On 09/12/2017 12:49 PM, Gert Wollny wrote:
Am Dienstag, den 12.09.2017, 09:56 +0300 schrieb Vadim Girlin:
On 09/11/2017 07:09 PM, Emil Velikov wrote:
Anyway, if num_arrays is 0 there, I suspect it can be a result of
some other issue.
}
- }
+ if (!rctx->blitter->running)
+ r600_update_compressed_resource_state(rctx);
SELECT_SHADER_OR_FAIL(ps);
Patch series is Reviewed-by: Glenn Kennard
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Signed-off-by: Glenn Kennard
---
src/gallium/drivers/r600/evergreen_state.c | 24 +++
src/gallium/drivers/r600/r600_pipe.c | 3 +
src/gallium/drivers/r600/r600_pipe.h | 14
src/gallium/drivers/r600/r600_shader.h | 1 +
src/gallium/drivers/r600
Signed-off-by: Glenn Kennard
---
src/gallium/drivers/r600/r600_shader.h | 1 +
src/gallium/drivers/r600/sb/sb_bc_finalize.cpp | 2 +-
src/gallium/drivers/r600/sb/sb_bc_parser.cpp | 12
src/gallium/drivers/r600/sb/sb_core.cpp| 3 ++-
src/gallium/drivers/r600/sb
Pessimistically spills arrays if GPR limit is exceeded.
Signed-off-by: Glenn Kennard
---
src/gallium/drivers/r600/r600_shader.c | 308 ++---
1 file changed, 285 insertions(+), 23 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_shader.c
b/src/gallium/drivers
Signed-off-by: Glenn Kennard
---
src/gallium/drivers/r600/evergreend.h | 14 ++
src/gallium/drivers/r600/r600d.h | 8 ++--
2 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreend.h
b/src/gallium/drivers/r600/evergreend.h
index
Signed-off-by: Glenn Kennard
---
src/gallium/drivers/r600/r700_sq.h | 30 ++
1 file changed, 30 insertions(+)
diff --git a/src/gallium/drivers/r600/r700_sq.h
b/src/gallium/drivers/r600/r700_sq.h
index d881012..81e0e7a 100644
--- a/src/gallium/drivers/r600/r700_sq.h
Signed-off-by: Glenn Kennard
---
src/gallium/drivers/r600/r600d.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/src/gallium/drivers/r600/r600d.h b/src/gallium/drivers/r600/r600d.h
index 9155076..0d04708 100644
--- a/src/gallium/drivers/r600/r600d.h
+++ b/src/gallium/drivers/r600
Signed-off-by: Glenn Kennard
---
src/gallium/drivers/r600/eg_asm.c | 3 ++-
src/gallium/drivers/r600/r600_asm.c | 25 +++-
src/gallium/drivers/r600/r600_asm.h | 15 ++
src/gallium/drivers/r600/r700_asm.c | 39 +
4 files
This patch series implements support for spilling temporary arrays on
R6xx/R7xx/Evergreen/NI if hardware GPR limits are exceeded. It opts for a
simple pessimistic scheme of spilling the largest arrays until things fit.
This fixes some subset of issues where "GPR limit exceeded" or "TGSI
translatio
Spills have to happen after the VLIW bundle currently
processed, so defer emitting the spill op.
Signed-off-by: Glenn Kennard
---
src/gallium/drivers/r600/r600_asm.c | 18 ++
src/gallium/drivers/r600/r600_asm.h | 4
2 files changed, 22 insertions(+)
diff --git a/src
Signed-off-by: Glenn Kennard
---
src/gallium/drivers/r600/sb/sb_bc.h | 11 ++
src/gallium/drivers/r600/sb/sb_bc_builder.cpp | 46 -
src/gallium/drivers/r600/sb/sb_bc_decoder.cpp | 49 ++-
src/gallium/drivers/r600/sb/sb_bc_dump.cpp
On Wed, 15 Jun 2016 20:13:13 +0200, Jan Vesely wrote:
Signed-off-by: Jan Vesely
---
Untested (I don't have the required hw)
src/gallium/drivers/r600/r600_pipe.c | 5 -
src/gallium/drivers/r600/r600_shader.c | 2 +-
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/src/gall
On Thu, 10 Mar 2016 18:13:03 +0100, Ilia Mirkin wrote:
On Thu, Mar 10, 2016 at 12:04 PM, Glenn Kennard wrote:
On Thu, 10 Mar 2016 17:02:15 +0100, Ilia Mirkin
wrote:
On Thu, Mar 10, 2016 at 10:57 AM, Nicolai Hähnle
wrote:
- if (c->MaxCombinedAtomicBuffers > 0)
+
The patch makes a bit more sense to me after realizing a fallthrough was
changed to a break, so the whole patch is
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On Thu, 10 Mar 2016 17:02:15 +0100, Ilia Mirkin wrote:
On Thu, Mar 10, 2016 at 10:57 AM, Nicolai Hähnle wrote:
- if (c->MaxCombinedAtomicBuffers > 0)
+ if (c->MaxCombinedAtomicBuffers > 0) {
extensions->ARB_shader_atomic_counters = GL_TRUE;
+ extensions->ARB_shader_atomic_cou
al arg = v0->get_const_value();
apply_alu_src_mod(a->bc, 0, arg);
- if (cur_neg)
+ if (cur_neg && distribute_neg)
arg.f = -arg.f;
if (last_arg == 0) {
With the allow_neg c
Based off of Ilia's original patch, but with output values replicated so
that it matches the TGSI semantics.
Signed-off-by: Glenn Kennard
---
src/gallium/drivers/r600/r600_pipe.c | 2 +-
src/gallium/drivers/r600/r600_shader.c | 107 +++--
2 files changed
On Wed, 16 Dec 2015 20:57:51 +0100, Nanley Chery wrote:
From: Nanley Chery
Commit 64880d073ab21ae1abad0c049ea2d6a1169a3cfa consolidated two
DIV_ROUND_UP() definitions to one, but chose the more
compute-intensive version in the process. Use the simpler version
instead. Reduces .text size by 13
PS: return "PS";
case TARGET_GS: return "GS";
+ case TARGET_HS: return "HS";
+ case TARGET_LS: return "LS";
case TARGET_COMPUTE: return "COMPUTE&qu
ALLOC_CONSUME, AC,30, 30)
+BC_FIELD(MEM_GDS_WORD1, BCARD_FIRST_REQ,BFR, 31, 31)
+BC_FORMAT_END(MEM_GDS_WORD1)
+
+BC_FORMAT_BEGIN_HW(MEM_GDS_WORD2, EGCM)
+BC_FIELD(MEM_GDS_WORD2, DST_SEL_X, DSX,2, 0)
+BC_FIELD(MEM_GDS_WORD2, DST_SEL_Y, DSY,5, 3)
+BC_FIELD(MEM_GDS_WORD2, DST_SEL_Z, DSZ,8, 6)
+BC_FIELD(MEM_GDS_WORD2, DST_SEL_W, DSW, 11, 9)
+BC_FORMAT_END(MEM_GDS_WORD2)
\ No newline at end of file
With src_rel/dst_rel dealt with as suggested above,
Reviewed-by: Glenn Kennard
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der_from_tgsi(struct r600_context
*rctx,
shader->nr_ps_color_exports = 0;
shader->nr_ps_max_color_exports = 0;
- if (ctx.type == TGSI_PROCESSOR_FRAGMENT)
- shader->two_side = key.ps.color_two_side;
/* register allocations */
/* Values [0,127
#x27;;
}
- if (alu->dst.write || alu->is_op3) {
+ if (alu_writes(alu)) {
o += fprintf(stderr, "%c", reg_char);
o += print_sel(alu->dst.sel, alu->dst.rel, alu->index_mode, 0);
} else {
Reviewed-by: Glenn Kennard
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ayman only */
+#define EG_V_SQ_ALU_SRC_LDS_OQ_A 0x00DB
+#define EG_V_SQ_ALU_SRC_LDS_OQ_B 0x00DC
+#define EG_V_SQ_ALU_SRC_LDS_OQ_A_POP 0x00DD
+#define EG_V_SQ_ALU_SRC_LDS_OQ_
E8
#define CM_R_028804_DB_EQAA 0x00028804
#define S_028804_MAX_ANCHOR_SAMPLES(x) (((x) & 0x7) << 0)
Reviewed-by: Glenn Kennard
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On Fri, 13 Nov 2015 18:57:28 +0100, Nicolai Hähnle
wrote:
On 13.11.2015 00:14, Glenn Kennard wrote:
Signed-off-by: Glenn Kennard
---
Maybe there is a better way to check if a thread is a helper invocation?
Is ctx->face_gpr guaranteed to be initialized when
load_helper_invocation
Signed-off-by: Glenn Kennard
---
Maybe there is a better way to check if a thread is a helper invocation?
src/gallium/drivers/r600/r600_shader.c | 83 +-
1 file changed, 72 insertions(+), 11 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_shader.c
b/src
gl_HelperInvocation */
+ TGSI_SEMANTIC_HELPER_INVOCATION,
/* Tessellation shaders
*/
@@ -5139,6 +5139,8 @@ st_translate_program(
TGSI_SEMANTIC_BASEVERTEX);
assert(_mesa_sysval_to_semantic[SYSTEM_VALUE_TESS_COORD] ==
TGSI_SE
p;
0x1)
#define C_028890_UNCACHED_FIRST_INST 0xEFFF
+#define R_028894_SQ_PGM_RESOURCES_2_ES 0x028894
#define R_028864_SQ_PGM_RESOURCES_2_VS 0x028864
#define S_028864_SINGLE_ROUND(x) (((x) &a
Supported on R700 and up.
Signed-off-by: Glenn Kennard
---
v2:
Use correct register for R700, set from r600_emit_db_misc_state
Added ps_conservative_z field to r600_db_misc_state
Shrunk ps_conservative_z to uint8 since only 2 bits are needed
Thanks Alex for noting the incorrect register
Supported on R700 and up.
Signed-off-by: Glenn Kennard
---
Not exactly a commonly used extension, but might as well set the
hardware registers rather than just dropping the hint on the floor.
src/gallium/drivers/r600/evergreen_state.c | 13 +
src/gallium/drivers/r600/evergreend.h
Signed-off-by: Glenn Kennard
---
See also additional texture view piglit test case posted to piglit ml,
which tests cases with layer>0. Notably softpipe and llvmpipe fail that
case but i965/hsw, nv50/nvc0 and r600g pass.
docs/GL3.txt | 2 +-
docs/relnotes/11.
On Wed, 07 Oct 2015 19:59:03 +0200, Benjamin Bellec
wrote:
Le 07/10/2015 19:13, Glenn Kennard a écrit :
On Wed, 07 Oct 2015 19:04:15 +0200, Benjamin Bellec
wrote:
Hi Glenn,
The series doesn't apply on current master.
Regard.
It's not meant to apply directly on master. Qu
On Wed, 07 Oct 2015 19:04:15 +0200, Benjamin Bellec
wrote:
Hi Glenn,
The series doesn't apply on current master.
Regard.
It's not meant to apply directly on master. Quoting from the notes in
patch 1/2:
This patch depends on prior patch:
r600g/sb: Support gs5 sampler indexing
/Gle
Signed-off-by: Glenn Kennard
---
This patch depends on prior patch:
r600g/sb: Support gs5 sampler indexing
Two items that could be improved on in some future patch:
Clauses using UBO indexing still lock the cache line for a
constant used to load the index register, which causes some
Signed-off-by: Glenn Kennard
---
Now that SB supports the GS5 features we can safely enable the
extension.
Note that gallium state tracker clamps the GLSL language / GL version
since GL_ARB_tessellation_shader isn't implemented yet.
docs/GL3.txt
On Tue, 29 Sep 2015 17:00:31 +0200, Marek Olšák wrote:
On Tue, Sep 29, 2015 at 4:48 PM, Romain Failliot
wrote:
What I don't understand is that all the lines starting with a "-" seems
to
be part of the GL_ARB_gpu_shader5 extension. See the line here:
http://cgit.freedesktop.org/mesa/mesa/tre
Signed-off-by: Glenn Kennard
---
Just UBO support left before gs5 can be enabled.
Could improve how the two index registers are set/used to reduce
the number of clauses, but as is its about as good as what the blob
emits.
src/gallium/drivers/r600/r600_shader.c | 12 ++-
src/gallium
_format_description(templ.format);
Tested / Reviewed-by: Glenn Kennard
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PIPE_CAP_TEXTURE_FLOAT_LINEAR,
PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR,
PIPE_CAP_DEPTH_BOUNDS_TEST,
+ PIPE_CAP_TGSI_TXQS,
};
#define PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50 (1 << 0)
Reviewed-by: Glenn Kennard
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me
Cypress/Cayman/Aruba, earlier r6xx/r7xx chips only support a subset
of the needed fp64 ops, and don't do GL4 anyway.
Signed-off-by: Glenn Kennard
---
Changes since v1:
Updated commit message
docs/GL3.txt | 4 ++--
docs/relnotes/11.1.0.html| 2 +-
Only for Cypress/Cayman/Aruba, older chips have only partial fp64 support.
Uses float intermediate values so only accurate for int24 range, which
matches what the blob does.
Signed-off-by: Glenn Kennard
---
Changes since v1:
Split into two functions
Make names a bit clearer which chips they
Series is:
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int <-> float <-> double conversion, matches what the blob does
Signed-off-by: Glenn Kennard
---
src/gallium/drivers/r600/r600_shader.c | 95 +++---
1 file changed, 87 insertions(+), 8 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_shader.c
b
Signed-off-by: Glenn Kennard
---
docs/GL3.txt | 4 ++--
docs/relnotes/11.1.0.html| 2 +-
src/gallium/drivers/r600/r600_pipe.c | 3 +++
3 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/docs/GL3.txt b/docs/GL3.txt
index 8ad1aac..7247eb6 100644
n() == r) {
+ last_cf = if_pop;
+ }
if_pop->bc.pop_count = 1;
if_pop->jump_after(if_pop);
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M_TYPE_TRISTRIP
};
assert(mode < Elements(prim_conv));
A dup of si_conv_prim_to_gs_out(), but probably not worth the hassle of
sharing.
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Signed-off-by: Glenn Kennard
---
src/gallium/drivers/r600/sb/sb_bc_parser.cpp | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/r600/sb/sb_bc_parser.cpp
b/src/gallium/drivers/r600/sb/sb_bc_parser.cpp
index 748aae2..c479927 100644
--- a/src/gallium
e8e443 missed adding check for undef values also in
unreserve function, leading to an assert triggering.
Signed-off-by: Glenn Kennard
---
src/gallium/drivers/r600/sb/sb_sched.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/r600/sb/sb_sched.cpp
b/src
print EOP bit if set in old asm printer.
Signed-off-by: Glenn Kennard
---
src/gallium/drivers/r600/r600_asm.c | 2 ++
src/gallium/drivers/r600/sb/sb_bc_decoder.cpp | 1 +
src/gallium/drivers/r600/sb/sb_bc_parser.cpp | 4 +++-
3 files changed, 6 insertions(+), 1 deletion(-)
diff --git a
Fixes https://bugs.freedesktop.org/show_bug.cgi?id=91726
Signed-off-by: Glenn Kennard
---
src/gallium/drivers/r600/r600_shader.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_shader.c
b/src/gallium/drivers/r600/r600_shader.c
index 6cbfd1b
FLT_TO_INT goes in the vector pipes on evergreen/NI,
not the trans unit as on earlier chips.
Signed-off-by: Glenn Kennard
---
Fixes issue found on nine: https://github.com/iXit/Mesa-3D/issues/119
src/gallium/drivers/r600/r600_isa.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
.bc->ar_reg + 1;
- ctx.bc->index_reg[0] = ctx.bc->ar_reg + 2;
- ctx.bc->index_reg[1] = ctx.bc->ar_reg + 3;
+ ctx.temp_reg = ctx.bc->ar_reg + 3;
}
shader->max_arrays = 0;
Reviewed-by: Glenn Kennard
__
't think of any useful cases for the cayman specific ALU global
register. Drop these four?
+
#endif
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ncides with the logical
&& operation, so if using logical and instead silences gcc 5 irritable
warning syndrome, it can get a
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ige', a, b)), ('ilt', a, b)),
+ (('inot', ('ieq', a, b)), ('ine', a, b)),
+ (('inot', ('ine', a, b)), ('ieq', a, b)),
(('fge', ('fneg', ('fabs', a)), 0.0), ('feq', a, 0.0)),
-)
Some minor nits for patches 1, 6 and 7, see separate mails
Patches 2-5, 8-19 are
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per patch */
+
patch_vertex_count, this field isn't the actual patch vertices data
Don't forget to update patch 10 with the name
/**
* For indexed drawing, these fields apply after index lookup.
*/
With above fixed,
Reviewed-by: Glenn Kennard
_
_shader_tokens.h
+++ b/src/gallium/include/pipe/p_shader_tokens.h
@@ -43,7 +43,9 @@ struct tgsi_header
#define TGSI_PROCESSOR_FRAGMENT 0
#define TGSI_PROCESSOR_VERTEX1
#define TGSI_PROCESSOR_GEOMETRY 2
-#define TGSI_PROCESSOR_COMPUTE 3
+#define TGSI_PROCESSOR_TESSCTRL 3
+#define TGSI_P
rc/gallium/include/pipe/p_shader_tokens.h
+++ b/src/gallium/include/pipe/p_shader_tokens.h
@@ -262,7 +262,12 @@ union tgsi_immediate_data
#define TGSI_PROPERTY_VS_PROHIBIT_UCPS 7
#define TGSI_PROPERTY_GS_INVOCATIONS 8
#define TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION 9
-#define TGSI_PROPE
Fixes assert triggered by
ext_transform_feedback-intervening-read output use_gs
piglit test.
Signed-off-by: Glenn Kennard
---
src/gallium/drivers/r600/sb/sb_sched.cpp | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/gallium/drivers/r600/sb/sb_sched.cpp
b/src/gallium/drivers/r600/sb
plained GS piglit regressions on R6xx/R7xx with SB
enabled otherwise.
Signed-off-by: Glenn Kennard
---
Changes since v1:
* Enable SB only for >= EVERGREEN. Something strange going on
with GS on R6xx/R7xx that the code emitted by SB triggers,
haven't been able to pinpoint it yet.
* Avoid spl
return r;
- r = tgsi_make_src_for_op3(ctx, ctx->temp_reg, 1, &alu.src[1],
&ctx->src[2], i);
+ r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[1],
&ctx->src[2]);
if (r)
return r;
- r = tgsi_make_src_for_op3(ctx, ctx-&
CF_END could end up emitted in the middle of a shader on cayman
when there was a loop at the very end.
Fixes glsl-1.50-geometry-end-primitive and
ext_transform_feedback-geometry-shaders-basic piglit tests.
Signed-off-by: Glenn Kennard
---
Bug exposed by [PATCH] r600g/sb: Enable SB for geometry
On Wed, 25 Mar 2015 14:26:40 +0100, Marc Dietrich wrote:
Am Dienstag, 24. März 2015, 20:05:46 schrieb Glenn Kennard:
On Tue, 24 Mar 2015 17:21:35 +0100, Dieter Nützel
wrote:
> Am 20.03.2015 14:13, schrieb Glenn Kennard:
>> Add SV_GEOMETRY_EMIT special variable type to track the
&g
On Tue, 24 Mar 2015 17:21:35 +0100, Dieter Nützel
wrote:
Am 20.03.2015 14:13, schrieb Glenn Kennard:
Add SV_GEOMETRY_EMIT special variable type to track the
implicit dependencies between CUT/EMIT_VERTEX/MEM_RING
instructions so GCM/scheduler doesn't reorder them.
Mark emit instructio
Add SV_GEOMETRY_EMIT special variable type to track the
implicit dependencies between CUT/EMIT_VERTEX/MEM_RING
instructions so GCM/scheduler doesn't reorder them.
Mark emit instructions as unkillable so DCE doesn't eat them.
Signed-off-by: Glenn Kennard
---
The hangs with SB on geomet
em value");
return;
Patches 4-9 are
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_OPCODE_DRCP, 0, ALU_OP2_RECIP_64, cayman_emit_double_instr},
+ {TGSI_OPCODE_DSQRT, 0, ALU_OP2_SQRT_64, cayman_emit_double_instr},
+ {TGSI_OPCODE_DMAD, 0, ALU_OP3_FMA_64, tgsi_op3_64},
+ {TGSI_OPCODE_DFRAC, 0, ALU_OP1_FRACT_64, tgsi
unreserve(bs_cycle(trans, bs, i), n->bc.src[i].sel,
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Don't try to do float comparisons on signed integer values,
some of them look like NaNs.
Fixes fs-temp-array-mat3-index-col-row-rd.shader_test regression
caused by 0d4272cd8e7c45157140dc8e283707714a8238d5.
Signed-off-by: Glenn Kennard
---
src/gallium/drivers/r600/sb/sb_peephole.cpp | 2
On Fri, 06 Feb 2015 17:08:46 +0100, Marek Olšák wrote:
Please bump the size of vgt_state for the SQ_VTX_BASE_VTX_LOC
register. It's set by r600_init_atom in r600_state.c and
evergreen_state.c
Please bump R600_MAX_DRAW_CS_DWORDS. It's an upper bound of how many
dwords draw_vbo can emit.
Than
On Fri, 06 Feb 2015 20:53:21 +0100, Roland Scheidegger
wrote:
FWIW I'm wondering why you'd actually need them in a d3d9 state tracker,
as this is a feature first seen with d3d10. Unless you'd want to handle
d3d10 of course, but in this case there's probably not much hope for any
of the d3d9 c
Requires Evergreen/Cayman and radeon kernel module
2.41.0 or newer.
Signed-off-by: Glenn Kennard
---
Changes since v2:
* Fix failing arb_draw_indirect-vertexid piglit test cases.
* Ensure start_instance, base_vertex, index_offset are reset when
switching back to direct draws.
* Juggled some
On Wed, 31 Dec 2014 21:43:51 +0100, Micah Fedke
wrote:
---
src/glsl/glcpp/glcpp-parse.y| 3 +++
src/glsl/glsl_parser_extras.cpp | 1 +
src/glsl/glsl_parser_extras.h | 2 ++
src/mesa/main/extensions.c | 1 +
src/mesa/main/mtypes.h | 1 +
5 files changed, 8 insertions(+)
d
egfaults on R600 (with
GALLIUM_TESTS=1), which i presume is intentional to expose a bug there. If
yes, then:
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*i,
0);
+
+ t[i]->buf_filled_size_valid = true;
}
rctx->streamout.begin_emitted = false;
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ge3DMultisample", 45, -1 },
{ "glTextureBuffer", 45, -1 },
+ /* GL_EXT_polygon_offset_clamp */
+ { "glPolygonOffsetClampEXT", 11, -1 },
+
{ NULL, 0, -1 }
};
Patches 1-5 (assuming fix for clamp in 2 noted already by Ilia) are
Reviewed-by: Glenn Kennard
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R6.y.2,R5.w.1, -1.0001|bf800347
because abs() modifier was ignored.
Signed-off-by: Xavier Bouchoux
Reviewed-by: Glenn Kennard
Thanks Xavier! For future patches, please use git send-email as noted in
http://www.mesa3d.org/devinfo.html so reviewers can comment inline
On Fri, 30 Jan 2015 15:19:49 +0100, Martin Peres
wrote:
Signed-off-by: Martin Peres
---
src/mesa/drivers/dri/common/drirc | 7 +++
1 file changed, 7 insertions(+)
diff --git a/src/mesa/drivers/dri/common/drirc
b/src/mesa/drivers/dri/common/drirc
index cecd6a9..073814e 100644
--- a/s
}
}
return key;
}
@@ -1265,6 +1269,7 @@ static bool r600_update_derived_state(struct
r600_context *rctx)
r600_update_ps_state(ctx,
rctx->ps_shader->current);
}
+ rctx->shader_stages.atom.dirty = true;
update
er->sprite_coord_enable !=
rctx->ps_shader->current->sprite_coord_enable ||
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On Thu, 15 Jan 2015 15:32:59 +0100, Roland Scheidegger
wrote:
Am 15.01.2015 um 10:05 schrieb Iago Toral:
Hi,
We have 16 deqp tests that fail, at least on i965, because of
insufficient precision of the mod GLSL function.
Mesa lowers mod(x,y) to y * fract(x,y) so there can be some precision
On Tue, 23 Dec 2014 22:50:30 +0100, Dave Airlie wrote:
This patch adds support for a set of double opcodes
to TGSI. It is an update of work done originally
by Michal Krol on the gallium-double-opcodes branch.
The opcodes have a hint where they came from in the
header file.
v2: add unsigned/in
entinel((_node)->node.next)
+static inline bool
+nir_cf_node_is_last(const nir_cf_node *node)
+{
+ return exec_node_is_tail_sentinel(node->node.next);
+}
NIR_DEFINE_CAST(nir_cf_node_as_block, nir_cf_node, nir_block, cf_node)
NIR_DEFINE_CAST(nir_cf_node_as_if, nir_cf_node, nir_if, cf_node)
Re
On Tue, 16 Dec 2014 07:04:14 +0100, Jason Ekstrand
wrote:
From: Connor Abbott
This includes all the instructions, ifs, loops, functions, etc. This is
similar to the information in ir.h.
v2: Jason Ekstrand :
Include ralloc and hash_table from the util directory
---
src/glsl/Makefile.sou
Requires Evergreen/Cayman and updated radeon kernel module
Signed-off-by: Glenn Kennard
---
Changes since V1:
* Fixed 8 bit index case, only triggerable using GLES 3.1 which isn't supported
yet
* Don't read info struct values that have no meaning for indirect case
* Don't update
cp_shader->ring_item_size >> 2);
r600_store_context_reg(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE,
(rshader->ring_item_size) >> 2);
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ode *a);
+ void insert_rv6xx_load_ar_workaround(alu_group_node *b4);
+ void finalize_alu_group(alu_group_node *g, node *prev_node);
+ bool finalize_alu_src(alu_group_node *g, alu_node *a, alu_group_node
*prev_node);
void emit_set_grad(fetch_node* f);
void finalize_fetch(fetch_node *f);
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DGE_INT;
+ alu.op = ALU_OP3_CNDE_INT;
r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
r600_bytecode_src(&alu.src[2], &ctx->
->is_depart() || repdep2->is_repeat());
I think i've managed to convince myself the above logic is correct, so
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->shader.has_txq_cube_array_z_comp;
+ if (need_buf_const) {
+ if (rctx->b.chip_class < EVERGREEN)
+ r600_setup_buffer_constants(rctx,
PIPE_SHADER_GEOMETRY);
+ else
+ eg_setup_buffer_constants(rctx,
PIPE_SHADER_GEOMETRY);
+ }
+ }
if (rctx->b.chip_class < EVERGREEN && rctx->ps_shader &&
rctx->vs_shader) {
if (!r600_adjust_gprs(rctx)) {
Passes piglits on a Turks with no obvious regressions, so with nits above
fixed, consider it
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if (r)
+ return r;
+ }
+ }
+
if (src_requires_loading && !src_loaded) {
for (i = 0; i < 4; i++) {
memset(&alu, 0, sizeof(struct r600_bytecode_alu));
ARB_shader_texture_lod piglits g
}
tex.dst_gpr = ctx->temp_reg; /* just to avoid confusing the asm
scheduler */
tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z =
tex.dst_sel_w = 7;
if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
Reviewed-by: Glenn
}
}
}
Confirmed fixes the same set of tests on a Turks.
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(struct r600_shader_ctx *ctx,
Confirmed fixes the same set of tests on a Turks.
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P_CF_END));
+ } else
last_cf->bc.end_of_program = 1;
for (unsigned t = EXP_PIXEL; t < EXP_TYPE_COUNT; ++t) {
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se if (inst->Instruction.Opcode == TGSI_OPCODE_LODQ) {
tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
Gotta permute those tex op bit encodings between hardware generations or
they go stale...
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amp;alu);
+ if (r)
+ return r;
+ }
+
return 0;
}
Trivial nit: last_slot is no longer needed and can be removed.
With a bit of luck it will also fix
https://bugs.freedesktop.org/show_bug.cgi?id=85376
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Requires evergreen/cayman, and updated radeon kernel module.
Signed-off-by: Glenn Kennard
---
See also kernel side patch sent to dri-de...@lists.freedesktop.org
docs/GL3.txt | 4 +-
docs/relnotes/10.4.html | 1 +
src/gallium/drivers/r600
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