[Mesa-dev] i965 Valleyview: 3DSTATE_URB_VS Minimum URB Entries Fix

Hello folks, I am not too sure if this right avenue but I am trying to get the patch below integrated into MESA. The patch below solves a bug where for several 3D application running on Intel's Valleyview hardware there would be massive corruption. Corruptions includes vertex being wrongly cl

[Mesa-dev] i965 Valleyview: 3DSTATE_URB_VS Minimum URB Entries Fix

Hello folks, I am not too sure if this right avenue but I am trying to get the patch below integrated into MESA. The patch below solves a bug where for several 3D application running on Intel's Valleyview hardware there would be massive corruption. Corruptions includes vertex being wrongly clip