https://bugs.freedesktop.org/show_bug.cgi?id=110847
--- Comment #2 from Mark Janes ---
Oops, I guess it needs an include also:
https://gitlab.freedesktop.org/majanes/mesa/commit/97e056faf38ff65274dd91e2a1d29ae7859c1c51
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https://bugs.freedesktop.org/show_bug.cgi?id=110847
Mark Janes changed:
What|Removed |Added
Status|NEW |ASSIGNED
Assignee|mesa-dev@lists
https://bugs.freedesktop.org/show_bug.cgi?id=110847
Bug ID: 110847
Summary: occlusion-query.c:190:45: error: format specifies type
'unsigned long' but the argument has type 'uint64_t'
(aka 'unsigned long long') [-Werror,-Wformat]
On Wed, Jun 5, 2019 at 12:04 PM Samuel Pitoiset
wrote:
>
>
> On 6/5/19 2:51 AM, Bas Nieuwenhuizen wrote:
> > On Thu, May 30, 2019 at 4:02 PM Samuel Pitoiset
> > wrote:
> >> From the Vulkan spec 1.1.109:
> >>
> >> "Some implementations may need to evaluate depth image values
> >> while p
r-b
On Mon, Jun 3, 2019 at 3:45 PM Bas Nieuwenhuizen
wrote:
>
> While it is not wrong, I don't think this is the right fix, as the
> current_layout is not necessarily accurate.
>
> Will try to get something better.
>
> On Thu, May 30, 2019 at 3:10 PM Samuel Pitoiset
> wrote:
> >
> > This might f
https://bugs.freedesktop.org/show_bug.cgi?id=110811
--- Comment #7 from Yury Zhuravlev ---
I have the same issue.
Also, before was GPU just hung, now it's working stable but with artifacts.
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Hi list,
Sorry for the brief message, but I'm on a time crunch. Things are chugging along
with the 19.0.6 release. This was planned to be the last release of the 19.0
series, but I'm planning to have another one in two weeks due to a longer RC
cycle for 19.1.
Dylan
Shortlog
Alok Hota (
We postfix instructions by their size if a destination override is in
place (a la AT&T assembly), disambiguating instruction sizes.
Previously, "16-bit instruction, 16-bit dest, 16-bit sources"
disassembled identically to "32-bit instruction, 16-bit dest, 16-bit
sources", which is semantically dist
Midgard ALUs can operate in one of four modes: vec2 64-bit, vec4 32-bit,
vec8 16-bit, or vec16 8-bit. Our compiler (and indeed, any OpenGL ES
shader) only uses 32-bit (and eventually vec4 16-bit) modes in normal
circumstances. Nevertheless, the other modes do exist and are easily
accessible through
This adds a set of opcodes for performing moves and type conversions
with respect to particular rounding modes, required for OpenCL.
Signed-off-by: Alyssa Rosenzweig
---
.../drivers/panfrost/midgard/midgard.h| 27 ++-
.../panfrost/midgard/midgard_compile.c| 18 +++
As a source modifier, shift allows shifting a value left by the bit
size, useful in conjunction with a greater register mode, for instance
to implement `upsample`. As a concrete example, the following OpenCL:
ushort hr0 = /* ... */, uint r1 = /* ... */;
uint r2 = (convert_uint(hr0) << 16) ^
This series is the culmination of quite a bit of poking at OpenCL
kernels, exposing a bunch of details about integer and reduced-precision
modes that don't normally come up in OpenGL (but come up in enough truly
bizarre corners, i.e. blend shaders, that without this knowledge,
debugging can be herc
For floats, output modifiers determine clamping behaviour. For integers,
they determine wrapping/saturation behaviour (or shifting -- see next
commit). These are very different; they are conceptually two unrelated
enums union'ed together; the distinction is responsible for many-a-bug.
While clampin
OP_TYPE_CONVERTS denotes an opcode that returns a different type than is
source (going from int-domain to float-domain or vice versa), named
after the f2i/i2f family of opcodes it covers. We care because source
mods are determined by the source type (i/f) but output modifiers are
determined by the
The pipeline register creation algorithm is only valid for SSA indices;
NIR registers and such cannot be pipelined without more complex
analysis. However, there are the ocassional class of "liars" -- indices
that claim to be SSA but are not. This occurs in the blend shader
prologue, for example. De
This piece of code was cargo-culted from the ir3 standalone compiler and
made sense when we were a standalone compiler ourselves. Unfortunately,
for the online compiler, mesa/st *already handles this for us* and if we
duplicate it here, we're duplicating it *incorrectly*. So just delete
these lines
Pushed.
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Reviewed-by: Marek Olšák
Marek
On Wed, Jun 5, 2019 at 6:49 AM Connor Abbott wrote:
> When e9d935ed0e2 added force_dcc_off(), we forced it off for any
> preloaded image descriptor which had stores associated with them, since
> the same preloaded descriptors were used for loads and stores. Howev
https://bugs.freedesktop.org/show_bug.cgi?id=110846
Bug ID: 110846
Summary: VA-API st doesn't expose NOISE_REDUCTION/SHARPNESS,
while they exposed via VDPAU st
Product: Mesa
Version: git
Hardware: x86 (IA32)
Hello, list.
The fifth release candidate for Mesa 19.1.0 is now available.
We have extended the release candidates because there are two bugs blocking the
final release:
#110302 - [bisected][regression] piglit egl-create-pbuffer-surface and
egl-gl-colorspace regressions
#110357 - [REGRESSION]
On Mon, 3 Jun 2019 at 23:52, Marek Olšák wrote:
>
> Would you please review this fixed version:
> https://cgit.freedesktop.org/~mareko/mesa/commit/?h=master&id=40e4702ef815410f74130f349e2b40cc0524e422
>
> It trivially solves the GBM crash by checking that gbm_surf != NULL before
> using it.
>
Mak
From: Emil Velikov
As elaborated in the next patch, there is some hidden ABI that
effectively require most entrypoints to be listed in the file.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110302
Cc: Marek Olšák
Fixes: c5c38e831ee ("mesa: implement ARB/KHR_parallel_shader_compile")
S
From: Emil Velikov
Earlier commit converted ES1 and ES2 to a new, much simpler, dispatch
generator. At the same time, GL/glapi and the driver side are still
using the old code.
There is a hidden ABI between GL*.so and glapi.so, former referencing
entry-points by offset in the _glapi_table. Hence
In a fragment shader, r0 is written out with a special branch sequence.
r0 is not a real register here, but essentially a pipeline register --
as such, it needs to be written out in full and on time, with hanging
dependencies in the bundle. Otherwise, we break up the bundle, which
costs an extra AL
The RA rewrite / schedler refactor series changed huge portions of the
Midgard codebase. Inevitably, that introduced a few hundred regressions
or so on dEQP. Fix them before anyone noticed.
Nothing to see here, folks.
Alyssa Rosenzweig (2):
panfrost/midgard: Fix cubemap regression
panfrost/mi
Fixes: 2d9802233 ("panfrost/midgard: Extend RA to non-vec4 sources")
Signed-off-by: Alyssa Rosenzweig
---
src/gallium/drivers/panfrost/midgard/midgard_ra.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/panfrost/midgard/midgard_ra.c
b/src/gal
Patch series Reviewed-By: Ryan Houdek
On Wed, Jun 5, 2019 at 8:41 AM Alyssa Rosenzweig <
alyssa.rosenzw...@collabora.com> wrote:
> This series adds some new ALU ops from OpenCL (cherry-picked from my
> downstream tree -- the full set of OpenCL-related ISA additions should
> be coming soon). In p
https://bugs.freedesktop.org/show_bug.cgi?id=110763
Michel Dänzer changed:
What|Removed |Added
Version|unspecified |19.0
QA Contact|xorg-t...@lists
Certain ops that only take one argument have an imaginary "zero"
constant for their second argument. For instance, conversions:
i2f [dest], [source], #0
Memory corruption meant that #0 was instead random noise. For some ops,
that doesn't matter (manifested as abnormally large code size and poo
These ops are used to accelerate various functions exposed in OpenCL.
This commit only includes the routine additions to the table. They are
not wired through the compiler; rather, they are just here to keep a
reference for the disassembler.
Signed-off-by: Alyssa Rosenzweig
---
src/gallium/drive
We use the shared nir_lower_idiv pass to lower integer division, fixing
144 dEQP tests. This pass was not applied in the past due to breakage
from iabs fixed earlier in the series.
Signed-off-by: Alyssa Rosenzweig
---
.../drivers/panfrost/ci/expected-failures.txt | 144 --
.../pa
This series adds some new ALU ops from OpenCL (cherry-picked from my
downstream tree -- the full set of OpenCL-related ISA additions should
be coming soon). In particular, it identifies iabs as iabsdiff/#0,
allowing an iabs bug to be fixed. From there, all prereqs are in place
to enable integer div
Reviewed-by: Samuel Pitoiset
On 6/5/19 5:09 PM, Connor Abbott wrote:
While we're here, copy the comment explaining this from radeonsi.
---
src/amd/common/ac_nir_to_llvm.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/comm
While we're here, copy the comment explaining this from radeonsi.
---
src/amd/common/ac_nir_to_llvm.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 833b1e54abc..11de22a8cbd 100644
--- a/src/amd/com
r-b
On Wed, Jun 5, 2019 at 12:02 PM Samuel Pitoiset
wrote:
>
> For some reasons, this actually introduced rendering issues with
> Far Cry 3 (and probably Far Cry 4). I'm reverting it for now
> until I figure out the right fix.
>
> See the following link for reference:
> https://github.com/ValveSo
When e9d935ed0e2 added force_dcc_off(), we forced it off for any
preloaded image descriptor which had stores associated with them, since
the same preloaded descriptors were used for loads and stores. However,
when the preloading was removed in 16be87c9042, the existing logic was
kept despite it not
On 6/5/19 2:51 AM, Bas Nieuwenhuizen wrote:
On Thu, May 30, 2019 at 4:02 PM Samuel Pitoiset
wrote:
From the Vulkan spec 1.1.109:
"Some implementations may need to evaluate depth image values
while performing image layout transitions. To accommodate this,
instances of the VkSamp
On 6/5/19 2:37 AM, Bas Nieuwenhuizen wrote:
On Thu, May 30, 2019 at 4:02 PM Samuel Pitoiset
wrote:
This will be used for the depth decompress pass that might need
to emit variable sample locations during layout transitions.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_meta.c | 20
For some reasons, this actually introduced rendering issues with
Far Cry 3 (and probably Far Cry 4). I'm reverting it for now
until I figure out the right fix.
See the following link for reference:
https://github.com/ValveSoftware/Proton/issues/727#issuecomment-498638025
Cc: 19.0 19.1
This rever
https://bugs.freedesktop.org/show_bug.cgi?id=110811
--- Comment #6 from Andrew Sheldon ---
(In reply to Samuel Pitoiset from comment #5)
> Does https://reviews.llvm.org/D62614 help?
No change, unfortunately.
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https://bugs.freedesktop.org/show_bug.cgi?id=110815
--- Comment #7 from Alex Fuller ---
Hello again,
I didn't realise it was so simple to build debug versions of Mesa/RADV so I
went ahead and did this.
I've found the bug:
https://gitlab.freedesktop.org/mesa/mesa/blob/master/src/amd/vulkan/radv_
Awesome, thanks for the fix.
Reviewed-By: Ryan Houdek
On Tue, Jun 4, 2019 at 11:55 PM Tomeu Vizoso
wrote:
> The compiler configuration was hardened to fail on format warnings and
> things stopped building.
>
> Fixes: c9c1e2610647 ("mesa: prevent common string formatting security
> issues")
> Si
The mesa/st flips the viewport, so we respect that rather than
trying to flip the framebuffer itself and ignoring the viewport and
using a messy heuristic.
However, this brings an underlying disagreement about the interpretation
of winding order to light. The blob uses a different strategy than Me
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