Hi Everyone,
I made changed changes to the patch as per @Rob Clark
comments
and I verified all the API functions with sample code, they are
working fine.
Please merge the MR:
https://gitlab.freedesktop.org/mesa/mesa/merge_requests/47 if there are no
changes
Thanks & Happy New Year
Veluri.
On W
Quoting Jan Vesely (2018-12-29 08:22:55)
> On Wed, 2018-12-26 at 15:26 +, Eric Engestrom wrote:
> > On Tuesday, 2018-12-25 23:09:53 +0100, Jan Vesely wrote:
> > > Guess my meson-fu is still pretty weak.
> > > Now I see the build failure again:
> > > In file included from ../mesa/src/intel/vulka
https://bugs.freedesktop.org/show_bug.cgi?id=109202
--- Comment #1 from Dylan Baker ---
You've either added -no-rtti or are using llvm built without rtti. I can make
this a hard error.
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https://bugs.freedesktop.org/show_bug.cgi?id=109202
Bug ID: 109202
Summary: nv50_ir.cpp:749:19: error: cannot use typeid with
-fno-rtti
Product: Mesa
Version: git
Hardware: x86-64 (AMD64)
OS: Linux (All)
https://bugs.freedesktop.org/show_bug.cgi?id=109201
Bug ID: 109201
Summary: Deep Rock Galactic: GPU Hang
Product: Mesa
Version: git
Hardware: x86-64 (AMD64)
OS: Linux (All)
Status: NEW
Severity: normal
https://bugs.freedesktop.org/show_bug.cgi?id=109201
Alexander changed:
What|Removed |Added
Version|git |18.3
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On Wed, Dec 19, 2018 at 12:50:54PM +0100, Iago Toral Quiroga wrote:
> From the Skylake PRM, Extended Math Function:
>
> "The execution size must be no more than 8 when half-floats
>are used in source or destination operand."
>
> Earlier generations do not support Extended Math with half-flo
On Wed, Dec 19, 2018 at 12:50:47PM +0100, Iago Toral Quiroga wrote:
> v2:
> - make 16-bit be its own separate case (Jason)
>
> Reviewed-by: Topi Pohjolainen (v1)
This version also.
> ---
> src/intel/compiler/brw_fs_nir.cpp | 18 +-
> 1 file changed, 17 insertions(+), 1 deletio
On Wed, Dec 19, 2018 at 12:50:44PM +0100, Iago Toral Quiroga wrote:
> There are some hardware restrictions that brw_nir_lower_conversions should
> have taken care of before we get here.
This patch and v2 of the previous:
Reviewed-by: Topi Pohjolainen
> ---
> src/intel/compiler/brw_fs_nir.cpp |
On Wed, Dec 19, 2018 at 12:50:42PM +0100, Iago Toral Quiroga wrote:
> Going forward having these split is a bit more convenient since these two
> groups have different restrictions.
Reviewed-by: Topi Pohjolainen
> ---
> src/intel/compiler/brw_fs_nir.cpp | 8
> 1 file changed, 8 inserti
https://bugs.freedesktop.org/show_bug.cgi?id=109190
Bug ID: 109190
Summary: virgl: buffer flushing error with some dEQP tests
[bisected]
Product: Mesa
Version: git
Hardware: Other
OS: All
Status:
On Wed, Dec 19, 2018 at 12:50:41PM +0100, Iago Toral Quiroga wrote:
> ---
> src/intel/compiler/brw_fs_nir.cpp | 55 ++-
> 1 file changed, 33 insertions(+), 22 deletions(-)
Reviewed-by: Topi Pohjolainen
>
> diff --git a/src/intel/compiler/brw_fs_nir.cpp
> b/src/inte
On Wed, Dec 19, 2018 at 12:50:40PM +0100, Iago Toral Quiroga wrote:
> Some conversions are not directly supported in hardware and need to be
> split in two conversion instructions going through an intermediary type.
> Doing this at the NIR level simplifies a bit the complexity in the backend.
I li
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