Re: [Mesa-dev] Make Jordan an Owner of the mesa project?

Ack. On Mon, Dec 3, 2018, 7:49 PM Jason Ekstrand Jordan has requested to be made an Owner of the mesa project. As much as > I may be the guy who pushed to get everything set up, I don't want to do > this sort of thing on my own. As such, I'm asking for some ACKs. If I can > get 5 ACKs (at leas

Re: [Mesa-dev] Lets talk about autotools

Hi Dylan, The architecture name in Debian is definitely ppc64el (not ppc64le). However, it's the IBM Power platform (POWER8) running in little endian mode (which yes, is confusing). https://wiki.debian.org/ppc64el https://wiki.debian.org/ArchiveQualification/ppc64el FWIW: Apparently there's fr

[Mesa-dev] [PATCH 34/59] intel/compiler: fix ddy for half-float in gen8

We use ALign16 mode for this, since it is more convenient, but the PRM for Broadwell states in Volume 3D Media GPGPU, Chapter 'Register region restrictions', Section '1. Special Restrictions': "In Align16 mode, the channel selects and channel enables apply to a pair of half-floats, because

[Mesa-dev] [PATCH 37/59] anv/pipeline: support SpvCapabilityFloat16 in gen8+

--- src/intel/vulkan/anv_pipeline.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index ee37685fccf..5b583c28582 100644 --- a/src/intel/vulkan/anv_pipeline.c +++ b/src/intel/vulkan/anv_pipeline.c @@ -146,6 +146,7 @@ anv_shader

[Mesa-dev] [PATCH 25/59] intel/compiler: add new half-float register type for 3-src instructions

This is available since gen8. --- src/intel/compiler/brw_reg_type.c | 35 +++ 1 file changed, 31 insertions(+), 4 deletions(-) diff --git a/src/intel/compiler/brw_reg_type.c b/src/intel/compiler/brw_reg_type.c index 60240ba1513..72295a2bd75 100644 --- a/src/intel/comp

[Mesa-dev] [PATCH 53/59] intel/compiler: implement is_zero, is_one, is_negative_one for 8-bit/16-bit

There are no 8-bit immediates, so assert in that case. 16-bit immediates are replicated in each word of a 32-bit immediate, so we only need to check the lower 16-bits. --- src/intel/compiler/brw_shader.cpp | 20 1 file changed, 20 insertions(+) diff --git a/src/intel/compiler

[Mesa-dev] [PATCH 15/59] intel/compiler: lower 16-bit extended math to 32-bit prior to gen9

Extended math desn't support half-float on these generations. --- src/intel/compiler/brw_nir.c | 13 - 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c index e0027f5179c..0b3094724c4 100644 --- a/src/intel/compile

[Mesa-dev] [PATCH 24/59] intel/compiler: add instruction setters for Src1Type and Src2Type.

The original SrcType is a 3-bit field that takes a subset of the types supported for the hardware for 3-source instructions. Since gen8, when the half-float type was added, 3-source floating point operations can use use mixed precision mode, where not all the operands have the same floating-point p

[Mesa-dev] [PATCH 42/59] intel/compiler: activate 16-bit bit-size lowerings also for 8-bit

Particularly, we need the same lowewrings we use for 16-bit integers. --- src/intel/compiler/brw_nir.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c index 0b3094724c4..0a5aa35c700 100644 --- a/src/intel/compiler/brw_

[Mesa-dev] [PATCH 56/59] intel/compiler: support half-float in the combine constants pass

--- .../compiler/brw_fs_combine_constants.cpp | 60 +++ 1 file changed, 49 insertions(+), 11 deletions(-) diff --git a/src/intel/compiler/brw_fs_combine_constants.cpp b/src/intel/compiler/brw_fs_combine_constants.cpp index e0c95d379b8..24307e365ab 100644 --- a/src/intel/compi

[Mesa-dev] [PATCH 49/59] intel/eu: force stride of 2 on NULL register for Byte instructions

The hardware only allows a stride of 1 on a Byte destination for raw byte MOV instructions. This is required even when the destination is the NULL register. Rather than making sure that we emit a proper NULL:B destination every time we need one, just fix it at emission time. --- src/intel/compile

[Mesa-dev] [PATCH 08/59] compiler/spirv: implement 16-bit frexp

--- src/compiler/spirv/vtn_glsl450.c | 48 ++-- 1 file changed, 46 insertions(+), 2 deletions(-) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c index 85851755aab..bb340c87416 100644 --- a/src/compiler/spirv/vtn_glsl450.c +++ b/src/comp

[Mesa-dev] [PATCH 54/59] intel/compiler: add a brw_reg_type_is_integer helper

--- src/intel/compiler/brw_reg_type.h | 18 ++ 1 file changed, 18 insertions(+) diff --git a/src/intel/compiler/brw_reg_type.h b/src/intel/compiler/brw_reg_type.h index ffbec90d3fe..a3365b7e34c 100644 --- a/src/intel/compiler/brw_reg_type.h +++ b/src/intel/compiler/brw_reg_type.h

[Mesa-dev] [PATCH 40/59] anv/extensions: expose VK_KHR_shader_float16_int8 on gen8+

--- src/intel/vulkan/anv_extensions.py | 1 + 1 file changed, 1 insertion(+) diff --git a/src/intel/vulkan/anv_extensions.py b/src/intel/vulkan/anv_extensions.py index 7c81228f705..9ca42d998ef 100644 --- a/src/intel/vulkan/anv_extensions.py +++ b/src/intel/vulkan/anv_extensions.py @@ -104,6 +104

[Mesa-dev] [PATCH 01/59] compiler/spirv: handle 16-bit float in radians() and degrees()

Reviewed-by: Jason Ekstrand --- src/compiler/nir/nir_builtin_builder.h | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/compiler/nir/nir_builtin_builder.h b/src/compiler/nir/nir_builtin_builder.h index 0e5b9db462a..1f5a1a12533 100644 --- a/src/compiler/nir/nir_buil

[Mesa-dev] [PATCH 07/59] compiler/spirv: implement 16-bit hyperbolic trigonometric functions

--- src/compiler/spirv/vtn_glsl450.c | 29 +++-- 1 file changed, 19 insertions(+), 10 deletions(-) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c index 8bdef9db822..85851755aab 100644 --- a/src/compiler/spirv/vtn_glsl450.c +++ b/src/compil

[Mesa-dev] [PATCH 48/59] intel/compiler: implement isign for int8

--- src/intel/compiler/brw_fs_nir.cpp | 25 + 1 file changed, 21 insertions(+), 4 deletions(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index db3a8812ae3..7a4594a24ac 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/

[Mesa-dev] [PATCH 58/59] intel/compiler: implement MAD algebraic optimizations on half-float

--- src/intel/compiler/brw_fs.cpp | 46 +-- 1 file changed, 33 insertions(+), 13 deletions(-) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 9ea67975e1e..32e0817ce02 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compil

[Mesa-dev] [PATCH 12/59] intel/compiler: handle b2i/b2f with other integer conversion opcodes

Since we handle booleans as integers this makes more sense. --- src/intel/compiler/brw_fs_nir.cpp | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 9f3d3bf9762..6c765fc2661 100644 --- a/src/in

[Mesa-dev] [PATCH 47/59] intel/compiler: assert that lower conversions produces valid strides

The hardware only has two bits to specify the horizontal stride, so the maximum horizontal stride we can use is 4. The pass calculates strides based on the sizes of the types involved, and for conversions between 64-bit and 8-bit types that can lead to strides of 8. The compiler should make sure t

[Mesa-dev] [PATCH 57/59] intel/compiler: fix combine constants for Align16 with half-float prior to gen9

There is a hardware restriction where <0,1,0>:HF in Align16 doesn't replicate a single 16-bit channel, but instead it replicates a full 32-bit channel. --- .../compiler/brw_fs_combine_constants.cpp | 24 +-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/src/int

[Mesa-dev] [PATCH 45/59] intel/compiler: implement conversions from 16-bit float to 8-bit int

--- src/intel/compiler/brw_fs_nir.cpp | 18 ++ 1 file changed, 18 insertions(+) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 4f815fef891..3f98c6a4474 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp

[Mesa-dev] [PATCH 27/59] intel/compiler: allow half-float on 3-source instructions since gen8

--- src/intel/compiler/brw_eu_emit.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c index 5f066d17a1f..2c9fc9a5c7c 100644 --- a/src/intel/compiler/brw_eu_emit.c +++ b/src/intel/compiler/brw_eu_emit.c @@ -755

[Mesa-dev] [PATCH 51/59] anv/pipeline: support SpvCapabilityInt8 in gen8+

--- src/intel/vulkan/anv_pipeline.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index 5b583c28582..d55e51adcbb 100644 --- a/src/intel/vulkan/anv_pipeline.c +++ b/src/intel/vulkan/anv_pipeline.c @@ -147,6 +147,7 @@ anv_shader

[Mesa-dev] [PATCH 52/59] anv/device: expose shaderInt8 feature

--- src/intel/vulkan/anv_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c index caf25ad8a03..17b73c115cd 100644 --- a/src/intel/vulkan/anv_device.c +++ b/src/intel/vulkan/anv_device.c @@ -971,7 +971,7 @@ void

[Mesa-dev] [PATCH 50/59] compiler/spirv: add implementation to check for SpvCapabilityInt8

--- src/compiler/shader_info.h| 1 + src/compiler/spirv/spirv_to_nir.c | 4 +++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/src/compiler/shader_info.h b/src/compiler/shader_info.h index 0a3cb37069c..e745cc15fc5 100644 --- a/src/compiler/shader_info.h +++ b/src/compiler/s

[Mesa-dev] [PATCH 13/59] intel/compiler: simplify f2*64 opcodes

Now that this case only handles 64-bit destinations we can simplify a bit the code. --- src/intel/compiler/brw_fs_nir.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 6c765fc2661..3eba8a478f5 100644

[Mesa-dev] [PATCH 44/59] intel/compiler: implement conversions from 8-bit int to 64-bit

There are hardware restrictions that need to be considered. --- src/intel/compiler/brw_fs_nir.cpp | 23 ++- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index c1ba799d59c..4f815fef891 10064

[Mesa-dev] [PATCH 59/59] intel/compiler: allow propagating HF immediates to MAD/LRP

--- src/intel/compiler/brw_fs_copy_propagation.cpp | 17 - 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/src/intel/compiler/brw_fs_copy_propagation.cpp b/src/intel/compiler/brw_fs_copy_propagation.cpp index 0f0284115fb..3d0fe883324 100644 --- a/src/intel/compiler/b

[Mesa-dev] [PATCH 43/59] intel/compiler: fix conversions from 64-bit to 8-bit int

These need to be implemented in two steps using an intermediary type. --- src/intel/compiler/brw_fs_nir.cpp | 11 +++ 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 559b55a0f84..c1ba799d59c 100644 -

[Mesa-dev] [PATCH 22/59] compiler/nir: add lowering for 16-bit ldexp

--- src/compiler/nir/nir_opt_algebraic.py | 5 + 1 file changed, 5 insertions(+) diff --git a/src/compiler/nir/nir_opt_algebraic.py b/src/compiler/nir/nir_opt_algebraic.py index 6c3b77c9b6e..747f1751086 100644 --- a/src/compiler/nir/nir_opt_algebraic.py +++ b/src/compiler/nir/nir_opt_algebra

[Mesa-dev] [PATCH 26/59] intel/compiler: don't compact 3-src instructions with Src1Type or Src2Type bits

We are now using these bits, so don't assert that they are not set, just avoid compaction in that case. --- src/intel/compiler/brw_eu_compact.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_eu_compact.c b/src/intel/compiler/brw_eu_compact.c index a

[Mesa-dev] [PATCH 29/59] intel/compiler: don't propagate HF immediates to 3-src instructions

3-src instructions don't support immediates, but since 36bc5f06dd22, we allow them on MAD and LRP relying on the combine constants pass to fix it up later. However, that pass is specialized for 32-bit float immediates and can't handle HF constants at present, so this patch ensures that copy-propaga

[Mesa-dev] [PATCH 55/59] intel/compiler: fix cmod propagation for non 32-bit types

--- src/intel/compiler/brw_fs_cmod_propagation.cpp | 8 +++- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/src/intel/compiler/brw_fs_cmod_propagation.cpp b/src/intel/compiler/brw_fs_cmod_propagation.cpp index 7bb5c9afbc9..dfef9d720a2 100644 --- a/src/intel/compiler/brw_fs_cmod

[Mesa-dev] [PATCH 46/59] intel/compiler: fix integer to/from half-float in atom platforms

Section Register Region Restriction of the 3D Media GPGPU chapter states: "Conversion between Integer and HF (Half Float) must be DWord aligned and strided by a DWord on the destination." The same restriction shows up in all hardware platforms that support half-float, however, empirical te

[Mesa-dev] [PATCH 30/59] intel/compiler: document MAD algebraic optimization

This optimization depends on two other optimization passes: the constant propagation pass, which allows immediate propagation on MAD/LRP instructions even though the hardware can't do it, and the combine constants pass to fix this up afterwards for the cases that we could not optimize here. Also,

[Mesa-dev] [PATCH 11/59] intel/compiler: Implement float64/int64 to float16 conversion

From: Samuel Iglesias Gonsálvez It is not supported directly in the HW, we need to convert to a 32-bit type first as intermediate step. v2 (Iago): handle conversions from 64-bit integers as well Signed-off-by: Samuel Iglesias Gonsálvez --- src/intel/compiler/brw_fs_nir.cpp | 42 ++

[Mesa-dev] [PATCH 28/59] intel/compiler: set correct precision fields for 3-source float instructions

Source0 and Destination extract the floating-point precision automatically from the SrcType and DstType instruction fields respectively when they are set to types :F or :HF. For Source1 and Source2 operands, we use the new 1-bit fields Src1Type and Src2Type, where 0 means normal precision and 1 mea

[Mesa-dev] [PATCH 31/59] intel/compiler: fix ddx and ddy for 16-bit float

We were assuming 32-bit elements. --- src/intel/compiler/brw_fs_generator.cpp | 34 + 1 file changed, 18 insertions(+), 16 deletions(-) diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp index 08dd83dded7..bffd9bc4787 100644 ---

[Mesa-dev] [PATCH 38/59] vulkan: import Khronos header and xml version 95

--- include/vulkan/vulkan_core.h | 109 +++-- src/vulkan/registry/vk.xml | 130 +++ 2 files changed, 204 insertions(+), 35 deletions(-) diff --git a/include/vulkan/vulkan_core.h b/include/vulkan/vulkan_core.h index 35c06649aa5..50064109ef3

[Mesa-dev] [PATCH 33/59] intel/compiler: do not copy-propagate strided regions to ddx/ddy arguments

The implementation of these opcodes in the generator assumes that their arguments are packed, and it generates register regions based on that assumption. While this expectation is reasonable for 32-bit, when we load 16-bit elements from UBOs we get them with a stride of 2 that we then need to pack

[Mesa-dev] [PATCH 41/59] intel/compiler: split is_partial_write() into two variants

This function is used in two different scenarios that for 32-bit instructions are the same, but for 16-bit instructions are not. One scenario is that in which we are working at a SIMD8 register level and we need to know if a register is fully defined or written. This is useful, for example, in the

[Mesa-dev] [PATCH 09/59] compiler/spirv: use 32-bit polynomial approximation for 16-bit asin()

The 16-bit polynomial execution doesn't meet Khronos precision requirements. Also, the half-float denorm range starts at 2^(-14) and with asin taking input values in the range [0, 1], polynomial approximations can lead to flushing relatively easy. An alternative is to use the atan2 formula to comp

[Mesa-dev] [PATCH 23/59] intel/compiler: Extended Math is limited to SIMD8 on half-float

From the Skylake PRM, Extended Math Function: "The execution size must be no more than 8 when half-floats are used in source or destination operand." Earlier generations do not support Extended Math with half-float. --- src/intel/compiler/brw_fs.cpp | 30 +++--- 1 fi

[Mesa-dev] [PATCH 39/59] anv/device: expose support for shaderFloat16 in gen8+

--- src/intel/vulkan/anv_device.c | 9 + 1 file changed, 9 insertions(+) diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c index 6b5ba25c6bc..caf25ad8a03 100644 --- a/src/intel/vulkan/anv_device.c +++ b/src/intel/vulkan/anv_device.c @@ -966,6 +966,15 @@ void anv_G

[Mesa-dev] [PATCH 21/59] intel/compiler: lower 16-bit flrp

Reviewed-by: Jason Ekstrand --- src/intel/compiler/brw_compiler.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/intel/compiler/brw_compiler.c b/src/intel/compiler/brw_compiler.c index f885e79c3e6..04a1a7cac4e 100644 --- a/src/intel/compiler/brw_compiler.c +++ b/src/intel/compiler/brw_c

[Mesa-dev] [PATCH 35/59] intel/compiler: workaround for SIMD8 half-float MAD in gen < 9

Broadwell hardware has a bug that manifests in SIMD8 executions of 16-bit MAD instructions when any of the sources is a Y or W component. We pack these components in the same SIMD register as components X and Z respectively, but starting at offset 16B (so they live in the second half of the registe

[Mesa-dev] [PATCH 32/59] intel/compiler: fix 16-bit float ddx and ddy for SIMD8

In SIMD8 we pack 2 vector components in a single SIMD register, so for example, component Y of a 16-bit vec2 starts is at byte offset 16B. This means that when we compute the offset of the elements to be differentiated we should not stomp whatever base offset we have, but instead add to it. --- sr

[Mesa-dev] [PATCH 20/59] compiler/nir: add lowering for 16-bit flrp

Reviewed-by: Jason Ekstrand --- src/compiler/nir/nir.h| 1 + src/compiler/nir/nir_opt_algebraic.py | 1 + 2 files changed, 2 insertions(+) diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h index 25ed64aa73c..65a1f60c3c6 100644 --- a/src/compiler/nir/nir.h +++ b/src/com

[Mesa-dev] [PATCH 17/59] intel/compiler: allow extended math functions with HF operands

The PRM states that half-float operands are supported since gen9. --- src/intel/compiler/brw_eu_emit.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c index 4630b83b1a0..5f066d17a1f 100644 --- a/src/intel

[Mesa-dev] [PATCH 19/59] intel/compiler: lower 16-bit fmod

Reviewed-by: Jason Ekstrand --- src/intel/compiler/brw_compiler.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/intel/compiler/brw_compiler.c b/src/intel/compiler/brw_compiler.c index fe632c5badc..f885e79c3e6 100644 --- a/src/intel/compiler/brw_compiler.c +++ b/src/intel/compiler/brw_c

[Mesa-dev] [PATCH 18/59] compiler/nir: add lowering option for 16-bit fmod

Reviewed-by: Jason Ekstrand --- src/compiler/nir/nir.h| 1 + src/compiler/nir/nir_opt_algebraic.py | 1 + 2 files changed, 2 insertions(+) diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h index db935c8496b..25ed64aa73c 100644 --- a/src/compiler/nir/nir.h +++ b/src/com

[Mesa-dev] [PATCH 14/59] intel/compiler: lower some 16-bit float operations to 32-bit

The hardware doesn't support half-float for these. --- src/intel/compiler/brw_nir.c | 5 + 1 file changed, 5 insertions(+) diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c index aa6788b9fe5..e0027f5179c 100644 --- a/src/intel/compiler/brw_nir.c +++ b/src/intel/compiler

[Mesa-dev] [PATCH 36/59] compiler/spirv: add implementation to check for SpvCapabilityFloat16 support

--- src/compiler/shader_info.h| 1 + src/compiler/spirv/spirv_to_nir.c | 4 +++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/src/compiler/shader_info.h b/src/compiler/shader_info.h index 65bc0588d67..0a3cb37069c 100644 --- a/src/compiler/shader_info.h +++ b/src/compiler/s

[Mesa-dev] [PATCH 16/59] intel/compiler: implement 16-bit fsign

--- src/intel/compiler/brw_fs_nir.cpp | 27 +-- 1 file changed, 21 insertions(+), 6 deletions(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 3eba8a478f5..559b55a0f84 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/inte

[Mesa-dev] [PATCH 03/59] compiler/spirv: implement 16-bit acos

--- src/compiler/spirv/vtn_glsl450.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c index e85123725da..4345c9c61a3 100644 --- a/src/compiler/spirv/vtn_glsl450.c +++ b/src/compiler/spirv/vtn_glsl450.c @@ -

[Mesa-dev] [PATCH 02/59] compiler/spirv: implement 16-bit asin

--- src/compiler/spirv/vtn_glsl450.c | 20 +--- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c index 06a49e48e3f..e85123725da 100644 --- a/src/compiler/spirv/vtn_glsl450.c +++ b/src/compiler/spirv/v

[Mesa-dev] [PATCH 06/59] compiler/spirv: implement 16-bit exp and log

Reviewed-by: Jason Ekstrand --- src/compiler/spirv/vtn_glsl450.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c index f05531dbad6..8bdef9db822 100644 --- a/src/compiler/spirv/vtn_glsl450.c +++ b/src/comp

[Mesa-dev] [PATCH 04/59] compiler/spirv: implement 16-bit atan

--- src/compiler/spirv/vtn_glsl450.c | 36 +--- 1 file changed, 24 insertions(+), 12 deletions(-) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c index 4345c9c61a3..9cda80c5137 100644 --- a/src/compiler/spirv/vtn_glsl450.c +++ b/src/com

[Mesa-dev] [PATCH 05/59] compiler/spirv: implement 16-bit atan2

v2: fix huge_val for 16-bit, it was mean't to be 2^14 not 10^14. --- src/compiler/spirv/vtn_glsl450.c | 21 ++--- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c index 9cda80c5137..f05531dbad6 100644

[Mesa-dev] [PATCH 00/59] intel: VK_KHR_shader_float16_int8 implementation

Hi, this series implements support for VK_KHR_shader_float16_int8 for Intel platforms (Broadwell and later). This extension enables Vulkan applications to consume SPIR-V shaders that use Float16 and Int8 types in shader code, extending the functionality included with VK_KHR_16bit_storage and VK_KH

[Mesa-dev] [PATCH 10/59] intel/compiler: implement conversions from 16-bit float to 64-bit

Signed-off-by: Samuel Iglesias Gonsálvez --- src/intel/compiler/brw_fs_nir.cpp | 41 +++ 1 file changed, 41 insertions(+) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 6eb68794f58..7294f49ddc0 100644 --- a/src/intel/compiler

Re: [Mesa-dev] [PATCH 04/11] st/mesa: Use Array._DrawVAO in st_atom_array.c.

Hey, On Monday, 3 December 2018 12:15:17 CET Erik Faye-Lund wrote: > Yeah. An important thing to note is that virgl is pretty widely tested > by now, and we don't see this pop up in other places... And that sounds > a bit strange to me. Good to know, I don't actually know how wide virgl is alread

Re: [Mesa-dev] [PATCH 04/11] nir: make use of new nir_cf_list_clone_and_reinsert() helper

Den tir. 20. nov. 2018 kl. 09:15 skrev Timothy Arceri : > > --- > src/compiler/nir/nir_opt_loop_unroll.c | 74 ++ > 1 file changed, 28 insertions(+), 46 deletions(-) > > diff --git a/src/compiler/nir/nir_opt_loop_unroll.c > b/src/compiler/nir/nir_opt_loop_unroll.c > index

[Mesa-dev] [Bug 108922] Meson: crosscompiling with a crossfile seems to fail

https://bugs.freedesktop.org/show_bug.cgi?id=108922 Alexandre Demers changed: What|Removed |Added Resolution|--- |INVALID Status|NEW

[Mesa-dev] [Bug 108922] Meson: crosscompiling with a crossfile fails

https://bugs.freedesktop.org/show_bug.cgi?id=108922 Alexandre Demers changed: What|Removed |Added Summary|Meson: crosscompiling with |Meson: crosscompiling with

Re: [Mesa-dev] Make Jordan an Owner of the mesa project?

Jason Ekstrand writes: > Jordan has requested to be made an Owner of the mesa project. As much as I > may be the guy who pushed to get everything set up, I don't want to do this > sort of thing on my own. As such, I'm asking for some ACKs. If I can get > 5 ACKs (at least 2 non-intel) from othe

Re: [Mesa-dev] GitLab merge requests, discussion summary - Re: [PATCH] docs: Document optional GitLab code review process

Jordan Justen writes: > Lots of discussion here. :) I hoped to just dip our toes into the > merge request stream, but the consensus is clearly against my idea. Oh > well. :) > > Here's what I gathered from the discussion: > > == Keep email, allow duplicate MR, my idea == > > I don't think anyone

Re: [Mesa-dev] [PATCH v3 1/3] nir: add glsl_replace_vector_type()

Ping! on the series ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] Partial loop unrolling support v2

Ping! On 20/11/18 7:14 pm, Timothy Arceri wrote: This series add support for partial loop unrolling for loops with an unknown trip count. The new partial_unroll function allows the caller to specifiy how may times the loop should be unrolled and then the loop is inserted in the innermost continu

[Mesa-dev] [PATCH 1/2] nvc0: replace use of explicit default_tsc with entry 0

This was used for implementing FBFETCH. However that uses TXF, which doesn't do much with a TSC. The only important bit is that sRGB-decoding works as expected, which we can achieve since all samplers we ever generate enable sRGB-decoding. Always point to entry 0 in the TSC table, and ensure that e

[Mesa-dev] [PATCH 2/2] NEEDS TEST nvc0: always keep TSC slot 0 bound to fix TXF

Same as on nv50, the TXF op always uses the TSC bound to slot 0, returning blank values if nothing is bound. An earlier change arranges for the TSC entries list to always have valid data at entry 0, so here we just make use of it. Fixes arb_texture_buffer_object-subdata-sync among others. Signed

[Mesa-dev] [PATCH 1/2] nir: add support for marking used patches when packing varyings

This adds support needed for marking the varyings as used but we don't actually support packing patches in this patch. --- src/compiler/nir/nir_linking_helpers.c | 73 ++ 1 file changed, 51 insertions(+), 22 deletions(-) diff --git a/src/compiler/nir/nir_linking_helpers.c

[Mesa-dev] [RFC 2/2] nir: rewrite varying component packing

There are three reasons for the rewrite. 1. Adding support for packing tess patch varyings in a sane way. 2. Making use of qsort allowing the code to be much easier to follow. 3. Adding a crude live range analysis for deciding which components should be packed together. We could simplify

Re: [Mesa-dev] GitLab merge requests, discussion summary - Re: [PATCH] docs: Document optional GitLab code review process

Seems like a pretty good sum-up of the discussion to me. On Mon, Dec 3, 2018 at 7:50 PM Jordan Justen wrote: > Lots of discussion here. :) I hoped to just dip our toes into the > merge request stream, but the consensus is clearly against my idea. Oh > well. :) > > Here's what I gathered from the

[Mesa-dev] GitLab merge requests, discussion summary - Re: [PATCH] docs: Document optional GitLab code review process

Lots of discussion here. :) I hoped to just dip our toes into the merge request stream, but the consensus is clearly against my idea. Oh well. :) Here's what I gathered from the discussion: == Keep email, allow duplicate MR, my idea == I don't think anyone else was in favor of this. Several were

Re: [Mesa-dev] Make Jordan an Owner of the mesa project?

On Mon, Dec 3, 2018 at 7:05 PM Ilia Mirkin wrote: > On Mon, Dec 3, 2018 at 7:49 PM Jason Ekstrand > wrote: > > > > Jordan has requested to be made an Owner of the mesa project. As much > as I may be the guy who pushed to get everything set up, I don't want to do > this sort of thing on my own.

Re: [Mesa-dev] [PATCH 0/7] EGLDevice, take 2.1

On Mon, Dec 3, 2018 at 8:06 AM Emil Velikov wrote: > Hi Gurchetan, > > On Thu, 29 Nov 2018 at 23:41, Gurchetan Singh > wrote: > > > > Does this require libdrm 2.4.95 for virtio-gpu? With > > platform_surfaceless, I keep getting "DRI2: failed to find EGLDevice" > > and the failure is happening i

Re: [Mesa-dev] Make Jordan an Owner of the mesa project?

On Mon, Dec 3, 2018 at 7:49 PM Jason Ekstrand wrote: > > Jordan has requested to be made an Owner of the mesa project. As much as I > may be the guy who pushed to get everything set up, I don't want to do this > sort of thing on my own. As such, I'm asking for some ACKs. If I can get 5 > ACK

Re: [Mesa-dev] Make Jordan an Owner of the mesa project?

On Tue, Dec 4, 2018 at 10:49 AM Jason Ekstrand wrote: > > Jordan has requested to be made an Owner of the mesa project. As much as I > may be the guy who pushed to get everything set up, I don't want to do this > sort of thing on my own. As such, I'm asking for some ACKs. If I can get 5 > AC

[Mesa-dev] Make Jordan an Owner of the mesa project?

Jordan has requested to be made an Owner of the mesa project. As much as I may be the guy who pushed to get everything set up, I don't want to do this sort of thing on my own. As such, I'm asking for some ACKs. If I can get 5 ACKs (at least 2 non-intel) from other Owners and no NAKs, I'll click

[Mesa-dev] [AppVeyor] mesa master #9463 completed

Build mesa 9463 completed Commit dd53bb7e1f by Matt Turner on 12/4/2018 12:20 AM: Revert "st/mesa: silenced unhanded enum warning in st_glsl_to_tgsi.cpp"\n\nThis reverts commit 198c50f4873758e9f64d89eea262af5dd1644df9.\n\nThis needs to be reverted after commit

Re: [Mesa-dev] [PATCH mesa] drop autotools

Quoting Bas Nieuwenhuizen (2018-12-03 14:14:19) > On Mon, Dec 3, 2018 at 7:30 PM Jan Vesely wrote: > > > > On Mon, 2018-12-03 at 10:21 +, Eric Engestrom wrote: > > > Cc: Emil Velikov > > > Cc: Andres Gomez > > > Cc: Juan A. Suarez Romero > > > Cc: Dylan Baker > > > Signed-off-by: Eric Enge

Re: [Mesa-dev] [AppVeyor] mesa master #9462 failed

This just broke for me locally: ../mesa/src/mesa/state_tracker/st_glsl_to_tgsi.cpp: In member function ‘virtual void glsl_to_tgsi_visitor::visit(ir_call*)’: ../mesa/src/mesa/state_tracker/st_glsl_to_tgsi.cpp:4075:9: error: ‘ir_intrinsic_begin_fragment_shader_ordering’ was not declared in this scop

[Mesa-dev] [AppVeyor] mesa master #9462 failed

Build mesa 9462 failed Commit 017199d2d2 by Matt Turner on 11/29/2018 11:46 PM: mesa: Revert INTEL_fragment_shader_ordering support\n\nThis extension is not properly tested (testing for\nGL_ARB_fragment_shader_interlock is not sufficient), and since this was\nn

Re: [Mesa-dev] [Mesa-stable] [PATCH] mesa: Revert INTEL_fragment_shader_ordering support

On Mon, Dec 3, 2018 at 8:12 AM Emil Velikov wrote: > > On Thu, 29 Nov 2018 at 23:54, Matt Turner wrote: > > > > This extension is not properly tested (testing for > > GL_ARB_fragment_shader_interlock is not sufficient), and since this was > > noted in review on August 28th no tests have been sent

Re: [Mesa-dev] [PATCH 1/9] intel/blorp: Only double the fast-clear rect alignment on HSW

I've received confirmation from the HW team that the extra doubling is only needed on Haswell GT3. On Tue, May 15, 2018 at 5:28 PM Jason Ekstrand wrote: > The data in the commit message is a bit sketchy for Ivybridge. We don't > run dEQP or any of the CTSs on Ivybridge in CI so all the data we

Re: [Mesa-dev] [PATCH 1/2] nir/algebraic: Rewrite bit-size inference

Quoting Jason Ekstrand (2018-12-03 14:12:41) > On Mon, Dec 3, 2018 at 3:50 PM Dylan Baker wrote: > > Quoting Connor Abbott (2018-11-29 10:32:02) > > Before this commit, there were two copies of the algorithm: one in C, > > that we would use to figure out what bit-size to give the repl

Re: [Mesa-dev] [PATCH 1/2] nir/algebraic: Rewrite bit-size inference

Quoting Jason Ekstrand (2018-12-03 14:12:41) > On Mon, Dec 3, 2018 at 3:50 PM Dylan Baker wrote: > > Quoting Connor Abbott (2018-11-29 10:32:02) > > Before this commit, there were two copies of the algorithm: one in C, > > that we would use to figure out what bit-size to give the repl

Re: [Mesa-dev] [PATCH] radv: rework the TC-compat HTILE hardware bug with COND_EXEC

On Mon, Dec 3, 2018 at 11:13 PM Samuel Pitoiset wrote: > > After investigating on this, it appears that COND_WRITE doesn't > work correctly in some situations. I don't know exactly why does > it fail to update DB_Z_INFO.ZRANGE_PRECISION, but as AMDVLK > also uses COND_EXEC I think there is a reaso

Re: [Mesa-dev] [PATCH mesa] drop autotools

On Mon, Dec 3, 2018 at 7:30 PM Jan Vesely wrote: > > On Mon, 2018-12-03 at 10:21 +, Eric Engestrom wrote: > > Cc: Emil Velikov > > Cc: Andres Gomez > > Cc: Juan A. Suarez Romero > > Cc: Dylan Baker > > Signed-off-by: Eric Engestrom > > --- > > This patch depends on the releasing procedure

[Mesa-dev] [Bug 108914] blocky shadow artifacts in The Forest with DXVK, RADV_DEBUG=nohiz fixes this

https://bugs.freedesktop.org/show_bug.cgi?id=108914 --- Comment #14 from Samuel Pitoiset --- Thanks for confirming. Patch is here: https://patchwork.freedesktop.org/series/53440/ -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.__

Re: [Mesa-dev] [PATCH 1/2] nir/algebraic: Rewrite bit-size inference

On Mon, Dec 3, 2018 at 3:50 PM Dylan Baker wrote: > Quoting Connor Abbott (2018-11-29 10:32:02) > > Before this commit, there were two copies of the algorithm: one in C, > > that we would use to figure out what bit-size to give the replacement > > expression, and one in Python, that emulated the

[Mesa-dev] [PATCH] radv: rework the TC-compat HTILE hardware bug with COND_EXEC

After investigating on this, it appears that COND_WRITE doesn't work correctly in some situations. I don't know exactly why does it fail to update DB_Z_INFO.ZRANGE_PRECISION, but as AMDVLK also uses COND_EXEC I think there is a reason. Now the driver stores a new metadata value in order to reflect

Re: [Mesa-dev] [PATCH] anv/query: flush render target before copying results

On Mon, Dec 3, 2018 at 11:26 AM Lionel Landwerlin < lionel.g.landwer...@intel.com> wrote: > This change tracks render target writes in the pipeline and applies a > render target flush before copying the query results to make sure the > preceding operations have landed in memory before the command

[Mesa-dev] [Bug 106958] Mass Effect Andromeda renders correctly on RX480 POLARIS but BAD ON RX VEGA 64 on wine 3.10 stagingf with DXVK

https://bugs.freedesktop.org/show_bug.cgi?id=106958 --- Comment #16 from Samuel Pitoiset --- Yes, if you have a key please send me one to my personal email. -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug._

Re: [Mesa-dev] [PATCH 1/2] nir/algebraic: Rewrite bit-size inference

Quoting Connor Abbott (2018-11-29 10:32:02) > Before this commit, there were two copies of the algorithm: one in C, > that we would use to figure out what bit-size to give the replacement > expression, and one in Python, that emulated the C one and tried to > prove that the C algorithm would never

[Mesa-dev] [Bug 108935] [LLVM Regression] Witcher 3 Corrupted Terrain

https://bugs.freedesktop.org/show_bug.cgi?id=108935 Bug ID: 108935 Summary: [LLVM Regression] Witcher 3 Corrupted Terrain Product: Mesa Version: git Hardware: x86-64 (AMD64) OS: Linux (All) Status: NEW Sev

Re: [Mesa-dev] [PATCH] vulkan: Update the XML and headers to 1.1.95

Thanks. Pushed. On Mon, Dec 3, 2018 at 10:50 AM Samuel Pitoiset wrote: > Acked-by: Samuel Pitoiset > > On 12/3/18 5:06 PM, Jason Ekstrand wrote: > > --- > > include/vulkan/vulkan_core.h | 109 +++-- > > src/vulkan/registry/vk.xml | 130 +++--

[Mesa-dev] [Bug 108914] blocky shadow artifacts in The Forest with DXVK, RADV_DEBUG=nohiz fixes this

https://bugs.freedesktop.org/show_bug.cgi?id=108914 --- Comment #13 from tempel.jul...@gmail.com --- (In reply to Samuel Pitoiset from comment #12) > Created attachment 142705 [details] [review] > possible fix > > Can you try the attached patch? It fixes the problem, thanks a lot. :) I also gav

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