I'm guessing your using GCC 8.2.1 to compile Mesa? There was a compiler bug:
https://bugzilla.redhat.com/show_bug.cgi?id=1645400
On 12/11/18 2:11 pm, Dieter Nützel wrote:
Hello,
I get brocken shaders with Blender and the above demos didn't start
any longer.
NOT NIR related.
Have to start bise
https://bugs.freedesktop.org/show_bug.cgi?id=108636
Tapani Pälli changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
On Sun, Nov 11, 2018 at 9:37 PM Timothy Arceri
wrote:
> On 12/11/18 2:11 pm, Jason Ekstrand wrote:
> > On November 11, 2018 20:30:29 Timothy Arceri
> wrote:
> >
> >> Fixes: 1c9c42d16b4c ("nir: add varying component packing helpers")
> >> ---
> >> src/compiler/nir/nir_linking_helpers.c | 9 ++
On 12/11/18 2:11 pm, Jason Ekstrand wrote:
On November 11, 2018 20:30:29 Timothy Arceri wrote:
Fixes: 1c9c42d16b4c ("nir: add varying component packing helpers")
---
src/compiler/nir/nir_linking_helpers.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/src/compiler
Hello,
I get brocken shaders with Blender and the above demos didn't start
any longer.
NOT NIR related.
Have to start bisect.
OpenGL renderer string: Radeon RX 580 Series (POLARIS10, DRM 3.27.0,
4.19.0-rc1-1.g7262353-default+, LLVM 8.0.0)
OpenGL core profile version string: 4.5 (Core Profile)
On November 11, 2018 20:30:29 Timothy Arceri wrote:
Fixes: 1c9c42d16b4c ("nir: add varying component packing helpers")
---
src/compiler/nir/nir_linking_helpers.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/src/compiler/nir/nir_linking_helpers.c
b/src/compiler/n
On Sun, Nov 11, 2018 at 8:46 PM Karol Herbst wrote:
> an)
> On Mon, Nov 12, 2018 at 12:37 AM Jason Ekstrand
> wrote:
> >
> > On November 11, 2018 16:36:16 Karol Herbst wrote:
> >
> > > On Sun, Nov 11, 2018 at 10:48 PM Jason Ekstrand
> wrote:
> > >>
> > >> On Sun, Nov 11, 2018 at 3:35 PM Plame
an)
On Mon, Nov 12, 2018 at 12:37 AM Jason Ekstrand wrote:
>
> On November 11, 2018 16:36:16 Karol Herbst wrote:
>
> > On Sun, Nov 11, 2018 at 10:48 PM Jason Ekstrand
> > wrote:
> >>
> >> On Sun, Nov 11, 2018 at 3:35 PM Plamena Manolova
> >> wrote:
> >>>
> >>>
> >>> Lowering shader variables
Fixes: 1c9c42d16b4c ("nir: add varying component packing helpers")
---
src/compiler/nir/nir_linking_helpers.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/src/compiler/nir/nir_linking_helpers.c
b/src/compiler/nir/nir_linking_helpers.c
index b07bb40894e..125a8d55b3e
---
src/compiler/nir_types.cpp | 5 +
src/compiler/nir_types.h | 1 +
2 files changed, 6 insertions(+)
diff --git a/src/compiler/nir_types.cpp b/src/compiler/nir_types.cpp
index d24f0941519..3cd61f66056 100644
--- a/src/compiler/nir_types.cpp
+++ b/src/compiler/nir_types.cpp
@@ -301,6 +301,
On November 11, 2018 16:36:16 Karol Herbst wrote:
On Sun, Nov 11, 2018 at 10:48 PM Jason Ekstrand wrote:
On Sun, Nov 11, 2018 at 3:35 PM Plamena Manolova
wrote:
Lowering shader variables which depend on the local work group
size being available in nir_lower_system_values is only possibl
On Sun, Nov 11, 2018 at 10:48 PM Jason Ekstrand wrote:
>
> On Sun, Nov 11, 2018 at 3:35 PM Plamena Manolova
> wrote:
>>
>> Lowering shader variables which depend on the local work group
>> size being available in nir_lower_system_values is only possible
>> if the local work group size isn't vari
On Sun, Nov 11, 2018 at 3:35 PM Plamena Manolova <
plamena.n.manol...@gmail.com> wrote:
> Lowering shader variables which depend on the local work group
> size being available in nir_lower_system_values is only possible
> if the local work group size isn't variable, otherwise this should
> be hand
On 10/11/2018 17:09, Axel Davy wrote:
Axel Davy (2):
st/nine: Allow 'triple buffering' with thread_submit
st/nine: Remove thread_submit warning
Nice! Series is:
Tested-by: Andre Heider
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h
Lowering shader variables which depend on the local work group
size being available in nir_lower_system_values is only possible
if the local work group size isn't variable, otherwise this should
be handled by the native driver (if it supports
ARB_compute_variable_group_size).
Signed-off-by: Plamen
Lowering the global invocation id and the local work group
size in nir_lower_system_values is only possible if the
local work group size isn't variable, otherwise this should
be handled by the native driver (if it supports
ARB_compute_variable_group_size).
Signed-off-by: Plamena Manolova
---
src
On nv50, certain operations must happen on regs below 64, due to
encoding requirements. First of all, we add infrastructure to enforce
this. Secondly we change the spill order to first spill RIG nodes that
are unconstrained, followed by ones that are.
This makes the gamecube logo shadertoy compile
Alright, thank you :)
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Some mobile GPUs lack fixed-function hardware for blending, instead
emulating blending via internal shaders. In particular for us, vc4 lacks
most of the fragment pipeline, implementing blending in the epilogue of
the fragment shader. Newer Malis supported by Panfrost have limitations
in their fixed
On Friday, 2018-11-09 13:28:49 -0800, Dylan Baker wrote:
> meson does this for you with it's warn levels, so we don't need to set
> it ourselves.
s/it's/its/
And yeah you're right, I just checked and -Wall (or equivalent) is
always passed to compilers that support it.
Reviewed-by: Eric Engestrom
Thank you. I noticed this as well.
Reviewed-by: Matt Turner
I'll commit it tomorrow if there are no additional comments.
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regs is only set and used on x86; on other platforms (like ARM), this
code causes a trivial warning, solved by moving the regs declaration to
the architecture-dependent usage.
Signed-off-by: Alyssa Rosenzweig
---
src/util/u_cpu_detect.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
On Thursday, 2018-10-11 16:36:15 +0100, Eric Engestrom wrote:
> Those empty variables in the !wayland case are useless and running that
> meson.build with them breaks the build:
>
> [287/850] Generating wayland-drm-client-protocol.h with a custom command.
> FAILED: src/egl/wayland/wayland-drm/
Instead of the size restriction existing in two places, and potentially
being applied twice, we move this together. Ops with 16-bit register
addresses can only take a short reg, and ops with immediates can only
take a short reg.
Of course we leave the immediate 0 in place since we know that it wil
Sagar reminded me via his MSR that this patch series never landed.
Everything got reviewed by Ian except this patch which he only acked.
Would someone mind doing a more proper review? This seemed like the wrong
patch to push with just an ack.
--Jason
On Thu, Oct 11, 2018 at 4:33 PM Jason Ekstran
On November 11, 2018 09:11:26 Gert Wollny wrote:
Am Sonntag, den 11.11.2018, 09:07 -0600 schrieb Jason Ekstrand:
On November 11, 2018 07:44:54 Gert Wollny
wrote:
From: Gert Wollny
Since some hardware supports source mods only for float operations
make
it possible to skip this lowering
Am Sonntag, den 11.11.2018, 09:07 -0600 schrieb Jason Ekstrand:
> On November 11, 2018 07:44:54 Gert Wollny
> wrote:
>
> > From: Gert Wollny
> >
> >
> > Since some hardware supports source mods only for float operations
> > make
> > it possible to skip this lowering for integer operations.
>
On November 11, 2018 07:44:54 Gert Wollny wrote:
From: Gert Wollny
Since some hardware supports source mods only for float operations make
it possible to skip this lowering for integer operations.
Out of curiosity, what hardware would that be?
Signed-off-by: Gert Wollny
---
I'm a bit un
From: Gert Wollny
Since some hardware supports source mods only for float operations make
it possible to skip this lowering for integer operations.
Signed-off-by: Gert Wollny
---
I'm a bit unsure about what the best name for the parameter is, i.e. passing in
true when one doesn't want all t
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