On Tue, Oct 9, 2018 at 12:43 AM Jason Ekstrand wrote:
>
> On Mon, Oct 8, 2018 at 4:06 PM Bas Nieuwenhuizen
> wrote:
>>
>> On Mon, Oct 8, 2018 at 2:39 PM Samuel Pitoiset
>> wrote:
>> >
>> > R32G32B32 are weird formats and we are only going to support
>> > some basic operations for now.
>> >
>> >
On Mon, Oct 8, 2018 at 4:06 PM Bas Nieuwenhuizen
wrote:
> On Mon, Oct 8, 2018 at 2:39 PM Samuel Pitoiset
> wrote:
> >
> > R32G32B32 are weird formats and we are only going to support
> > some basic operations for now.
> >
> > Signed-off-by: Samuel Pitoiset
> > ---
> > src/amd/vulkan/radv_forma
https://bugs.freedesktop.org/show_bug.cgi?id=108275
Bas Nieuwenhuizen changed:
What|Removed |Added
Status|NEEDINFO|NEW
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I didn't see any issue when I was testing Tahiti and Hawaii on amdgpu.
radeon is too unstable for a 16-thread piglit, so I never use it.
You can try to set reg_saved = 0 in si_begin_new_gfx_cs. That should
prevent issues with CLEAR_STATE.
Marek
On Mon, Oct 8, 2018 at 12:30 PM Michel Dänzer wrote
https://bugs.freedesktop.org/show_bug.cgi?id=108277
Bug ID: 108277
Summary: Implement tiled copies for AMD -> Intel PRIME
Product: Mesa
Version: git
Hardware: Other
OS: All
Status: NEW
Severity: enhancemen
https://bugs.freedesktop.org/show_bug.cgi?id=99553
Jan Vesely changed:
What|Removed |Added
Blocks|108272 |
Depends on|
On Mon, Oct 8, 2018 at 3:46 PM Ian Romanick wrote:
> On 10/05/2018 09:10 PM, Jason Ekstrand wrote:
> > ---
> > src/compiler/nir/nir_constant_expressions.py | 1 +
> > src/compiler/nir/nir_opcodes.py | 43 ++--
> > 2 files changed, 40 insertions(+), 4 deletions(-)
>
https://bugs.freedesktop.org/show_bug.cgi?id=99553
Jan Vesely changed:
What|Removed |Added
Blocks||108272
Referenced Bugs:
https://bugs.free
https://bugs.freedesktop.org/show_bug.cgi?id=108275
--- Comment #3 from mais...@archlinux.us ---
Seems to work just fine on Intel (Anvil).
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On Mon, Oct 8, 2018 at 2:39 PM Samuel Pitoiset
wrote:
>
> R32G32B32 are weird formats and we are only going to support
> some basic operations for now.
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_formats.c | 14 ++
> 1 file changed, 14 insertions(+)
>
> diff --git
I really like this one; its very readable =)
Reviewed-by: Thomas Helland
Den tor. 30. aug. 2018 kl. 07:37 skrev Ian Romanick :
>
> From: Ian Romanick
>
> Signed-off-by: Ian Romanick
> ---
> src/compiler/nir/meson.build| 12 +
> src/compiler/nir/nir.h
On Tue, Oct 02, 2018 at 07:16:01PM +0300, asimiklit.w...@gmail.com wrote:
> From: Andrii Simiklit
>
> I guess that when we calculating the width0, height0, depth0
> to use for function 'intel_miptree_create' we need to consider
> the 'base level' like it is done in the 'intel_miptree_create_for_t
On 10/05/2018 09:10 PM, Jason Ekstrand wrote:
> ---
> src/compiler/nir/nir_constant_expressions.py | 1 +
> src/compiler/nir/nir_opcodes.py | 43 ++--
> 2 files changed, 40 insertions(+), 4 deletions(-)
>
> diff --git a/src/compiler/nir/nir_constant_expressions.py
>
Den tor. 30. aug. 2018 kl. 07:37 skrev Ian Romanick :
>
> From: Ian Romanick
>
> On some GPUs, especially older Intel GPUs, some math instructions are
> very expensive. On those architectures, don't reduce flow control to a
> csel if one of the branches contains one of these expensive math
> inst
Quoting Jason Ekstrand (2018-10-05 21:10:14)
> While I generally trust rediculousfish to have done his homework, we've
> made some adjustments to suite the needs of mesa and it'd be good to
^
suit
> test those. Also, there's no better plac
On Fri, Sep 14, 2018 at 10:46 PM Caio Marcelo de Oliveira Filho <
caio.olive...@intel.com> wrote:
> Note at the moment the pass called is nir_opt_copy_prop_vars, because
> dead write elimination is implemented there.
>
> Also added tests that involve identifying dead writes in multiple
> blocks (e
https://bugs.freedesktop.org/show_bug.cgi?id=108275
Ian Romanick changed:
What|Removed |Added
Status|NEW |NEEDINFO
--- Comment #2 from Ian Romanic
Den tir. 11. sep. 2018 kl. 01:30 skrev Ian Romanick :
>
> This series implements a code-generation optimization for sign(x)*y. In
> GLSL, sign(x) is defined as:
>
> Returns 1.0 if x > 0, 0.0 if x = 0, or -1.0 if x < 0.
>
> It is silent on the NaN behavior, so I have taken it as "undefined." I
Den tir. 11. sep. 2018 kl. 01:30 skrev Ian Romanick :
>
> From: Ian Romanick
>
Reviewed-by: Thomas Helland
> Signed-off-by: Ian Romanick
> ---
> src/compiler/nir/nir.h | 23 +++
> 1 file changed, 23 insertions(+)
>
> diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/ni
Den tir. 11. sep. 2018 kl. 01:30 skrev Ian Romanick :
>
> From: Ian Romanick
>
> No shader-db or CI changes on any Intel platform.
>
I'm no expert on the intel backend, but this seems trivial enough.
Reviewed-by: Thomas Helland
> Signed-off-by: Ian Romanick
> ---
> src/intel/compiler/brw_fs_n
Den tir. 11. sep. 2018 kl. 01:30 skrev Ian Romanick :
>
> From: Ian Romanick
>
> These allows us to not support fsign.sat in the Intel compiler backend,
> and that will simplify some later changes.
>
> No shader-db changes on any Intel platform.
>
I was a bit skeptical to how this would impact ot
Den tir. 11. sep. 2018 kl. 01:30 skrev Ian Romanick :
>
> From: Ian Romanick
>
Reviewed-by: Thomas Helland
> shader-db results:
>
> All Gen7+ platforms had similar results. (Skylake shown)
> total instructions in shared programs: 15106023 -> 15105981 (<.01%)
> instructions in affected programs:
https://bugs.freedesktop.org/show_bug.cgi?id=108275
--- Comment #1 from mais...@archlinux.us ---
To replay the pipeline (for debugging):
./cli/fossilize-replay fossilize.json --filter-compute 3
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https://bugs.freedesktop.org/show_bug.cgi?id=108275
Bug ID: 108275
Summary: Breaking out of loop creates broken code on RADV
Product: Mesa
Version: 18.2
Hardware: Other
OS: All
Status: NEW
Severity: normal
This patch is
Reviewed-by: Ian Romanick
On 10/05/2018 09:10 PM, Jason Ekstrand wrote:
> ---
> src/util/Makefile.am | 1 +
> src/util/Makefile.sources | 1 +
> src/util/bigmath.h| 112 ++
> src/util/meson.build | 1 +
> 4 files changed,
On Wed, Sep 26, 2018 at 3:30 AM Gert Wollny wrote:
>
> Am Dienstag, den 25.09.2018, 10:20 -0400 schrieb Ilia Mirkin:
> > I haven't double-checked yet, but doesn't this result in a reduction
> > of functionality for pre-independent-blend GPUs (like the early
> > NVIDIA
> > Tesla series)? Configurin
https://bugs.freedesktop.org/show_bug.cgi?id=93089
--- Comment #22 from Ian Romanick ---
(In reply to freedesktop from comment #21)
> This also popped up on archlinux32 when trying to package mesa for i486:
>
> /usr/bin/ld: src/intel/vulkan/libanv_common.a(anv_allocator.c.o): in
> function `anv_
https://bugs.freedesktop.org/show_bug.cgi?id=108118
--- Comment #4 from duoora...@gmail.com ---
I have been unable to replicate this problem with vulkan-radeon from the new
Mesa 18.2.2, I think it might have been fixed in the 18.2.1 -> 18.2.2 update.
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I have a recollection of wanting to do something similar in the past.
However I also have a record of the test passing before (circa 2015).
OTOH we do things differently on GM107+, so ... who knows. My guess is
that it was the splitting out of is_user_buffer changed how the code
behaved somehow - p
On 2018-10-03 5:53 p.m., Sonny Jiang wrote:
> Signed-off-by: Sonny Jiang
Unfortunately, this change causes GPU hangs with the radeon kernel
driver on Kaveri, see the attached dmesg excerpt (this might have been
with later patches from the series still applied, but I've had to revert
those in addi
Fixes crash in piglit's gl-3.1-vao-broken-attrib.
Signed-off-by: Rhys Perry
---
src/gallium/drivers/nouveau/nvc0/nvc0_state.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_state.c
b/src/gallium/drivers/nouveau/nvc0/nvc0_state.c
It's valid to have a vertex buffer with a NULL resource.
Signed-off-by: Rhys Perry
---
src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c | 4
1 file changed, 4 insertions(+)
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c
b/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c
index 66de6d9e2f..
On Sat, Oct 6, 2018 at 1:52 PM Marek Olšák wrote:
> With my comments addressed, patches 2 - 6 are:
>
> Reviewed-by: Marek Olšák
>
Thanks! Unfortunately, the tests require patch 1 so it'd be nice if that
got review by someone. I'd also be happy to pull in someone else's more
vetted code for la
On Mon, Oct 8, 2018 at 10:22 AM Alejandro Piñeiro
wrote:
> I was not able to finish trying to get ARB_gl_spirv using this pass. The
> major difference is that on ARB_gl_spirv (and afaiu on GLSL too) we are
> merging the info of all the available xfb varyings from all the stages,
> while this pass
Reviewed-by: Dylan Baker
You could add radv_flags to future safety, but it's not used currently so this
should fix things.
Quoting Eric Engestrom (2018-10-08 08:25:58)
> Fixes: 6f3aee40f90d725653b6 "radv: using tls to store llvm related info
> and speed up compiles (
Fixes: 6f3aee40f90d725653b6 "radv: using tls to store llvm related info
and speed up compiles (v10)"
Cc: Dave Airlie
Signed-off-by: Eric Engestrom
---
src/amd/vulkan/meson.build | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/amd/vulkan/meson.build b/src/amd/
I was not able to finish trying to get ARB_gl_spirv using this pass. The
major difference is that on ARB_gl_spirv (and afaiu on GLSL too) we are
merging the info of all the available xfb varyings from all the stages,
while this pass gathers info from a individual nir shader (so one
individual stage
Hi Veluri,
On 07.10.2018 21:31, Veluri Mithun wrote:
> All these days I worked on packaging since I didn't find much time last
> month in my new academic schedule, I finished it if you wish you may
> download it
> here(https://flathub.org/apps/details/br.com.jeanhertel.adriconf).
> Currently,
Hi,
You're right, it would be easy to do. I'll include it in my next submission.
On 10/08/2018 12:13 AM, Ilia Mirkin wrote:
See my feedback from your earlier submission for how to make this work
on more than triangles. Seems easy enough to just do it.
https://patchwork.freedesktop.org/patch/25
On 10/8/18 9:23 AM, Kenneth Graunke wrote:
On Monday, September 24, 2018 4:19:36 AM PDT Tapani Pälli wrote:
Hi;
Here's another try to inline sse41 code and get rid of gtt maps
in intel_miptree_map (revert 58fb613a519). To be able to safely
utilize sse41 we separate sse41 functionality as a lib
https://bugs.freedesktop.org/show_bug.cgi?id=108113
--- Comment #1 from Samuel Pitoiset ---
https://patchwork.freedesktop.org/series/50686/
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R32G32B32 are weird formats and we are only going to support
some basic operations for now.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_formats.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/src/amd/vulkan/radv_formats.c b/src/amd/vulkan/radv_formats.c
index ad0
This fixes crashes for some CTS:
dEQP-VK.api.copy_and_blit.core.blit_image.all_formats.color.*.linear_*_*
dEQP-VK.api.copy_and_blit.core.blit_image.all_formats.color.*.*_linear_*
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108113
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_
https://bugs.freedesktop.org/show_bug.cgi?id=93089
--- Comment #21 from freedesk...@eckner.net ---
This also popped up on archlinux32 when trying to package mesa for i486:
/usr/bin/ld: src/intel/vulkan/libanv_common.a(anv_allocator.c.o): in function
`anv_block_pool_alloc_new':
anv_allocator.c:(.t
---
src/compiler/nir/meson.build | 1 +
src/compiler/nir/nir.h | 2 +
src/compiler/nir/nir_divergence_analysis.c | 333 +
3 files changed, 336 insertions(+)
create mode 100644 src/compiler/nir/nir_divergence_analysis.c
diff --git a/src/co
This is an RFC for a Divergence Analysis for NIR.
The algorithm implements "The Simple Divergence Analysis" from
Diogo Sampaio, Rafael De Souza, Sylvain Collange, Fernando Magno Quintão
Pereira.
Divergence Analysis.
The proposed pass computes for each ssa definition if it is uniform.
That is, t
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