[Mesa-dev] [PATCH] radv: Do not use multiple draws for multisample copies.

Use sample rate shading instead, should give better locality. --- src/amd/vulkan/radv_meta_blit2d.c | 62 +++ 1 file changed, 5 insertions(+), 57 deletions(-) diff --git a/src/amd/vulkan/radv_meta_blit2d.c b/src/amd/vulkan/radv_meta_blit2d.c index d2975532d4b..45eb4b3

Re: [Mesa-dev] [PATCH 1/2] anv: s/batch/value_bo/ on anv_device_init_hiz_clear_batch

Rb On September 26, 2018 01:27:05 Jordan Justen wrote: Signed-off-by: Jordan Justen Cc: Jason Ekstrand --- src/intel/vulkan/anv_device.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c index 4219a073d2d..265

Re: [Mesa-dev] [RESEND PATCH 0/5] i965: More cmod propagation

Hi Ian, Do you have these in a branch somewhere? Do you also have a branch somewhere of the PRE for compares? I'll try to have a look at these, and the sign(x)*y series this evening. I will probably only be able to review the simplest patches, but something is probably better than nothing, I guess

Re: [Mesa-dev] [PATCH] mesa/st: In the precense of integer buffers enable per buffer blending

On Tue, Sep 25, 2018 at 6:54 PM, Kenneth Graunke wrote: > On Wednesday, September 26, 2018 12:48:13 AM CEST Kenneth Graunke wrote: >> On Tuesday, September 25, 2018 4:20:04 PM CEST Ilia Mirkin wrote: >> > I haven't double-checked yet, but doesn't this result in a reduction >> > of functionality fo

[Mesa-dev] [PATCH 2/2] anv: If softpin is supported, use it with the hiz clear value bo

Signed-off-by: Jordan Justen Cc: Nanley Chery Cc: Jason Ekstrand --- src/intel/vulkan/anv_device.c | 9 + 1 file changed, 9 insertions(+) diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c index 265fc4a3347..4e64f595650 100644 --- a/src/intel/vulkan/anv_device.c

[Mesa-dev] [PATCH 1/2] anv: s/batch/value_bo/ on anv_device_init_hiz_clear_batch

Signed-off-by: Jordan Justen Cc: Jason Ekstrand --- src/intel/vulkan/anv_device.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c index 4219a073d2d..265fc4a3347 100644 --- a/src/intel/vulkan/anv_device.c +++ b/

Re: [Mesa-dev] [PATCH] anv: If softpin is supported, use it with hiz clear batch bo

On 2018-09-25 16:02:28, Nanley Chery wrote: > On Tue, Sep 25, 2018 at 03:22:11PM -0700, Jordan Justen wrote: > > Signed-off-by: Jordan Justen > > Cc: Nanley Chery > > --- > > src/intel/vulkan/anv_device.c | 9 + > > 1 file changed, 9 insertions(+) > > > > diff --git a/src/intel/vulkan/a

Re: [Mesa-dev] [PATCH] anv: If softpin is supported, use it with hiz clear batch bo

On Tue, Sep 25, 2018 at 03:22:11PM -0700, Jordan Justen wrote: > Signed-off-by: Jordan Justen > Cc: Nanley Chery > --- > src/intel/vulkan/anv_device.c | 9 + > 1 file changed, 9 insertions(+) > > diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c > index 0ea8be05

Re: [Mesa-dev] [PATCH] mesa/st: In the precense of integer buffers enable per buffer blending

On Wednesday, September 26, 2018 12:48:13 AM CEST Kenneth Graunke wrote: > On Tuesday, September 25, 2018 4:20:04 PM CEST Ilia Mirkin wrote: > > I haven't double-checked yet, but doesn't this result in a reduction > > of functionality for pre-independent-blend GPUs (like the early NVIDIA > > Tesla

Re: [Mesa-dev] [PATCH] mesa/st: In the precense of integer buffers enable per buffer blending

On Tuesday, September 25, 2018 4:20:04 PM CEST Ilia Mirkin wrote: > I haven't double-checked yet, but doesn't this result in a reduction > of functionality for pre-independent-blend GPUs (like the early NVIDIA > Tesla series)? Configuring blending for an integer RT does nothing on > NVIDIA hardware

Re: [Mesa-dev] [PATCH] anv: If softpin is supported, use it with hiz clear batch bo

The BO this function allocates is not a batch. Please change the commit message. Bonus points if you send another patch to rename the function. On September 26, 2018 00:23:42 Jordan Justen wrote: Signed-off-by: Jordan Justen Cc: Nanley Chery --- src/intel/vulkan/anv_device.c | 9 + 1

[Mesa-dev] [PATCH] anv: If softpin is supported, use it with hiz clear batch bo

Signed-off-by: Jordan Justen Cc: Nanley Chery --- src/intel/vulkan/anv_device.c | 9 + 1 file changed, 9 insertions(+) diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c index 0ea8be052fa..4e446c3280a 100644 --- a/src/intel/vulkan/anv_device.c +++ b/src/intel/vul

[Mesa-dev] [PATCH] vl: reorder H264 profiles

From: Boyuan Zhang Fix the wrong h264 profiles order. Previously, the constrained baseline was added in between baseline and main profiles, which breaked the logic in radeon/vce when converting from pipe_video_profile to profile_idc Signed-off-by: Boyuan Zhang --- src/gallium/include/pipe/p_vi

Re: [Mesa-dev] [PATCH v2 1/4] util: Get program name based on path when possible

On 24 September 2018 at 19:18, Nicholas Kazlauskas wrote: > Some programs start with the path and command line arguments in > argv[0] (program_invocation_name). Chromium is an example of > an application using mesa that does this. > > This tries to query the real path for the symbolic link /proc/s

[Mesa-dev] [Bug 108065] Launching SteamVR results in nir_deref_instr_remove_if_unused assert

https://bugs.freedesktop.org/show_bug.cgi?id=108065 Bug ID: 108065 Summary: Launching SteamVR results in nir_deref_instr_remove_if_unused assert Product: Mesa Version: git Hardware: Other OS: All

Re: [Mesa-dev] [PATCH] intel/isl: Add a _B suffix to some struct fields

On Wed, Sep 05, 2018 at 02:10:28PM -0500, Jason Ekstrand wrote: > I was about to make the claim to someone that every field in isl_surf > is either an enum or has explicit units. Then I looked at isl_surf and > discovered this claim was wrong. We should fix that. > > Cc: Chad Versace > --- > s

Re: [Mesa-dev] [PATCH 2/2] .travis: Drop note about Clover builds being slow

On Tue, 2018-09-25 at 18:11 +0100, Emil Velikov wrote: > On 12 September 2018 at 23:20, Jan Vesely wrote: > > SWR takes 17+ minutes to build. Clover builds take ~6-7 minutes. > > > > Clover takes the same time as all the other state-trackers combined. > Ideally we'll tweak change to something mo

Re: [Mesa-dev] [PATCH] radv: do not use the availability bit for timestamp queries

On Wed, 26 Sep 2018 at 04:27, Samuel Pitoiset wrote: > > It's unnecessary because we can just check if the timestamp > is to different to the default value when a pool is created > or resetted. Instead of waiting for the availability bit to > be 1, we have to emit a not equal WAIT_REG_MEM for chec

[Mesa-dev] [Bug 108062] Mesa 18.2.0 and Mesa 18.2.1 RADV Freeze

https://bugs.freedesktop.org/show_bug.cgi?id=108062 Bug ID: 108062 Summary: Mesa 18.2.0 and Mesa 18.2.1 RADV Freeze Product: Mesa Version: unspecified Hardware: Other OS: All Status: NEW Severity: normal

[Mesa-dev] [PATCH] radv: do not use the availability bit for timestamp queries

It's unnecessary because we can just check if the timestamp is to different to the default value when a pool is created or resetted. Instead of waiting for the availability bit to be 1, we have to emit a not equal WAIT_REG_MEM for checking if the timestamp is ready. Signed-off-by: Samuel Pitoiset

Re: [Mesa-dev] [PATCH 2/2] .travis: Drop note about Clover builds being slow

On 12 September 2018 at 23:20, Jan Vesely wrote: > SWR takes 17+ minutes to build. Clover builds take ~6-7 minutes. > Clover takes the same time as all the other state-trackers combined. Ideally we'll tweak change to something more accurate as ^^, but either way For the series, Reviewed-by: Emil

Re: [Mesa-dev] [PATCH 2/2] .travis: Drop note about Clover builds being slow

On Wed, 2018-09-19 at 11:43 -0400, Jan Vesely wrote: > On Wed, 2018-09-12 at 18:20 -0400, Jan Vesely wrote: > > SWR takes 17+ minutes to build. Clover builds take ~6-7 minutes. > > > > Signed-off-by: Jan Vesely > > --- > > .travis.yml | 4 > > 1 file changed, 4 deletions(-) > > > > diff --

Re: [Mesa-dev] [PATCH v2 1/4] util: Get program name based on path when possible

On 26/9/18 12:02 am, Kazlauskas, Nicholas wrote: On 09/24/2018 08:00 PM, Timothy Arceri wrote: On 25/9/18 4:18 am, Nicholas Kazlauskas wrote: Some programs start with the path and command line arguments in argv[0] (program_invocation_name). Chromium is an example of an application using mesa

Re: [Mesa-dev] [PATCH 19/26] nir/linker: use only the array element type for array of ssbo/ubo

On 20/09/18 00:22, Timothy Arceri wrote: > > > On 19/9/18 11:10 pm, Alejandro Piñeiro wrote: >> >> On 19/09/18 14:09, Timothy Arceri wrote: >>> On 19/9/18 7:59 pm, Alejandro Piñeiro wrote: On 19/09/18 07:20, Timothy Arceri wrote: > On 16/9/18 2:18 am, Alejandro Piñeiro wrote: >> For

Re: [Mesa-dev] [PATCH] mesa/st: In the precense of integer buffers enable per buffer blending

I haven't double-checked yet, but doesn't this result in a reduction of functionality for pre-independent-blend GPUs (like the early NVIDIA Tesla series)? Configuring blending for an integer RT does nothing on NVIDIA hardware, so it all works out there just fine... Perhaps both patches should just

Re: [Mesa-dev] [PATCH] Revert "mesa: remove unnecessary 'sort by year' for the GL extensions"

Looks great to me. Reviewed-by: Roland Scheidegger Am 24.09.2018 um 17:19 schrieb Emil Velikov: > This reverts commit 3d81e11b49366b5636b8524ba0f8c7076e3fdf34. > > As reported by Federico, some games require the 'sort by year' since > they truncate the extensions which do not fit the fixed size

[Mesa-dev] [PATCH v2] glsl: do not attempt assignment if operand type not parsed correctly

v2: check types of both operands (Ian) Cc: mesa-sta...@lists.freedesktop.org Signed-off-by: Tapani Pälli Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108012 --- src/compiler/glsl/ast_to_hir.cpp | 6 ++ 1 file changed, 6 insertions(+) diff --git a/src/compiler/glsl/ast_to_hir.cpp b

Re: [Mesa-dev] [PATCH v2 1/4] util: Get program name based on path when possible

On 09/24/2018 08:00 PM, Timothy Arceri wrote: On 25/9/18 4:18 am, Nicholas Kazlauskas wrote: Some programs start with the path and command line arguments in argv[0] (program_invocation_name). Chromium is an example of an application using mesa that does this. This tries to query the real path f

Re: [Mesa-dev] [PATCH 1/5] util: import public domain code for integer division by a constant

On 09/25/2018 02:24 AM, Jason Ekstrand wrote: > On Mon, Sep 24, 2018 at 6:41 PM Marek Olšák > wrote: > > Did you copy the code from the same author? > > > No, I read a paper and implemented it myself. >   > > Does your version also have an interface for dividin

Re: [Mesa-dev] [PATCH 1/5] util: import public domain code for integer division by a constant

On Mon, Sep 24, 2018 at 7:15 PM Marek Olšák wrote: > This patch also handles all types, just differently. If you change the > typedefs in the header, you'll get a different type and the code is > exactly the same for all types, but that's not important (to me > anyway). > > It also supports signe

Re: [Mesa-dev] [PATCH 1/5] util: import public domain code for integer division by a constant

On Mon, Sep 24, 2018 at 6:41 PM Marek Olšák wrote: > Did you copy the code from the same author? > No, I read a paper and implemented it myself. > Does your version also have an interface for dividing by a uniform > instead of a compile time constant? > I'm not sure what you mean by that. No

Re: [Mesa-dev] [Mesa-stable] [PATCH] radeonsi: add a workaround for bitfield_extract when count is 0

On Tue, Sep 25, 2018 at 8:50 AM Samuel Pitoiset wrote: > On 9/25/18 6:46 AM, Timothy Arceri wrote: > > On 25/9/18 10:35 am, Marek Olšák wrote: > >> Do you know what's broken in LLVM? Or is it a problem with the ISA? > > > > I haven't actually dug any further. Adding Samuel to see if he remembers >

Re: [Mesa-dev] [Mesa-stable] [PATCH] radeonsi: add a workaround for bitfield_extract when count is 0

On Sat, 2018-09-22 at 12:38 +1000, Timothy Arceri wrote: > This ports the fix from 3d41757788ac. Both LLVM 7 & 8 continue > to have this problem. > > It fixes rendering issues in some menu and loading screens of > Civ VI which can be seen in the trace from bug 104602. > Thank you. Added this pat

[Mesa-dev] [PATCH 19/20] intel/aub_viewer: add page editor from pml4 view

Signed-off-by: Lionel Landwerlin --- src/intel/tools/aubinator_viewer.cpp | 26 ++ 1 file changed, 18 insertions(+), 8 deletions(-) diff --git a/src/intel/tools/aubinator_viewer.cpp b/src/intel/tools/aubinator_viewer.cpp index 0f4528caf0d..b3cc1909bfa 100644 --- a/src/in

[Mesa-dev] [PATCH 10/20] intel/error2aub: build a list of BOs before writing them

The error state contains several kind of BOs, including the context image which we will want to write in a later commit. Because it can come later in the error state then the user buffers and because we need to write it first in the aub file, we have to first build a list of BOs and then write them

[Mesa-dev] [PATCH 20/20] intel/aub_viewer: make pphwsp/context image visible

Signed-off-by: Lionel Landwerlin --- src/intel/tools/aubinator_viewer.cpp | 64 1 file changed, 46 insertions(+), 18 deletions(-) diff --git a/src/intel/tools/aubinator_viewer.cpp b/src/intel/tools/aubinator_viewer.cpp index b3cc1909bfa..21c76bb2f11 100644 --- a/src

[Mesa-dev] [PATCH 17/20] intel/error2aub: add a verbose option

Signed-off-by: Lionel Landwerlin --- src/intel/tools/error2aub.c | 18 -- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/src/intel/tools/error2aub.c b/src/intel/tools/error2aub.c index 354e4e00924..2ad47010bdf 100644 --- a/src/intel/tools/error2aub.c +++ b/src/inte

[Mesa-dev] [PATCH 09/20] intel/aub_write: factorize context image/pphwsp/ring creation

We allocate GGTT entries and physical addresses are we create engines rather than having a fixed layout. Context images now receive a parameter argument which is used to setup pml4 & ring buffer addresses. Signed-off-by: Lionel Landwerlin --- src/intel/tools/aub_write.c | 240 ++

[Mesa-dev] [PATCH 16/20] intel/error2aub: write GGTT buffers into the aub file

Signed-off-by: Lionel Landwerlin --- src/intel/tools/aub_write.c | 69 +++ src/intel/tools/aub_write.h | 5 +++ src/intel/tools/error2aub.c | 82 +++-- 3 files changed, 144 insertions(+), 12 deletions(-) diff --git a/src/intel/tools/au

[Mesa-dev] [PATCH 12/20] intel/error2aub: strenghten batchbuffer identifier marker

Found out that some base64 data matched the '---' identifier. We can avoid this by adding the surrounding spaces. Signed-off-by: Lionel Landwerlin --- src/intel/tools/error2aub.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/intel/tools/error2aub.c b/src/intel/tools

[Mesa-dev] [PATCH 11/20] intel/error2aub: identify buffers by engine

Signed-off-by: Lionel Landwerlin --- src/intel/tools/error2aub.c | 84 ++--- 1 file changed, 60 insertions(+), 24 deletions(-) diff --git a/src/intel/tools/error2aub.c b/src/intel/tools/error2aub.c index ff8622cde6d..ed11b35ffb1 100644 --- a/src/intel/tools/error2

[Mesa-dev] [PATCH 13/20] intel/error2aub: parse other buffer types

We don't write them in the aub file yet. Signed-off-by: Lionel Landwerlin --- src/intel/tools/error2aub.c | 35 ++- 1 file changed, 22 insertions(+), 13 deletions(-) diff --git a/src/intel/tools/error2aub.c b/src/intel/tools/error2aub.c index ef8cd9dacf9..99c84bd

[Mesa-dev] [PATCH 14/20] intel/error2aub: annotate buffer with their address space

Signed-off-by: Lionel Landwerlin --- src/intel/tools/error2aub.c | 37 ++--- 1 file changed, 26 insertions(+), 11 deletions(-) diff --git a/src/intel/tools/error2aub.c b/src/intel/tools/error2aub.c index 99c84bd15ef..0400da53470 100644 --- a/src/intel/tools/error2

[Mesa-dev] [PATCH 05/20] intel/aub_write: switch to use i915_drm engine classes

Error states can contain vcs0/vcs1. The current ring_flag doesn't deal with this very well, leading to confusion between buffers of different types. Signed-off-by: Lionel Landwerlin --- src/intel/tools/aub_write.c | 73 +++- src/intel/tools/aub_write.h | 4

[Mesa-dev] [PATCH 15/20] intel/error2aub: store engine last ring buffer head/tail pointers

Signed-off-by: Lionel Landwerlin --- src/intel/tools/error2aub.c | 22 ++ 1 file changed, 22 insertions(+) diff --git a/src/intel/tools/error2aub.c b/src/intel/tools/error2aub.c index 0400da53470..72531a97b18 100644 --- a/src/intel/tools/error2aub.c +++ b/src/intel/tools/erro

[Mesa-dev] [PATCH 18/20] intel/error2aub: deal with GuC log buffer

When Guc is enabled, the error state will contain a "global" buffer for the GuC log buffer. Signed-off-by: Lionel Landwerlin --- src/intel/tools/error2aub.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/intel/tools/error2aub.c b/src/intel/tools/error2aub.c index 2ad47010bdf..37c082d417

[Mesa-dev] [PATCH 03/20] intel/aub_write: write header in init

Signed-off-by: Lionel Landwerlin --- src/intel/tools/aub_write.c | 152 --- src/intel/tools/aub_write.h | 3 +- src/intel/tools/error2aub.c | 4 +- src/intel/tools/intel_dump_gpu.c | 7 +- 4 files changed, 84 insertions(+), 82 deletions(-) diff --

[Mesa-dev] [PATCH 07/20] intel/aub_write: store the physical page allocator in struct

We want to use this allocator in the next commit for GGTT pages. Signed-off-by: Lionel Landwerlin --- src/intel/tools/aub_write.c | 47 + src/intel/tools/aub_write.h | 1 + 2 files changed, 33 insertions(+), 15 deletions(-) diff --git a/src/intel/tools/aub_w

[Mesa-dev] [PATCH 08/20] intel/aub_write: turn context images arrays into functions

We'll make them more parameterized in a later commit. As this is just a transitional commit, we allow ourself to leak the context images allocated in get_context_init(). We'll fix this in the next commit. Signed-off-by: Lionel Landwerlin --- src/intel/tools/aub_write.c | 62 src/i

[Mesa-dev] [PATCH 04/20] intel/aub_write: break execlist write in 2

We want to reuse the execlist submission, but won't need the ring buffer update. Signed-off-by: Lionel Landwerlin --- src/intel/tools/aub_write.c | 100 ++-- 1 file changed, 62 insertions(+), 38 deletions(-) diff --git a/src/intel/tools/aub_write.c b/src/intel/to

[Mesa-dev] [PATCH 02/20] intel/aub_write: split comment section from HW setup

In the future we'll want error2aub to reuse the context image saved by i915 instead of the default one we write in intel_dump_gpu. Signed-off-by: Lionel Landwerlin --- src/intel/tools/aub_write.c | 75 +--- src/intel/tools/aub_write.h | 1 + src/intel/tools

[Mesa-dev] [PATCH 06/20] intel/aub_write: log mmio writes

Signed-off-by: Lionel Landwerlin --- src/intel/tools/aub_write.c | 5 + 1 file changed, 5 insertions(+) diff --git a/src/intel/tools/aub_write.c b/src/intel/tools/aub_write.c index 7b435fcd893..a4cb474e1e7 100644 --- a/src/intel/tools/aub_write.c +++ b/src/intel/tools/aub_write.c @@ -238,6 +

[Mesa-dev] [PATCH 00/20] intel/error2aub: place all buffers (GGTT/PPGTT)

Hi all, This series is adding support for placing all of the buffers reported by the i915 error state. The idea is to produce an aub file complete enough that it could be used to replay the last execbuffer that triggered a hang. In particular we want to place the GGTT buffers containing the logica

[Mesa-dev] [PATCH 01/20] intel/aub_read: handle video engine execlists writes

We don't strictly need this, but because we setup the engine in aub_write, it might be worth parsing it correctly for the sake of completeness. Signed-off-by: Lionel Landwerlin --- src/intel/tools/aub_read.c | 23 +++ src/intel/tools/aub_read.h | 3 +++ 2 files changed, 26 i

Re: [Mesa-dev] [PATCH] Revert "mesa: remove unnecessary 'sort by year' for the GL extensions"

I confirm that this does indeed fix Elite Force On 2018-09-24 17:19, Emil Velikov wrote: This reverts commit 3d81e11b49366b5636b8524ba0f8c7076e3fdf34. As reported by Federico, some games require the 'sort by year' since they truncate the extensions which do not fit the fixed size string array.