[Mesa-dev] [Bug 107096] GLSL disk cache: blob format changes may cause segfaults etc.

https://bugs.freedesktop.org/show_bug.cgi?id=107096 Darren Salt changed: What|Removed |Added Hardware|Other |All --- Comment #1 from Darren Salt ---

[Mesa-dev] [Bug 107096] GLSL disk cache: blob format changes may cause segfaults etc.

https://bugs.freedesktop.org/show_bug.cgi?id=107096 Bug ID: 107096 Summary: GLSL disk cache: blob format changes may cause segfaults etc. Product: Mesa Version: unspecified Hardware: Other OS: All

[Mesa-dev] [PATCH 2/2] i965/vec4: Make the vec4_visitor::nir_emit_instr default case unreachable

From: Ian Romanick The bug fixed by the previous commit went undetected because extra stderr messages are not flagged by the CI. Copy the solution from fs_visitor::nir_emit_instr and mark the default case unreachable. An alternate solution is to delete the default case so that the compiler will

[Mesa-dev] [PATCH 1/2] i965/vec4: Handle nir_instr_type_deref to silence run-time output

From: Ian Romanick Previously, shader-db runs on Gen5 through Haswell would spew tons of messages like: VS instruction not yet implemented by NIR->vec4 I checked several instance of this, and all of them were nir_instr_type_deref instructions in vertex shaders that had texture accesses (e.g

Re: [Mesa-dev] Question about EGL_KHR_partial_update implementation

Hi Qiang, Qiang Yu writes: >> > For lima implementation, I want to use the damage region (buffer >> > damage) provided >> > by EGL_KHR_partial_update to skip rendering of un-damaged region when >> > eglSwapBuffersXXX. And tell damage region (surface damage) to compositor >> > should >> > be lef

Re: [Mesa-dev] [PATCH 11/11] ac/radv: using tls to store llvm related info and speed up compiles (v3)

On 30 June 2018 at 14:11, Marek Olšák wrote: > I wonder if we can somehow make the TLS magic apply to RADV only. > Radeonsi can do it without TLS. Then, the RADV-specific TLS code can be > moved to RADV, and other code (if any) can be shared. > > It doesn't make much sense to do the TLS initializa

Re: [Mesa-dev] Question about EGL_KHR_partial_update implementation

Hi Harish, > > > To my understand this extension should only depend on the driver support > > instead > > of platform support while the EGL_KHR_swap_buffers_with_damage is the > > opposite: > > https://www.khronos.org/registry/EGL/extensions/KHR/EGL_KHR_swap_buffers_with_damage.txt > > > > I alw

[Mesa-dev] [Bug 107092] Thread leak when changing context size

https://bugs.freedesktop.org/show_bug.cgi?id=107092 --- Comment #3 from Roland Scheidegger --- I'm near certain this is a bug in the xlib state tracker rather than llvmpipe. swr will leak as well, you just don't notice because it doesn't create additional threads. glXChooseFBConfig will call choo

Re: [Mesa-dev] Question about EGL_KHR_partial_update implementation

Hi Qiang, Thanks for probing about this. Qiang Yu writes: > Hi Harish, > > I want to implement EGL_KHR_partial_update for lima mesa driver and find you > worked on Android/Wayland support for it: > https://patchwork.freedesktop.org/patch/160944/ > https://patchwork.freedesktop.org/patch/188695/

[Mesa-dev] [PATCH] radv: using tls to store llvm related info and speed up compiles (v6)

From: Dave Airlie I'd like to encourage people to test this to see if it helps (like does it make app startup better or less hitching in dxvk). The basic idea is to store a bunch of LLVM related data structs in thread local storage so we can avoid reiniting them every time we compile a shader. S

[Mesa-dev] radv add thread local storage for compiler info

This just ports the last patch I posted to be a pure radv patch, it doesn't add the radeonsi bits to it at this stage. I think I'd prefer to land this and then we can work on understanding how best to add the same features to radeonsi without causing any possible regressions or driver specific cod

[Mesa-dev] [PATCH] radv: using tls to store llvm related info and speed up compiles (v5)

From: Dave Airlie I'd like to encourage people to test this to see if it helps (like does it make app startup better or less hitching in dxvk). The basic idea is to store a bunch of LLVM related data structs in thread local storage so we can avoid reiniting them every time we compile a shader. S

Re: [Mesa-dev] [PATCH 11/12] nir: Add partial redundancy elimination for compares

On 06/28/2018 05:19 PM, Caio Marcelo de Oliveira Filho wrote: > Hi, > > On Wed, Jun 27, 2018 at 09:46:24PM -0700, Ian Romanick wrote: >> From: Ian Romanick >> >> This pass attempts to dectect code sequences like >> >> if (x < y) { >> z = y - z; > > Typo "z = x - y". > > >> Current

[Mesa-dev] [PATCH 11/11] ac: make some fns static

From: Dave Airlie Some of the compiler functions are no longer called outside the util file. --- src/amd/common/ac_llvm_util.c | 12 ++-- src/amd/common/ac_llvm_util.h | 7 --- 2 files changed, 6 insertions(+), 13 deletions(-) diff --git a/src/amd/common/ac_llvm_util.c b/src/amd/co

[Mesa-dev] [PATCH 09/11] ac/radeonsi: port compiler init/destroy out of radeonsi.

From: Dave Airlie We want to share this code with radv in the future, so port it out of radeonsi. Add a return value as radv will want that to know if this succeeds --- src/amd/common/ac_llvm_util.c | 43 ++ src/amd/common/ac_llvm_util.h | 6 src/

[Mesa-dev] [PATCH 07/11] radeonsi: rename si_compiler -> ac_llvm_compiler

From: Dave Airlie As precursor to moving init to common code, just rename the struct and move it. --- src/amd/common/ac_llvm_util.h | 7 ++ src/gallium/drivers/radeonsi/si_compute.c | 2 +- src/gallium/drivers/radeonsi/si_pipe.c| 4 ++-- src/gallium/drivers/rad

[Mesa-dev] [PATCH 06/11] ac: add target library info helpers

From: Dave Airlie --- src/amd/common/ac_llvm_helper.cpp | 13 + src/amd/common/ac_llvm_util.h | 2 ++ 2 files changed, 15 insertions(+) diff --git a/src/amd/common/ac_llvm_helper.cpp b/src/amd/common/ac_llvm_helper.cpp index 495bd98da9c..48a5a44e392 100644 --- a/src/amd/common

[Mesa-dev] [PATCH 02/11] radv: drop copy of ac_create_target_machine.

From: Dave Airlie Once we split the init once stuff out, this can be shared again. --- src/amd/vulkan/radv_shader.c | 32 +--- 1 file changed, 1 insertion(+), 31 deletions(-) diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index 749e89e4bf7..

[Mesa-dev] [PATCH 04/11] radv: port to use common passmgr code.

From: Dave Airlie This adds a inline always pass, but otherwise should work the same. --- src/amd/common/ac_llvm_util.c | 5 +++-- src/amd/vulkan/radv_nir_to_llvm.c | 26 +++--- 2 files changed, 6 insertions(+), 25 deletions(-) diff --git a/src/amd/common/ac_llvm_util.c

[Mesa-dev] [PATCH 10/11] ac/radv: move llvm compiler info to struct and init in one place

From: Dave Airlie This ports radv to the shared code, however due to a bug in LLVM version prior to 7, radv cannot add target info at this stage, as it would leak one for every shader compile, however I'd prefer to keep this llvm damage in the shared code, since it isn't the driver at fault here.

[Mesa-dev] [PATCH 01/11] ac/radv: split the non-common init_once code from the common target code. (v2)

From: Dave Airlie This just splits out the non-shared code and reuses ac_get_llvm_target in radv. v2: rebase on Marek's patch - fixup brace position/whitespace --- src/amd/common/ac_llvm_util.c | 7 +-- src/amd/common/ac_llvm_util.h | 2 ++ src/amd/vulkan/radv_shader.c

[Mesa-dev] [PATCH 03/11] ac/radeonsi: refactor out pass manager init to common code.

From: Dave Airlie --- src/amd/common/ac_llvm_util.c | 30 ++ src/amd/common/ac_llvm_util.h | 2 ++ src/gallium/drivers/radeonsi/si_pipe.c | 27 ++- 3 files changed, 34 insertions(+), 25 deletions(-) diff --git a/src/amd/common/ac_ll

[Mesa-dev] ac/radeonsi/radv: share more compiler code

This is the prep work patches for storing the compiler in TLS for radv. I'm revising how I think that should end up looking in light of Marek's review, but I think we could at least land this chunk of the setup code first. I've moved some of these around since the last posting, and renamed a few th

[Mesa-dev] [PATCH 08/11] radv/radeonsi: add a check ir tm options

From: Dave Airlie This doesn't do much yet, but it makes it easier to move the code to a common shared code base. --- src/amd/common/ac_llvm_util.h | 1 + src/amd/vulkan/radv_shader.c | 4 +++- src/gallium/drivers/radeonsi/si_pipe.c | 5 +++-- 3 files changed, 7 insertions(+),

[Mesa-dev] [PATCH 05/11] radv: create/destroy passmgr at the higher level.

From: Dave Airlie This is prep work for moving this to a per-thread struct --- src/amd/vulkan/radv_nir_to_llvm.c | 15 +++ src/amd/vulkan/radv_private.h | 2 ++ src/amd/vulkan/radv_shader.c | 7 +-- 3 files changed, 14 insertions(+), 10 deletions(-) diff --git a/src/a

[Mesa-dev] [Bug 107090] nir: problem case for loop unrolling

https://bugs.freedesktop.org/show_bug.cgi?id=107090 Timothy Arceri changed: What|Removed |Added Status|NEW |NEEDINFO --- Comment #1 from Timothy A

Re: [Mesa-dev] [PATCH v2 00/16] ARB_gl_spirv series 3 v2: support for atomic counters

Series looks good to me. How much to go before we can turn this extension on? On 03/07/18 00:58, Alejandro Piñeiro wrote: Hi Timothy. Thanks for the quick review! As you suggested some squash and commit drops, Im resending the v2 of the series, just in case you want a final overview of the ser

Re: [Mesa-dev] [PATCH 13/16] nir: Fix OpAtomicCounterIDecrement for uniform atomic counters

Thanks. Reviewed-by: Timothy Arceri On 03/07/18 00:58, Alejandro Piñeiro wrote: From: Antia Puentes From the SPIR-V 1.0 specification, section 3.32.18, "Atomic Instructions": "OpAtomicIDecrement: The instruction's result is the Original Value." However, we were implementing

Re: [Mesa-dev] [PATCH v2] mesa: enable EXT_render_snorm extension

On Fri, Jun 15, 2018 at 08:11:57AM +0300, Tapani Pälli wrote: > Patch sets additional formats renderable and enables the extension > when OpenGL ES 3.1 is supported. > > v2: instead of dummy_true, have a separate toggle for extension > (Eric Anholt) > > Signed-off-by: Tapani Pälli > --- > s

Re: [Mesa-dev] [PATCH 3/3] anv: Implement VK_EXT_vertex_attribute_divisor

> How about this version? > https://gitlab.freedesktop.org/jekstrand/mesa/commits/wip/VK_EXT_vertex_attribute_divisor > > I've changed it to first grab the vertex divisors from the struct and then > the multiview handling is a *=. This moves it to more of a "set a bunch of > stuff then compile" m

Re: [Mesa-dev] [PATCH 11/16] nir/types: Add wrappers for a couple of atomic counter methods

you missed my r-b here ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 20/23] intel/eu: Rework opcode description tables to allow efficient look-up by either HW or IR opcode.

> >> +nodist_EXTRA_tools_aubinator_SOURCES = dummy.cpp > >> + > >> tools_aubinator_CFLAGS = \ > >>$(AM_CFLAGS) \ > >>$(ZLIB_CFLAGS) > >> @@ -47,6 +49,8 @@ tools_aubinator_LDADD = \ > >> tools_aubinator_error_decode_SOURCES = \ > >>tools/aubinator_error_decode.c > >> > >> +nodist_EXT

Re: [Mesa-dev] [PATCH 20/23] intel/eu: Rework opcode description tables to allow efficient look-up by either HW or IR opcode.

Caio Marcelo de Oliveira Filho writes: >> diff --git a/src/intel/Makefile.tools.am b/src/intel/Makefile.tools.am >> index b00cc8cc2cb..4f2027cdfd6 100644 >> --- a/src/intel/Makefile.tools.am >> +++ b/src/intel/Makefile.tools.am >> @@ -27,6 +27,8 @@ tools_aubinator_SOURCES = \ >> tools/aubina

Re: [Mesa-dev] [PATCH 11/11] ac/radv: using tls to store llvm related info and speed up compiles (v3)

On 30 June 2018 at 14:11, Marek Olšák wrote: > I wonder if we can somehow make the TLS magic apply to RADV only. > Radeonsi can do it without TLS. Then, the RADV-specific TLS code can be > moved to RADV, and other code (if any) can be shared. It's not the TLS code that is going to cause the probl

Re: [Mesa-dev] [PATCH 07/11] ac/radv: move llvm compiler info to struct and init in one place

On 30 June 2018 at 13:30, Marek Olšák wrote: > On Tue, Jun 26, 2018 at 11:58 PM, Dave Airlie wrote: >> From: Dave Airlie >> >> This creates a common per-thread compiler info struct, and adds >> the init code to it. This is mostly ported from radeonsi. >> >> The common info struct is used in radv

Re: [Mesa-dev] [PATCH 07/12] intel/compiler: More peephole select

On 06/28/2018 03:25 PM, Caio Marcelo de Oliveira Filho wrote: > Hi, > >> diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c >> index 67c062d91f5..6a0d4090fa7 100644 >> --- a/src/intel/compiler/brw_nir.c >> +++ b/src/intel/compiler/brw_nir.c >> @@ -557,7 +557,22 @@ brw_nir_opt

Re: [Mesa-dev] [PATCH] glsl: skip mul by zero opt for floating point expression

On 07/02/2018 08:22 AM, vadym.shovkoplias wrote: > From: Vadym Shovkoplias > > One of the operands can be NaN and multiplication by zero > should also result to NaN value. E.g: > > float Temp = 0.0; > void main() > { > Temp = log2(Temp); > Temp = Temp * 0.0; > isnan(Temp); >

[Mesa-dev] [Bug 107089] [GLSL] "Multiplication by zero" optimization for floating point expression should be skipped

https://bugs.freedesktop.org/show_bug.cgi?id=107089 --- Comment #3 from Ian Romanick --- Basically, unless you use precise, it's like compiling -ffast-math. A lot of apps go to lengths to avoid the possibility of generating Inf or NaN in shaders due the the problems that they cause. -- You are

Re: [Mesa-dev] [PATCH 3/3] anv: Implement VK_EXT_vertex_attribute_divisor

On Mon, Jul 2, 2018 at 3:26 PM, Caio Marcelo de Oliveira Filho < caio.olive...@intel.com> wrote: > > > @@ -1430,6 +1431,18 @@ anv_pipeline_init(struct anv_pipeline *pipeline, > > > anv_subpass_view_count(pipeline->subpass); > > > } > > > > > > + const VkPipelineVertexInputDivisorSt

Re: [Mesa-dev] [PATCH 3/3] anv: Implement VK_EXT_vertex_attribute_divisor

> > @@ -1430,6 +1431,18 @@ anv_pipeline_init(struct anv_pipeline *pipeline, > > anv_subpass_view_count(pipeline->subpass); > > } > > > > + const VkPipelineVertexInputDivisorStateCreateInfoEXT *vi_div_state = > > + vk_find_struct_const(pCreateInfo->pNext, > > +

Re: [Mesa-dev] [PATCH 3/3] anv: Implement VK_EXT_vertex_attribute_divisor

Patches 1-3 are Reviewed-by: Caio Marcelo de Oliveira Filho But consider comment below. > @@ -1430,6 +1431,18 @@ anv_pipeline_init(struct anv_pipeline *pipeline, > anv_subpass_view_count(pipeline->subpass); > } > > + const VkPipelineVertexInputDivisorStateCreateInfoEXT *vi_di

Re: [Mesa-dev] [PATCH] i965: Fix BRW_NEW_NUM_SAMPLES to be in .brw, not .mesa

Reviewed-by: Jason Ekstrand On Mon, Jul 2, 2018 at 2:19 PM, Kenneth Graunke wrote: > This is the wrong kind of dirty bit. Caught by GCC warnings, due to > 64-bit values being truncated to 32 bits. > > Fixes: b95b0e2918c052068caeb4f6c2802ba89be043a3 (intel/anv,blorp,i965: > Implement the SKL 16

[Mesa-dev] [PATCH 3/3] anv: Implement VK_EXT_vertex_attribute_divisor

--- src/intel/vulkan/anv_device.c | 8 src/intel/vulkan/anv_extensions.py | 1 + src/intel/vulkan/anv_pipeline.c| 13 + 3 files changed, 22 insertions(+) diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c index 7b3ddbb9501..fc2576db1e6 10064

[Mesa-dev] [PATCH 2/3] anv/pipeline: Add a per-VB instance divisor

--- src/intel/vulkan/anv_pipeline.c| 8 src/intel/vulkan/anv_private.h | 1 + src/intel/vulkan/genX_cmd_buffer.c | 7 +-- src/intel/vulkan/genX_pipeline.c | 8 ++-- 4 files changed, 12 insertions(+), 12 deletions(-) diff --git a/src/intel/vulkan/anv_pipeline.c b/src/int

[Mesa-dev] [PATCH 1/3] anv/pipeline: Use a per-VB struct instead of separate arrays

--- src/intel/vulkan/anv_pipeline.c| 6 +++--- src/intel/vulkan/anv_private.h | 7 +-- src/intel/vulkan/genX_cmd_buffer.c | 4 ++-- src/intel/vulkan/genX_pipeline.c | 2 +- 4 files changed, 11 insertions(+), 8 deletions(-) diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vul

Re: [Mesa-dev] [PATCH 20/23] intel/eu: Rework opcode description tables to allow efficient look-up by either HW or IR opcode.

> diff --git a/src/intel/Makefile.tools.am b/src/intel/Makefile.tools.am > index b00cc8cc2cb..4f2027cdfd6 100644 > --- a/src/intel/Makefile.tools.am > +++ b/src/intel/Makefile.tools.am > @@ -27,6 +27,8 @@ tools_aubinator_SOURCES = \ > tools/aubinator.c \ > tools/intel_aub.h > > +nodis

[Mesa-dev] [Bug 106644] [llvmpipe] Mesa 18.1.2 fails lp_test_format, lp_test_arit, lp_test_blend, lp_test_printf, lp_test_conv tests

https://bugs.freedesktop.org/show_bug.cgi?id=106644 --- Comment #22 from Ben Crocker --- Would you please run the lp_test_* tests with the following environmental controls in place: % export LIBGL_DEBUG=verbose % export MESA_DEBUG=verbose % export MESA_GLSL="" % export MESA_GLSL="dump log unifo

[Mesa-dev] [PATCH] i965: Fix BRW_NEW_NUM_SAMPLES to be in .brw, not .mesa

This is the wrong kind of dirty bit. Caught by GCC warnings, due to 64-bit values being truncated to 32 bits. Fixes: b95b0e2918c052068caeb4f6c2802ba89be043a3 (intel/anv,blorp,i965: Implement the SKL 16x MSAA SIMD32 workaround) --- src/mesa/drivers/dri/i965/genX_state_upload.c | 4 ++-- 1 file c

[Mesa-dev] [Bug 107092] Thread leak when changing context size

https://bugs.freedesktop.org/show_bug.cgi?id=107092 Cory Quammen changed: What|Removed |Added CC||cory.quam...@kitware.com -- You are rec

[Mesa-dev] [Bug 107092] Thread leak when changing context size

https://bugs.freedesktop.org/show_bug.cgi?id=107092 --- Comment #2 from Cory Quammen --- Please note that the apitrace output is from a single iteration of the loop in vtk-mesa-threads-growth.py -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for

[Mesa-dev] [Bug 107092] Thread leak when changing context size

https://bugs.freedesktop.org/show_bug.cgi?id=107092 --- Comment #1 from Cory Quammen --- Created attachment 140441 --> https://bugs.freedesktop.org/attachment.cgi?id=140441&action=edit VTK Python script showing the thread leak -- You are receiving this mail because: You are the QA Contact for

[Mesa-dev] [Bug 107092] Thread leak when changing context size

https://bugs.freedesktop.org/show_bug.cgi?id=107092 Bug ID: 107092 Summary: Thread leak when changing context size Product: Mesa Version: unspecified Hardware: Other OS: All Status: NEW Severity: normal

[Mesa-dev] [Bug 106843] Cannot build osmesa with GLES (shared glapi) using Scons and MSVC

https://bugs.freedesktop.org/show_bug.cgi?id=106843 --- Comment #7 from Alex Granni --- (In reply to Eric Engestrom from comment #4) > Hi Alex, > Would you mind testing the work-in-progress branch and report if it works > when building with Meson? > git://people.freedesktop.org/~dbaker/mesa meson

Re: [Mesa-dev] [PATCH] st/nir: Disable varying packing when doing transform feedback.

Eric Anholt writes: > [ Unknown signature status ] > Timothy Arceri writes: > >> nir_compact_varyings() is meant to skip over varyings used by xfb: >> >> /* We can't repack xfb varyings. */ >> if (var->data.always_active_io) >> continue; >> >> Any idea why that i

Re: [Mesa-dev] [PATCH v2 4/9] nir/deref: Add helpers for getting offsets

On Mon, Jul 2, 2018 at 11:10 AM, Kenneth Graunke wrote: > On Friday, June 29, 2018 5:13:52 PM PDT Jason Ekstrand wrote: > > These are very similar to the related function in nir_lower_io except > > that they don't handle per-vertex or packed things (that could be added, > > in theory) and they ta

Re: [Mesa-dev] [PATCH v2 0/9] anv, nir: Move large constants to a UBO

On Mon, Jul 2, 2018 at 11:26 AM, Kenneth Graunke wrote: > On Friday, June 29, 2018 5:13:48 PM PDT Jason Ekstrand wrote: > > This little series adds an optimization pass to NIR and wires up up in > anv > > that moves large constant variables to a UBO. This fixes a farily common > > case in some f

[Mesa-dev] [Bug 107089] [GLSL] "Multiplication by zero" optimization for floating point expression should be skipped

https://bugs.freedesktop.org/show_bug.cgi?id=107089 --- Comment #2 from Roland Scheidegger --- (In reply to Ilia Mirkin from comment #1) > So NaN * 0 -> 0 appears to be a valid transformation. I haven't gone back > and checked what's in the core specs, but I doubt it's any different. For this par

Re: [Mesa-dev] [PATCH] r600: compare structure elements instead of doing a memcmp

Looks good to me. Although I wonder if it wouldn't be a good idea to make sure it's actually all initialized (via memset). But I think that's not quite consistently handled the same everywhere (that is, some things are memset, some are not). (There might be similar bugs lurking elswhere, but OTOH t

Re: [Mesa-dev] [PATCH v2 0/9] anv, nir: Move large constants to a UBO

On Friday, June 29, 2018 5:13:48 PM PDT Jason Ekstrand wrote: > This little series adds an optimization pass to NIR and wires up up in anv > that moves large constant variables to a UBO. This fixes a farily common > case in some filter or ambient occlusion shaders where they put some sort > of loo

Re: [Mesa-dev] [PATCH 1/1] mesa/st: draw_vbo: initialize restart_index too

Reviewed-by: Roland Scheidegger Am 01.07.2018 um 10:05 schrieb Gert Wollny: > From: Gert Wollny > > restart_index is later always used in a comparison, so it should be > initialized properly. > > Fixes valgrind warning: > Conditional jump or move depends on uninitialised value(s) > at 0xB

Re: [Mesa-dev] [PATCH 3/3] r600: Scale interger valued texture border colors to float

Am 01.07.2018 um 19:32 schrieb Gert Wollny: > It seems the hardware always expects floating point border color values > [0,1] for unsigned, and [-1,1] for signed texture component, regardless > of pixel type, but the border colors are passed according to texture > component type. Hence, before subm

Re: [Mesa-dev] [PATCH 05/12] nir: Make deref_has_indirect public

On July 2, 2018 12:58:47 Caio Marcelo de Oliveira Filho wrote: diff --git a/src/compiler/nir/nir_lower_io_arrays_to_elements.c b/src/compiler/nir/nir_lower_io_arrays_to_elements.c index 9a5eec8f870..7753f85824d 100644 --- a/src/compiler/nir/nir_lower_io_arrays_to_elements.c +++ b/src/compiler

Re: [Mesa-dev] [PATCH v2 4/9] nir/deref: Add helpers for getting offsets

On Friday, June 29, 2018 5:13:52 PM PDT Jason Ekstrand wrote: > These are very similar to the related function in nir_lower_io except > that they don't handle per-vertex or packed things (that could be added, > in theory) and they take a more detailed size/align function pointer. > One day, we shou

Re: [Mesa-dev] [PATCH v2 1/9] util/macros: Import ALIGN_POT from ralloc.c

On Monday, July 2, 2018 7:59:31 AM PDT Jason Ekstrand wrote: > v2 (Jason Ekstrand): > - Rename y to pot_align (Brian) > - Also use ALIGN_POT in build_id.c and slab.c (Brian) > > Cc: Brian Paul > Reviewed-by: Timothy Arceri > --- > src/util/build_id.c | 7 +++ > src/util/macros.h | 3 +++

Re: [Mesa-dev] [PATCH 05/12] nir: Make deref_has_indirect public

> diff --git a/src/compiler/nir/nir_lower_io_arrays_to_elements.c > b/src/compiler/nir/nir_lower_io_arrays_to_elements.c > index 9a5eec8f870..7753f85824d 100644 > --- a/src/compiler/nir/nir_lower_io_arrays_to_elements.c > +++ b/src/compiler/nir/nir_lower_io_arrays_to_elements.c > @@ -194,12 +194,1

Re: [Mesa-dev] [PATCH 1/3] r600: force LOD range to be only one value when mip.min filter is NONE

Am 01.07.2018 um 19:32 schrieb Gert Wollny: > For a texture that has only one LOD defined, but for which > GL_TEXTURE_MAX_LEVEL is the default (1000) and > GL_TEXTURE_MIN_LOD != GL_TEXTURE_MAX_LOD the reading from the texture does > not properly resolve the LOD level and texture lookup might fail.

[Mesa-dev] [Bug 107090] nir: problem case for loop unrolling

https://bugs.freedesktop.org/show_bug.cgi?id=107090 Bug ID: 107090 Summary: nir: problem case for loop unrolling Product: Mesa Version: git Hardware: Other OS: All Status: NEW Severity: normal Pr

[Mesa-dev] [PATCH] radv/winsys: make use of radeon_emit()

Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c | 31 ++- 1 file changed, 16 insertions(+), 15 deletions(-) diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c index 848e81924f..9eebcd9ea0 10

Re: [Mesa-dev] [PATCH v2 1/9] util/macros: Import ALIGN_POT from ralloc.c

On 07/02/2018 10:50 AM, Jason Ekstrand wrote: On Mon, Jul 2, 2018 at 9:23 AM, Brian Paul > wrote: On 07/02/2018 09:00 AM, Jason Ekstrand wrote: On Mon, Jul 2, 2018 at 6:33 AM, Brian Paul mailto:bri...@vmware.com>

Re: [Mesa-dev] [PATCH 2/2] mesa: don't double incr/decr ActiveCounters

On Mon, Jul 2, 2018 at 12:15 PM, Brian Paul wrote: > On 07/02/2018 09:13 AM, Rob Clark wrote: >> >> Frameretrace ends up w/ excess calls to SelectPerfMonitorCountersAMD() >> which ends up re-enabling already enabled counters. Which causes >> ActiveCounters[group] to be double incremented for the

Re: [Mesa-dev] [PATCH v2 1/9] util/macros: Import ALIGN_POT from ralloc.c

On Mon, Jul 2, 2018 at 9:23 AM, Brian Paul wrote: > On 07/02/2018 09:00 AM, Jason Ekstrand wrote: > >> On Mon, Jul 2, 2018 at 6:33 AM, Brian Paul > bri...@vmware.com>> wrote: >> >> On 06/29/2018 06:13 PM, Jason Ekstrand wrote: >> >> --- >>src/util/macros.h | 3 +++ >>

Re: [Mesa-dev] [PATCH v2 1/9] util/macros: Import ALIGN_POT from ralloc.c

On 07/02/2018 09:00 AM, Jason Ekstrand wrote: On Mon, Jul 2, 2018 at 6:33 AM, Brian Paul > wrote: On 06/29/2018 06:13 PM, Jason Ekstrand wrote: ---   src/util/macros.h | 3 +++   src/util/ralloc.c | 2 --   2 files changed, 3 insert

Re: [Mesa-dev] [PATCH 1/2] mesa: fix error msg typo

On 07/02/2018 09:13 AM, Rob Clark wrote: Signed-off-by: Rob Clark --- src/mesa/main/performance_monitor.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/main/performance_monitor.c b/src/mesa/main/performance_monitor.c index 65ea8437fd8..35972ff 100644 --- a/

Re: [Mesa-dev] [PATCH 2/2] mesa: don't double incr/decr ActiveCounters

On 07/02/2018 09:13 AM, Rob Clark wrote: Frameretrace ends up w/ excess calls to SelectPerfMonitorCountersAMD() which ends up re-enabling already enabled counters. Which causes ActiveCounters[group] to be double incremented for the same counter. This causes BeginPerfMonitorAMD() to fail. The AM

[Mesa-dev] [PATCH v6] nv50/ir, nvc0: add debug options for shader replacement

Changes in v6: - Fix heap overflow in createDumpFilename() Changes in v5: - Add a forgotten change to fix memory leaks of fname Changes in v4: - Move code to nv50_ir_dump.cpp - Dump headers of nvc0 programs - Use CRC-32 instead of a truncated SHA1 - Set prog->maxGPR to targ->getFileSize() - 1 and s

Re: [Mesa-dev] [PATCH] glsl: skip mul by zero opt for floating point expression

On Mon, Jul 2, 2018 at 11:22 AM, vadym.shovkoplias wrote: > From: Vadym Shovkoplias > > One of the operands can be NaN and multiplication by zero > should also result to NaN value. E.g: See my comment in https://bugs.freedesktop.org/show_bug.cgi?id=107089#c1 > > float Temp = 0.0; > void main()

[Mesa-dev] [Bug 107089] [GLSL] "Multiplication by zero" optimization for floating point expression should be skipped

https://bugs.freedesktop.org/show_bug.cgi?id=107089 --- Comment #1 from Ilia Mirkin --- GLSL's approach to NaN is pretty weak. https://www.khronos.org/registry/OpenGL/extensions/ARB/ARB_shader_precision.txt """ The following rules apply to both single and double precision operations:

[Mesa-dev] [PATCH] glsl: skip mul by zero opt for floating point expression

From: Vadym Shovkoplias One of the operands can be NaN and multiplication by zero should also result to NaN value. E.g: float Temp = 0.0; void main() { Temp = log2(Temp); Temp = Temp * 0.0; isnan(Temp); ... } here Temp should be NaN and isnan() should return true

[Mesa-dev] [Bug 107089] [GLSL] "Multiplication by zero" optimization for floating point expression should be skipped

https://bugs.freedesktop.org/show_bug.cgi?id=107089 Bug ID: 107089 Summary: [GLSL] "Multiplication by zero" optimization for floating point expression should be skipped Product: Mesa Version: unspecified Hardware: Other

[Mesa-dev] [PATCH 1/2] mesa: fix error msg typo

Signed-off-by: Rob Clark --- src/mesa/main/performance_monitor.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/main/performance_monitor.c b/src/mesa/main/performance_monitor.c index 65ea8437fd8..35972ff 100644 --- a/src/mesa/main/performance_monitor.c +++ b/src

[Mesa-dev] [PATCH 2/2] mesa: don't double incr/decr ActiveCounters

Frameretrace ends up w/ excess calls to SelectPerfMonitorCountersAMD() which ends up re-enabling already enabled counters. Which causes ActiveCounters[group] to be double incremented for the same counter. This causes BeginPerfMonitorAMD() to fail. The AMD_performance_monitor spec doesn't say that

[Mesa-dev] [Bug 106644] [llvmpipe] Mesa 18.1.2 fails lp_test_format, lp_test_arit, lp_test_blend, lp_test_printf, lp_test_conv tests

https://bugs.freedesktop.org/show_bug.cgi?id=106644 erhar...@mailbox.org changed: What|Removed |Added Summary|[llvmpipe] Mesa 18.1.0 |[llvmpipe] Mesa 18.1.2

[Mesa-dev] [Bug 106644] [llvmpipe] Mesa 18.1.0 fails lp_test_format, lp_test_arit, lp_test_blend, lp_test_printf, lp_test_conv tests

https://bugs.freedesktop.org/show_bug.cgi?id=106644 erhar...@mailbox.org changed: What|Removed |Added Attachment #139749|0 |1 is obsolete|

[Mesa-dev] [Bug 106644] [llvmpipe] Mesa 18.1.0 fails lp_test_format, lp_test_arit, lp_test_blend, lp_test_printf, lp_test_conv tests

https://bugs.freedesktop.org/show_bug.cgi?id=106644 erhar...@mailbox.org changed: What|Removed |Added Attachment #139748|0 |1 is obsolete|

[Mesa-dev] [Bug 106644] [llvmpipe] Mesa 18.1.0 fails lp_test_format, lp_test_arit, lp_test_blend, lp_test_printf, lp_test_conv tests

https://bugs.freedesktop.org/show_bug.cgi?id=106644 erhar...@mailbox.org changed: What|Removed |Added Attachment #139747|0 |1 is obsolete|

Re: [Mesa-dev] [PATCH] spirv: Implicitly set missing NonWriteable decoration

This should be fixed in upstream dxvk so let's not put the hack in mesa: https://github.com/doitsujin/dxvk/issues/460 On Wed, Jun 27, 2018 at 6:25 PM, Jason Ekstrand wrote: > This works around rendering issues in Skyrim caused by DXVK missing a > decoration. > --- > src/compiler/spirv/vtn_vari

[Mesa-dev] [Bug 106644] [llvmpipe] Mesa 18.1.0 fails lp_test_format, lp_test_arit, lp_test_blend, lp_test_printf, lp_test_conv tests

https://bugs.freedesktop.org/show_bug.cgi?id=106644 erhar...@mailbox.org changed: What|Removed |Added Attachment #139746|0 |1 is obsolete|

[Mesa-dev] [Bug 106644] [llvmpipe] Mesa 18.1.0 fails lp_test_format, lp_test_arit, lp_test_blend, lp_test_printf, lp_test_conv tests

https://bugs.freedesktop.org/show_bug.cgi?id=106644 erhar...@mailbox.org changed: What|Removed |Added Attachment #139745|0 |1 is obsolete|

Re: [Mesa-dev] [PATCH v2 1/9] util/macros: Import ALIGN_POT from ralloc.c

On Mon, Jul 2, 2018 at 6:33 AM, Brian Paul wrote: > On 06/29/2018 06:13 PM, Jason Ekstrand wrote: > >> --- >> src/util/macros.h | 3 +++ >> src/util/ralloc.c | 2 -- >> 2 files changed, 3 insertions(+), 2 deletions(-) >> >> diff --git a/src/util/macros.h b/src/util/macros.h >> index 6d3df9040

Re: [Mesa-dev] [PATCH v2 00/16] ARB_gl_spirv series 3 v2: support for atomic counters

Forgot to CC Timothy. On 02/07/18 16:58, Alejandro Piñeiro wrote: > Hi Timothy. Thanks for the quick review! > > As you suggested some squash and commit drops, Im resending the v2 of > the series, just in case you want a final overview of the series > (although it is somewhat an overkill, I know)

[Mesa-dev] [PATCH v2 1/9] util/macros: Import ALIGN_POT from ralloc.c

v2 (Jason Ekstrand): - Rename y to pot_align (Brian) - Also use ALIGN_POT in build_id.c and slab.c (Brian) Cc: Brian Paul Reviewed-by: Timothy Arceri --- src/util/build_id.c | 7 +++ src/util/macros.h | 3 +++ src/util/ralloc.c | 2 -- src/util/slab.c | 6 ++ 4 files changed,

[Mesa-dev] [PATCH 13/16] nir: Fix OpAtomicCounterIDecrement for uniform atomic counters

From: Antia Puentes From the SPIR-V 1.0 specification, section 3.32.18, "Atomic Instructions": "OpAtomicIDecrement: The instruction's result is the Original Value." However, we were implementing it, for uniform atomic counters, as a pre-decrement operation, as was the one available

[Mesa-dev] [PATCH 10/16] spirv/nir: add capability check for SpvCapabilityAtomicStorage

Capability that informs if atomic counters are supported. From SPIR-V 1.0 spec, section 3.7, "Storage Class", item 10 from table: (Column "Storage Class"): "AtomicCounter For holding atomic counters. Visible across all functions of the current invocation. Atomic counter-specific memory

[Mesa-dev] [PATCH 16/16] i965: Use the new nir atomic counter linker for SPIR-V shaders

From: Neil Roberts Reviewed-by: Timothy Arceri --- src/mesa/drivers/dri/i965/brw_link.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp b/src/mesa/drivers/dri/i965/brw_link.cpp index 8bc97fa4f3e..1071056f149 100644 --- a/src/mesa/drivers/dri/i965/

[Mesa-dev] [PATCH 06/16] spirv/nir: tweak nir type when storage class is SpvStorageClassAtomicCounter

GLSL types differentiates uint from atomic uint. On SPIR-V the type is uint, and the variable has a specific storage class. So we need to tweak the type based on the storage class. Ideally we would like to get the proper type at vtn_handle_type, but we don't have the storage class at that moment.

[Mesa-dev] [PATCH 08/16] spirv/nir: initialize offset on the nir var at vtn_create_variable

This is convenient when dealing with atomic counter uniforms. The alternative would be doing that at vtn_handle_atomics. Reviewed-by: Timothy Arceri --- src/compiler/spirv/vtn_variables.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/compiler/spirv/vtn_variables.c b/src/compiler/spirv

[Mesa-dev] [PATCH 07/16] nir/spirv: Fix atomic counter (multidimensional-)arrays

From: Antia Puentes When constructing NIR if we have a SPIR-V uint variable and the storage class is SpvStorageClassAtomicCounter, we store as NIR's glsl_type an atomic_uint to reflect the fact that the variable is an atomic counter. However, we were tweaking the type only for atomic_uint scalar

[Mesa-dev] [PATCH 12/16] nir/linker: Add a pure NIR implementation of the atomic counter linker

From: Neil Roberts This is mostly just a straight-forward conversion of link_assign_atomic_counter_resources to C directly using nir variables instead of GLSL IR variables. It is based on the version of link_assign_atomic_counter_resources in 6b8909f2d1906. I’m noting this here to make it easier

[Mesa-dev] [PATCH 15/16] i965: enable AtomicStorage capability for gen7+

That is the same gen requirement for ARB_shader_atomic_counters. Reviewed-by: Timothy Arceri --- src/mesa/drivers/dri/i965/brw_context.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index 9ced230ec14..e755d

[Mesa-dev] [PATCH 14/16] mesa/glspirv: lower workgroup access to offsets

From: Antia Puentes This will perform the CS shared lowering. See 8761a04d0d93 Reviewed-by: Timothy Arceri --- src/mesa/main/glspirv.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mesa/main/glspirv.c b/src/mesa/main/glspirv.c index c585bc51bbf..8ad6c373914 100644 --- a/src/mesa/main

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