glPolygonOffset() has been part of the GL standard since 1.1. Also
niether AMD or Nvidia support this in their binary drivers.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=61761
---
docs/relnotes/18.2.0.html | 64 +
src/mapi/glapi/gen/gl_API.xml
From: Dave Airlie
For a multi-layer subpass resolve we want to make sure we flush all
the layers.
---
src/amd/vulkan/radv_meta_resolve.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_meta_resolve.c
b/src/amd/vulkan/radv_meta_resolve.c
index f3e088b10c4.
From: Dave Airlie
I don't think the hw resolve path can't handle multi-layer images.
This fixes all the:
dEQP-VK.renderpass.multisample_resolve.layers_*
tests on my VI card.
---
src/amd/vulkan/radv_meta_resolve.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/amd/vulkan/radv_meta_res
From: Dave Airlie
This path should iterate across all layers, I've some ideas
for doing this in a single pass, but this is simpler for now.
This passes the tests because we don't use the fragment path
unless we have DCC, and we don't have DCC on layered images.
---
src/amd/vulkan/radv_meta_reso
https://bugs.freedesktop.org/show_bug.cgi?id=34259
--- Comment #1 from Timothy Arceri ---
Hi Roland, is this bug still relevant or can it be closed?
--
You are receiving this mail because:
You are the assignee for the bug.___
mesa-dev mailing list
mes
https://bugs.freedesktop.org/show_bug.cgi?id=47166
Timothy Arceri changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
https://bugs.freedesktop.org/show_bug.cgi?id=92286
Timothy Arceri changed:
What|Removed |Added
Status|NEEDINFO|RESOLVED
Resolution|---
https://bugs.freedesktop.org/show_bug.cgi?id=105494
--- Comment #6 from Timothy Arceri ---
Could one of you create an apitrace of the problem and upload it to somewhere
like google drive. If the problem exists with i965 than it will be far easier
to do a git bisect using that driver.
--
You are
For 1-3,5: Reviewed-by: Brian Paul
On 05/10/2018 10:28 AM, Rhys Perry wrote:
This patch set adds support for GL_ARB_sample_locations in mesa core, gallium,
the mesa OpenGL state tracker and the nvc0 driver.
Changes in v2:
- various minor changes/cleanups (mostly formatting and style changes)
On 05/10/2018 10:21 AM, Marek Olšák wrote:
From: Marek Olšák
The slot index is always 0, and is pretty unlikely to change in the future.
---
src/gallium/auxiliary/cso_cache/cso_context.c | 52 ++-
src/gallium/auxiliary/cso_cache/cso_context.h | 5 ---
src/gallium/au
Reviewed-by: Marek Olšák
Marek
On Thu, May 10, 2018 at 7:27 PM, Jan Vesely wrote:
> Fixes memory leak on module unload.
>
> CC:
> Signed-off-by: Jan Vesely
> ---
> src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c | 7 ++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/sr
Hi All,
I developed the following infographic to inform readers about the various
parts that make up the Intel Mesa drivers. It is intended to help groups
inside Intel better understand the open source community, and at the same
time, it helps train newcomers to Mesa in driver architecture.
I ha
https://bugs.freedesktop.org/show_bug.cgi?id=103126
--- Comment #5 from Timothy Arceri ---
(In reply to Marek Olšák from comment #4)
> I don't think this has anything to do with 32 bits. There are 32-bit apps
> where glthread works. Witcher 2 is an app where glthread gets disabled.
Yeah it's not
https://bugs.freedesktop.org/show_bug.cgi?id=103126
--- Comment #4 from Marek Olšák ---
I don't think this has anything to do with 32 bits. There are 32-bit apps where
glthread works. Witcher 2 is an app where glthread gets disabled.
--
You are receiving this mail because:
You are the assignee
Fixes memory leak on module unload.
CC:
Signed-off-by: Jan Vesely
---
src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
index f4bb
Reviewed-by: Bruce Cherniak
> On May 4, 2018, at 1:40 PM, George Kyriazis wrote:
>
> Misc OpenSWR changes
>
> George Kyriazis (7):
> swr/rast: Change formatting
> swr/rast: Use binner topology to assemble backend attributes
> swr/rast: Add constant initializer for uint64_t
> swr/rast: Add
On Thu, May 10, 2018 at 4:39 PM, Jan Vesely wrote:
> Is this still needed for llvm-6.0.1?
>
Probably.
Marek
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mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
On Friday, May 4, 2018 5:56:04 PM PDT James Xiong wrote:
> From: "Xiong, James"
>
> Now that a bucket contains cached buffers with different sizes, go
> through its list and search for a cached buffer with enough size.
>
> Signed-off-by: Xiong, James
> ---
> src/mesa/drivers/dri/i965/brw_bufmg
Is this still needed for llvm-6.0.1?
On Mon, Apr 16, 2018 at 8:52 PM, Marek Olšák wrote:
> From: Marek Olšák
>
> ---
> src/gallium/drivers/radeonsi/si_pipe.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/
> radeonsi/si_
Factor in clear values wherever required while updating destination
min/max.
References: HSDES#160184
Signed-off-by: Michel Thierry
Cc: mesa-dev@lists.freedesktop.org
Cc: Mika Kuoppala
Cc: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_workarou
https://bugs.freedesktop.org/show_bug.cgi?id=106465
--- Comment #1 from Francisco Jerez ---
It should be trivial to extend the arb_shader_image_load_store-invalid piglit
test (which already checks a similar condition for other texture targets) to
catch this problem.
--
You are receiving this ma
Yes, I did. No regressions.
On Thu, May 10, 2018 at 12:09 PM, Jason Ekstrand wrote:
> Did you get a chance to test them?
>
>
> On May 10, 2018 11:58:54 Anuj Phogat wrote:
>
>> On Mon, May 7, 2018 at 2:56 PM, Jason Ekstrand
>> wrote:
>>>
>>> ---
>>> src/intel/isl/isl_storage_image.c | 16 ++
Did you get a chance to test them?
On May 10, 2018 11:58:54 Anuj Phogat wrote:
On Mon, May 7, 2018 at 2:56 PM, Jason Ekstrand wrote:
---
src/intel/isl/isl_storage_image.c | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/src/intel/isl/isl_storage_image.c
On Mon, May 7, 2018 at 2:56 PM, Jason Ekstrand wrote:
> ---
> src/intel/isl/isl_storage_image.c | 16 ++--
> 1 file changed, 10 insertions(+), 6 deletions(-)
>
> diff --git a/src/intel/isl/isl_storage_image.c
> b/src/intel/isl/isl_storage_image.c
> index 20f6fd5..ed1c600 100644
> ---
On Mon, Mar 19, 2018 at 11:26:56AM -0700, Francisco Jerez wrote:
> This reverts commit c0ed52f6146c7e24e1275451773bd47c1eda3145. It was
> preventing the image format validation from being done on buffer
> textures, which is required to ensure that the application doesn't
> attempt to create a buff
https://bugs.freedesktop.org/show_bug.cgi?id=106465
Bug ID: 106465
Summary: No test for Image Load/Store on format-incompatible
texture buffer
Product: Mesa
Version: git
Hardware: Other
OS: All
S
Plamena Manolova writes:
> This extension provides new GLSL built-in functions
> beginInvocationInterlockARB() and endInvocationInterlockARB()
> that delimit a critical section of fragment shader code. For
> pairs of shader invocations with "overlapping" coverage in a
> given pixel, the OpenGL im
Plamena Manolova writes:
> Adds suppport for ARB_fragment_shader_interlock. We achieve
> the interlock and fragment ordering by issuing a memory fence
> via sendc.
>
> Signed-off-by: Plamena Manolova
Reviewed-by: Francisco Jerez
> ---
> docs/features.txt| 2 +-
>
Tested-by: Mark Janes
Brian Paul writes:
> Since size can be 3, 4 or GL_BGRA we need to keep these glGet types
> as TYPE_INT, not TYPE_UBYTE.
>
> Fixes: d07466fe18522 ("mesa: fix glGetInteger/Float/etc queries for
> vertex arrays attribs")
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?i
Dear Sir,
I was really interested in contributing to your project DriConf
replacement. I want to know what you mean by "write an advanced
configuration tool for Mesa drivers". What all functionality or options
should it contain?
Thank You,
Vivek Raj.
__
Signed-off-by: Rhys Perry
---
docs/features.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/docs/features.txt b/docs/features.txt
index e786bbecf4..2eac14fb32 100644
--- a/docs/features.txt
+++ b/docs/features.txt
@@ -305,7 +305,7 @@ Khronos, ARB, and OES extensions that a
Signed-off-by: Rhys Perry
---
src/gallium/auxiliary/util/u_framebuffer.c | 30 +++
src/gallium/auxiliary/util/u_framebuffer.h | 5
src/gallium/docs/source/context.rst | 3 +++
src/gallium/docs/source/screen.rst | 3 +++
src/galliu
Signed-off-by: Rhys Perry
---
src/mapi/glapi/gen/gl_API.xml | 104 +
src/mesa/main/config.h | 9 ++
src/mesa/main/dd.h | 9 ++
src/mesa/main/extensions_table.h| 2 +
src/mesa/main/fbobject.c| 256 +++
Signed-off-by: Rhys Perry
---
src/mesa/state_tracker/st_atom.h | 2 +-
src/mesa/state_tracker/st_atom_list.h | 2 +-
src/mesa/state_tracker/st_atom_msaa.c | 77 +-
src/mesa/state_tracker/st_cb_msaa.c| 27
src/mesa/state_tracker/st_context
This patch set adds support for GL_ARB_sample_locations in mesa core, gallium,
the mesa OpenGL state tracker and the nvc0 driver.
Changes in v2:
- various minor changes/cleanups (mostly formatting and style changes)
- improve error handling
- don't expose the ARB_* variant on ES
- expose NV_sample
Signed-off-by: Rhys Perry
---
.../drivers/nouveau/codegen/nv50_ir_driver.h | 2 +
.../drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 7 +
.../nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 91 +--
.../nouveau/codegen/nv50_ir_lowering_nvc0.h| 2 +
src/gallium/drive
From: Marek Olšák
The slot index is always 0, and is pretty unlikely to change in the future.
---
src/gallium/auxiliary/cso_cache/cso_context.c | 52 ++-
src/gallium/auxiliary/cso_cache/cso_context.h | 5 ---
src/gallium/auxiliary/hud/hud_context.c | 14 +++-
s
https://bugs.freedesktop.org/show_bug.cgi?id=106462
Brian Paul changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
Hi Brian,
actually that value appears to be used even, but not for the input to the
information rather than its used for the output of the LOC_CUSTOM code.
Sorry!
I came to the same fix at about the same moment, so:
Reviewed-by: Mathias Fröhlich
best
Matias
On Thursday, 10 May 2018 17:27:42 C
Since size can be 3, 4 or GL_BGRA we need to keep these glGet types
as TYPE_INT, not TYPE_UBYTE.
Fixes: d07466fe18522 ("mesa: fix glGetInteger/Float/etc queries for
vertex arrays attribs")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106462
cc: mesa-sta...@lists.freedesktop.org
---
src/
These are going to be crazy and we are probably going to add
more scan stuff in the future. Also use switch cases instead.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_shader_info.c | 127 +++---
1 file changed, 80 insertions(+), 47 deletions(-)
diff --git a/sr
On Thu, May 10, 2018 at 1:43 AM, Thomas Petazzoni
wrote:
> Hello Matt,
>
> On Wed, 9 May 2018 16:30:12 -0700, Matt Turner wrote:
>
>> Hi Thomas,
>>
>> I rebased this patch on
>>
>> commit 54ba73ef102f7b9085922686bb31719539e0dc3c
>> Author: Nicolas Boichat
>> Date: Thu Apr 5 0
https://bugs.freedesktop.org/show_bug.cgi?id=106462
Bug ID: 106462
Summary: piglit.spec.arb_vertex_array_bgra.get regression
Product: Mesa
Version: git
Hardware: Other
OS: All
Status: NEW
Keywords: bisecte
On Wed, 2018-05-09 at 18:17 +0200, Michel Dänzer wrote:
> On 2018-05-08 09:47 PM, Adam Jackson wrote:
> > dri*_bind_context, when switching current drawables, will drop the
> > reference on the old one; since that refcount has probably now gone to
> > zero that means we lose all the state we applie
Am 10.05.2018 um 16:47 schrieb Ivan Kalvachev:
> On 5/10/18, Roland Scheidegger wrote:
>> Quite a sneaky little bug, can't hurt to make undefined behavior a bit
>> more defined :-).
>
> Actually, this behavior is completely defined in Direct3D,
> where out-of-bound access is expected to
> always
Adds suppport for ARB_fragment_shader_interlock. We achieve
the interlock and fragment ordering by issuing a memory fence
via sendc.
Signed-off-by: Plamena Manolova
---
docs/features.txt| 2 +-
docs/relnotes/18.1.0.html| 1 +
src/intel/compiler/b
This extension provides new GLSL built-in functions
beginInvocationInterlockARB() and endInvocationInterlockARB()
that delimit a critical section of fragment shader code. For
pairs of shader invocations with "overlapping" coverage in a
given pixel, the OpenGL implementation will guarantee that the
On 5/10/18, Roland Scheidegger wrote:
> Quite a sneaky little bug, can't hurt to make undefined behavior a bit
> more defined :-).
Actually, this behavior is completely defined in Direct3D,
where out-of-bound access is expected to
always return 0.0 .
This is why Witcher1 has the issue in both Gal
https://bugs.freedesktop.org/show_bug.cgi?id=106450
Brian Paul changed:
What|Removed |Added
Resolution|--- |FIXED
Status|NEW
https://bugs.freedesktop.org/show_bug.cgi?id=106246
--- Comment #10 from Philip Rebohle ---
I added an initial implementation to a separate branch in DXVK:
https://github.com/doitsujin/dxvk/tree/disable-opt-bit
It currently does not use derivative pipelines (I'll have to re-implement that
at so
https://bugs.freedesktop.org/show_bug.cgi?id=106209
Pavel Ondračka changed:
What|Removed |Added
CC||pavel.ondra...@email.cz
--
You are re
I think this has two issues:
1) We don't properly handles stores, which should be disabled.
2) this could turn a loop which only has a discard as exit into an
infinite loop.
Also have we confirmed that LLVM 6.0+ works correctly?
On Thu, May 10, 2018 at 11:43 AM, Samuel Pitoiset
wrote:
> D3D be
I'm personally fine with this as a temporary solution (correctness vs
performance).
If Bas and Dave also agree, we would need to backport it I think (note
that radv_use_dcc_for_image() is pretty recent and this patch probably
can't be applied to 18.0).
Just one comment below.
On 05/10/2018
D3D behaviour and Vulkan are different. The workaround can
be enabled with RADV_DEBUG=correctderivsafterkill.
When enabled, this fixes rendering issues with DXVK. For
now, I don't want to force-enable this behaviour for DXVK
because having per-app workarounds is a bad idea.
We are probably going
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_shader.h | 1 +
src/amd/vulkan/radv_shader_info.c | 4
2 files changed, 5 insertions(+)
diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index 6588b78772..c28407352a 100644
--- a/src/amd/vulkan/radv_shader.h
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_shader.h | 1 +
src/amd/vulkan/radv_shader_info.c | 31 +++
2 files changed, 32 insertions(+)
diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index c28407352a..f8826f41ef 100644
---
Sometimes it is nice (and useful) to not just see if you've messed up
but also if you've made an improvement.
---
si-report.py | 24
1 file changed, 24 insertions(+)
diff --git a/si-report.py b/si-report.py
index fba652c..d0e0686 100755
--- a/si-report.py
+++ b/si-report
When using sha as part of the captured shader name that name can get so
long that part of it is cut off and not visible anymore (although this
also happens when using long directory names etc.) So this is a general
improvement.
---
si-report.py | 72 ++-
Move shader-cache code from back to front and make generate_sha1() usable
unconditionally to avoid code duplication in the following patch
---
src/mesa/main/shaderapi.c | 228 +++---
1 file changed, 116 insertions(+), 112 deletions(-)
diff --git a/src/mesa
It is inconvenient to capture shaders by program name alone because this does
not allow to capture shaders that get overwritten by shaders with the same
program name (ie games when you change settings or piglit).
---
src/mesa/main/shaderapi.c | 47 ---
remove a memset too and yes, this is all functionally identical
---
src/mesa/main/shaderapi.c | 40
1 file changed, 20 insertions(+), 20 deletions(-)
diff --git a/src/mesa/main/shaderapi.c b/src/mesa/main/shaderapi.c
index e8acca4490..1d0ca5374b 100644
--
When capturing shaders with MESA_SHADER_CAPTURE_PATH, shaders can and will
be overwritten if they have the same program number.
This happens when you're capturing shaders from games especially after
changing graphics settings and piglit shaders (I use that as a convenient way
for testing radeonsi
Implement ir_binop_vector_extract using NIR operations. Based on SPIR-V
to NIR approach.
This fixes:
dEQP-GLES3.functional.shaders.indexing.moredynamic.with_value_from_indexing_expression_fragment
Piglit's glsl-fs-vec4-indexing-8.shader_test
Signed-off-by: Juan A. Suarez Romero
---
Pending to v
Hello Matt,
On Wed, 9 May 2018 16:30:12 -0700, Matt Turner wrote:
> Hi Thomas,
>
> I rebased this patch on
>
> commit 54ba73ef102f7b9085922686bb31719539e0dc3c
> Author: Nicolas Boichat
> Date: Thu Apr 5 09:33:09 2018 +0800
>
> configure.ac/meson.build: Fix -lato
ping
On 25/04/18 12:35, Samuel Iglesias Gonsálvez wrote:
> These two patches are still unreviewed.
>
> Sam
>
>
> On 13/04/18 07:30, Samuel Iglesias Gonsálvez wrote:
>> Hello,
>>
>> This series implements support for doing fp16 <-> fp64 conversions on
>> i965. The PRM says we need to do an interme
On 2018-05-09 18:51:04, Brian Paul wrote:
> The vertex array Size and Stride attributes are now ubyte and short,
> respectively. The glGet code needed to be updated to handle those
> types, but wasn't.
>
> Fixes the new piglit test gl-1.5-get-array-attribs test.
>
> Bugzilla: https://bugs.freede
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