[Mesa-dev] [Bug 54363] Mesa 9.0-devel implementation error: Bad bpp in _mesa_meta_CopyTexSubImage()

https://bugs.freedesktop.org/show_bug.cgi?id=54363 Timothy Arceri changed: What|Removed |Added Status|NEW |NEEDINFO --- Comment #1 from Timothy Ar

[Mesa-dev] [Bug 103078] MATLAB broken with mesa software rendering

https://bugs.freedesktop.org/show_bug.cgi?id=103078 Timothy Arceri changed: What|Removed |Added CC||aidan.wal...@gmail.com --- Comment #14

[Mesa-dev] [Bug 105847] Profile GL3bc is not available on X11GraphicsDevice

https://bugs.freedesktop.org/show_bug.cgi?id=105847 Timothy Arceri changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Mesa-dev] [Bug 105832] radeonsi NIR missing bindless textures support

https://bugs.freedesktop.org/show_bug.cgi?id=105832 Timothy Arceri changed: What|Removed |Added Component|Mesa core |Drivers/Gallium/radeonsi QA Co

Re: [Mesa-dev] [PATCH v1 1/2] egl/android: #ifdef out flink name support

On Tue, May 1, 2018 at 11:20 AM Rob Herring wrote: > On Fri, Apr 27, 2018 at 6:57 AM, Robert Foss wrote: > > From: Rob Herring [snip] > > @@ -1228,20 +1254,31 @@ dri2_initialize_android(_EGLDriver *drv, _EGLDisplay *disp) > > > > dri2_dpy->is_render_node = drmGetNodeTypeFromFd(dri2_dpy->fd)

[Mesa-dev] [Bug 49497] build leaves behind python compiled (.pyc) files

https://bugs.freedesktop.org/show_bug.cgi?id=49497 Timothy Arceri changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Mesa-dev] [Bug 89624] Drivers, Gallium/legacy swrast glDrawPixels differences

https://bugs.freedesktop.org/show_bug.cgi?id=89624 Timothy Arceri changed: What|Removed |Added Component|Other |Drivers/Gallium/llvmpipe -- You are re

[Mesa-dev] [Bug 91691] Missing "gl.pc" file while using Scons for cross-compiling

https://bugs.freedesktop.org/show_bug.cgi?id=91691 Timothy Arceri changed: What|Removed |Added Resolution|--- |WONTFIX Status|NEW

[Mesa-dev] [Bug 106290] meson: missing radeon option in dri-drivers section of meson_options.txt

https://bugs.freedesktop.org/show_bug.cgi?id=106290 charlie changed: What|Removed |Added Resolution|--- |WORKSFORME Status|NEW

Re: [Mesa-dev] [PATCH] egl/android: prevent deadlock in droid_query_buffer_age

Hi Min, On Sat, Apr 28, 2018 at 11:56 AM He, Min wrote: > Hi, Tomasz > On 4/27/2018 5:01 PM, Tomasz Figa wrote: > > Hi Min, > > > > On Fri, Apr 27, 2018 at 11:36 AM Min He wrote: > > > >> To avoid blocking other EGL calls, release the display mutex before > >> calling update_buffers(), which w

Re: [Mesa-dev] [PATCH] [rfc] nir: pass uniform storage instead of shader program

On 01/05/18 11:50, Dave Airlie wrote: From: Dave Airlie Only the asserts were accessing anything, and I'm not sure the value of those is worth preserving, this removes mtypes.h includes from nir which seemed like a laudable goal. I've just pushed a patch that moved these files from src/compil

Re: [Mesa-dev] [PATCH] nir: drop main/compiler.h from nir_lower_samplers*

Reviewed-by: Timothy Arceri On 01/05/18 11:53, Dave Airlie wrote: From: Dave Airlie This include is no longer required. --- src/compiler/nir/nir_lower_samplers.c | 2 -- src/compiler/nir/nir_lower_samplers_as_deref.c | 2 -- 2 files changed, 4 deletions(-) diff --git a/src/compi

[Mesa-dev] [PATCH] radv: set fmask_surf_index on fmask surfaces.

From: Dave Airlie This is needed for gfx9 and later for all fmask surface index. (Mentioned by Marek on irc) --- src/amd/vulkan/radv_image.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index 0d0080ca889..ad4809

Re: [Mesa-dev] [PATCH v1 1/2] egl/android: #ifdef out flink name support

On Fri, Apr 27, 2018 at 6:57 AM, Robert Foss wrote: > From: Rob Herring > > Maintaining both flink names and prime fd support which are provided by > 2 different gralloc implementations is problematic because we have a > dependency on a specific gralloc implementation header. > > This mostly disa

[Mesa-dev] [PATCH] radv: Add support for IMG_DATA_FORMAT_32_32_32.

Basic sampling support for linear tiling. No CTS regressions, but it seems the blitting coverage is not very extensive. --- src/amd/common/ac_surface.c | 4 src/amd/vulkan/radv_formats.c | 10 ++ src/amd/vulkan/radv_meta_copy.c | 1 + 3 files changed, 11 insertions(+), 4 dele

[Mesa-dev] [PATCH] nir: drop main/compiler.h from nir_lower_samplers*

From: Dave Airlie This include is no longer required. --- src/compiler/nir/nir_lower_samplers.c | 2 -- src/compiler/nir/nir_lower_samplers_as_deref.c | 2 -- 2 files changed, 4 deletions(-) diff --git a/src/compiler/nir/nir_lower_samplers.c b/src/compiler/nir/nir_lower_samplers.c ind

[Mesa-dev] [PATCH] [rfc] nir: pass uniform storage instead of shader program

From: Dave Airlie Only the asserts were accessing anything, and I'm not sure the value of those is worth preserving, this removes mtypes.h includes from nir which seemed like a laudable goal. --- src/compiler/nir/nir.h | 8 src/compiler/nir/nir_lower_atomics.c

[Mesa-dev] [RFC PATCH] gallium: add interface for EQAA

From: Marek Olšák This is a hypothetical interface for EQAA (a superset of CSAA). CSAA could be exposed via GL_NV_framebuffer_multisample_coverage. EQAA additionally removes the restriction that the number of samples in all FBO attachments must match, which means it allows arbitrary sample counts

Re: [Mesa-dev] [PATCH 11/13] i965/miptree: Map with movntdqa for linear buffers only

Kenneth Graunke writes: > On Monday, April 30, 2018 10:25:50 AM PDT Scott D Phillips wrote: >> Removes a place where gtt mapping is used. >> >> Reviewed-by: Nanley Chery >> Reviewed-by: Chris Wilson >> --- >> src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 3 ++- >> 1 file changed, 2 insertio

Re: [Mesa-dev] [PATCH v2 00/13] 86 gtt maps

Kenneth Graunke writes: > On Monday, April 30, 2018 10:25:39 AM PDT Scott D Phillips wrote: >> Here is a v2 of the 86 gtt maps series with the refactor >> suggestions by Chris folded in. >> >> Chris Wilson (8): >> i965: Move unmap_gtt before map_gtt >> i965: Move unmap_blit before map_blit >

Re: [Mesa-dev] [PATCH 10/13] i965/miptree: Use cpu tiling/detiling when mapping

Kenneth Graunke writes: > On Monday, April 30, 2018 10:25:49 AM PDT Scott D Phillips wrote: >> Rename the (un)map_gtt functions to (un)map_map (map by >> returning a map) and add new functions (un)map_tiled_memcpy that >> return a shadow buffer populated with the intel_tiled_memcpy >> functions.

Re: [Mesa-dev] [PATCH 09/13] i965/tiled_memcpy: inline movntdqa loads in tiled_to_linear

Matt Turner writes: > On Mon, Apr 30, 2018 at 10:25 AM, Scott D Phillips > wrote: >> The reference for MOVNTDQA says: >> >> For WC memory type, the nontemporal hint may be implemented by >> loading a temporary internal buffer with the equivalent of an >> aligned cache line without fi

Re: [Mesa-dev] [PATCH v2 06/18] intel/compiler: fix brw_imm_w for negative 16-bit integers

On Mon, Apr 30, 2018 at 3:53 PM, Chema Casanova wrote: > > > On 30/04/18 23:12, Jason Ekstrand wrote: > > On Mon, Apr 30, 2018 at 7:18 AM, Iago Toral Quiroga > > wrote: > > > > From: Jose Maria Casanova Crespo > > > > > > 16-bi

Re: [Mesa-dev] [PATCH v2 06/18] intel/compiler: fix brw_imm_w for negative 16-bit integers

On 30/04/18 23:12, Jason Ekstrand wrote: > On Mon, Apr 30, 2018 at 7:18 AM, Iago Toral Quiroga > wrote: > > From: Jose Maria Casanova Crespo > > > 16-bit immediates need to replicate the 16-bit immediate value > in both w

Re: [Mesa-dev] [PATCH 3/5] intel: emit is_indexed_draw in the same VE than gl_DrawID

On Sat, Apr 28, 2018 at 5:09 AM, Antia Puentes wrote: > The Vertex Elements are now: > * VE 1: > * VE 2: > > VE1 is it kept as it was before, VE2 additionally contains the new > system value. > --- > src/intel/compiler/brw_fs_nir.cpp | 2 ++ > src/intel/compiler/brw_nir.c

Re: [Mesa-dev] [PATCH 0/3] common bits from HDR POC

Here's a really dumb question: What good does it do someone to have the extension if no actual window-system HDR is supported? I'm just wondering if we want to only expose the extension if hardware can actually do it. On Sun, Apr 29, 2018 at 11:42 PM, Tapani Pälli wrote: > Hi; > > I took Ville

Re: [Mesa-dev] [PATCH v2 00/13] 86 gtt maps

On Monday, April 30, 2018 10:25:39 AM PDT Scott D Phillips wrote: > Here is a v2 of the 86 gtt maps series with the refactor > suggestions by Chris folded in. > > Chris Wilson (8): > i965: Move unmap_gtt before map_gtt > i965: Move unmap_blit before map_blit > i965: Move unmap_movntdqa befor

Re: [Mesa-dev] [PATCH] radv/winsys: fix leaking resources from bo's imported by fd

Reviewed-by: Bas Nieuwenhuizen On Tue, May 1, 2018 at 12:13 AM, Andres Rodriguez wrote: > A bo's ref_count was not being initialized when imported from an fd. > Therefore, we would fail to free the resource during VkFreeMemory(). > > This patch fixes applications like hifi VR in threaded mode,

Re: [Mesa-dev] [PATCH 02/10] dri_interface: add __DRI_IMAGE_TRANSFER_USER_STRIDE

On Mon, Apr 30, 2018 at 2:38 PM, Marek Olšák wrote: > On Mon, Apr 30, 2018 at 3:11 PM, Eric Anholt wrote: >> >> Marek Olšák writes: >> >> > From: Nicolai Hähnle >> > >> > Allow the caller to specify the row stride (in bytes) with which an >> > image >> > should be mapped. Note that completely i

[Mesa-dev] [PATCH] anv: Don't advertise Float64 or Int64 on HW withou 64-bit types

--- src/intel/vulkan/anv_device.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c index adcd506..e82f294 100644 --- a/src/intel/vulkan/anv_device.c +++ b/src/intel/vulkan/anv_device.c @@ -757,8 +757,10 @@ void

[Mesa-dev] [PATCH] radv/winsys: fix leaking resources from bo's imported by fd

A bo's ref_count was not being initialized when imported from an fd. Therefore, we would fail to free the resource during VkFreeMemory(). This patch fixes applications like hifi VR in threaded mode, which perform frequent imports/releases of IPC shared memory. Signed-off-by: Andres Rodriguez CC:

[Mesa-dev] [PATCH] anv: Advertise variableMultisampleRate

Initially, I didn't understand this feature. Turns out that all it means is that you can switch multisample rates in the middle of a zero-attachment subpass. We've been able to do this since forever. --- src/intel/vulkan/anv_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --

Re: [Mesa-dev] [PATCH 10/13] i965/miptree: Use cpu tiling/detiling when mapping

On Monday, April 30, 2018 10:25:49 AM PDT Scott D Phillips wrote: > Rename the (un)map_gtt functions to (un)map_map (map by > returning a map) and add new functions (un)map_tiled_memcpy that > return a shadow buffer populated with the intel_tiled_memcpy > functions. > > Tiling/detiling with the cp

Re: [Mesa-dev] [PATCH 09/13] i965/tiled_memcpy: inline movntdqa loads in tiled_to_linear

On Mon, Apr 30, 2018 at 10:25 AM, Scott D Phillips wrote: > The reference for MOVNTDQA says: > > For WC memory type, the nontemporal hint may be implemented by > loading a temporary internal buffer with the equivalent of an > aligned cache line without filling this data to the cache. >

Re: [Mesa-dev] [PATCH v2 15/18] intel/compiler: implement 16-bit pack/unpack opcodes

Reviewed-by: Jason Ekstrand On Mon, Apr 30, 2018 at 7:18 AM, Iago Toral Quiroga wrote: > --- > src/intel/compiler/brw_fs_nir.cpp | 10 ++ > 1 file changed, 10 insertions(+) > > diff --git a/src/intel/compiler/brw_fs_nir.cpp > b/src/intel/compiler/brw_fs_nir.cpp > index d590a00385..25e8

Re: [Mesa-dev] [PATCH v2 14/18] compiler/spirv: implement 16-bit bitcasts

Reviewed-by: Jason Ekstrand On Mon, Apr 30, 2018 at 7:18 AM, Iago Toral Quiroga wrote: > --- > src/compiler/spirv/vtn_alu.c | 31 ++- > 1 file changed, 22 insertions(+), 9 deletions(-) > > diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c > in

Re: [Mesa-dev] [PATCH v2 13/18] compiler/lower_64bit_packing: rename the pass to be more generic

Drp... Ignore my comments on 12... Reviewed-by: Jason Ekstrand On Mon, Apr 30, 2018 at 7:18 AM, Iago Toral Quiroga wrote: > It can do 32-bit packing too now. > --- > src/amd/vulkan/radv_shader.c| 2 +- > src/compiler/Makefile.sources

Re: [Mesa-dev] [PATCH v2 12/18] nir/lower_64bit_packing: extend the pass to handle packing from / to 16-bit.

On Mon, Apr 30, 2018 at 7:18 AM, Iago Toral Quiroga wrote: > With 16-bit support we can now do 32-bit packing, a follow-up patch will > rename the pass to something more generic. > --- > src/compiler/nir/nir_lower_64bit_packing.c | 64 > +++--- > 1 file changed, 59 insert

Re: [Mesa-dev] [PATCH v2 11/18] nir: add opcodes for 16-bit packing and unpacking

Reviewed-by: Jason Ekstrand On Mon, Apr 30, 2018 at 7:18 AM, Iago Toral Quiroga wrote: > Noitice that we don't need 'split' versions of the 64-bit to / from > 16-bit opcodes which we require during pack lowering to implement these > operations. This is because these operations can be expressed

[Mesa-dev] [Bug 104302] Wolfenstein 2 (2017) under wine graphical artifacting on RADV

https://bugs.freedesktop.org/show_bug.cgi?id=104302 --- Comment #16 from Matt --- Confirming everything is fixed bar the melting facial animations with Fedora 28, Mesa-git 18.2 and LLVM 7.0 -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the

Re: [Mesa-dev] [PATCH v2 10/18] intel/compiler: fix 16-bit comparisons

On Mon, Apr 30, 2018 at 7:18 AM, Iago Toral Quiroga wrote: > NIR assumes that booleans are always 32-bit, but Intel hardware produces > 16-bit booleans for 16-bit comparisons. This means that we need to convert > the 16-bit result to 32-bit. > > In the future we want to add an optimization pass t

Re: [Mesa-dev] [PATCH 02/10] dri_interface: add __DRI_IMAGE_TRANSFER_USER_STRIDE

On Mon, Apr 30, 2018 at 3:11 PM, Eric Anholt wrote: > Marek Olšák writes: > > > From: Nicolai Hähnle > > > > Allow the caller to specify the row stride (in bytes) with which an image > > should be mapped. Note that completely ignoring USER_STRIDE is a valid > > implementation of mapImage. > > >

Re: [Mesa-dev] [PATCH v2 09/18] intel/compiler: lower some 16-bit integer operations to 32-bit

Reviewed-by: Jason Ekstrand On Mon, Apr 30, 2018 at 7:18 AM, Iago Toral Quiroga wrote: > These are not supported in hardware for 16-bit integers. > > We do the lowering pass after the optimization loop to ensure that we > lower ALU operations injected by algebraic optimizations too. > --- > sr

Re: [Mesa-dev] [PATCH v2 08/18] compiler/nir: add a lowering pass to convert the bit size of ALU operations

On Mon, Apr 30, 2018 at 7:18 AM, Iago Toral Quiroga wrote: > Not all bit-sizes may be supported natively in hardware for all operations. > This pass allows drivers to lower such operations to a bit-size that is > actually supported and then converts the result back to the original > bit-size. > >

Re: [Mesa-dev] [PATCH 10/13] i965/miptree: Use cpu tiling/detiling when mapping

On Monday, April 30, 2018 10:25:49 AM PDT Scott D Phillips wrote: > Rename the (un)map_gtt functions to (un)map_map (map by > returning a map) and add new functions (un)map_tiled_memcpy that > return a shadow buffer populated with the intel_tiled_memcpy > functions. > > Tiling/detiling with the cp

Re: [Mesa-dev] [PATCH v2 07/18] intel/compiler: fix brw_negate_immediate for 16-bit types

On Mon, Apr 30, 2018 at 7:18 AM, Iago Toral Quiroga wrote: > From: Jose Maria Casanova Crespo > > From Intel Skylake PRM, vol 07, "Immediate" section (page 768): > > "For a word, unsigned word, or half-float immediate data, > software must replicate the same 16-bit immediate value to both > the

Re: [Mesa-dev] [PATCH v2 06/18] intel/compiler: fix brw_imm_w for negative 16-bit integers

On Mon, Apr 30, 2018 at 7:18 AM, Iago Toral Quiroga wrote: > From: Jose Maria Casanova Crespo > > 16-bit immediates need to replicate the 16-bit immediate value > in both words of the 32-bit value. This needs to be careful > to avoid sign-extension, which the previous implementation was > not ha

Re: [Mesa-dev] [PATCH 11/13] i965/miptree: Map with movntdqa for linear buffers only

On Monday, April 30, 2018 10:25:50 AM PDT Scott D Phillips wrote: > Removes a place where gtt mapping is used. > > Reviewed-by: Nanley Chery > Reviewed-by: Chris Wilson > --- > src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --gi

Re: [Mesa-dev] [PATCH] nir: Implement optional b2f->iand lowering

On Sun, Apr 29, 2018 at 11:19 AM, Alyssa Rosenzweig wrote: > This pass is required by the Midgard compiler; our instruction set uses > NIR-style booleans (~0 for true) but lacks a dedicated b2f instruction. > Normally, this lowering pass would be implemented in a backend-specific > algebraic pass,

[Mesa-dev] [Bug 106315] The witness + dxvk suffers flickering garbage

https://bugs.freedesktop.org/show_bug.cgi?id=106315 --- Comment #2 from Grazvydas Ignotas --- Created attachment 139237 --> https://bugs.freedesktop.org/attachment.cgi?id=139237&action=edit wine's d3d rendering I no longer have access to the Windows machine, but here's how wine without dxvk bu

Re: [Mesa-dev] [PATCH] Add virgl cap for invariant attrib in tgsi

On 10 April 2018 at 08:01, Joe M. Kniss wrote: > While some support for invariant shader attribute exisits in > tgsi, it was never fully implemented. This patch adds a virgl > cap for this feature in advance of the tgsi invariant implementation > to insure backward compatibility. Current virglre

[Mesa-dev] [Bug 106151] [amdgpu][vulkan] GPU hang (Vega 56) while running game (Rise of the Tomb Raider)

https://bugs.freedesktop.org/show_bug.cgi?id=106151 --- Comment #12 from Martin F --- Hi Samuel. It looks good, no hang here so far. Well done! -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.__

Re: [Mesa-dev] [PATCH] glsl/tests: add GLSL_TYPE_UINT8, GLSL_TYPE_INT8 cases to switch statements

Brian Paul writes: > To silence warnings about unhandled switch values. > Untested otherwise. Maybe this should go down with the unimplemented UINT16 cases? Either way, thanks for cleaning up warnings. Reviewed-by: Eric Anholt signature.asc Description: PGP signature ___

Re: [Mesa-dev] [PATCH 02/10] dri_interface: add __DRI_IMAGE_TRANSFER_USER_STRIDE

Marek Olšák writes: > From: Nicolai Hähnle > > Allow the caller to specify the row stride (in bytes) with which an image > should be mapped. Note that completely ignoring USER_STRIDE is a valid > implementation of mapImage. > > This is horrible API design. Unfortunately, cros_gralloc does indeed

Re: [Mesa-dev] [PATCH 08/13] i965/tiled_memcpy: ytiled_to_linear a cache line at a time

Reviewed-by: Jason Ekstrand On Mon, Apr 30, 2018 at 10:25 AM, Scott D Phillips < scott.d.phill...@intel.com> wrote: > Similar to the transformation applied to linear_to_ytiled, also align > each readback from the ytiled source to a cacheline (i.e. transfer a > whole cacheline from the source bef

Re: [Mesa-dev] [PATCH 2/2] spirv: convert the offset and count operands for bitfield ops to uint32

On Mon, Apr 30, 2018 at 1:46 AM, Samuel Iglesias Gonsálvez < sigles...@igalia.com> wrote: > On 26/04/18 18:14, Jason Ekstrand wrote: > > > > On Thu, Apr 26, 2018 at 2:24 AM, Samuel Iglesias Gonsálvez < > sigles...@igalia.com> wrote: > >> SPIR-V allows to define the shift operand for shift opcodes

[Mesa-dev] [AppVeyor] mesa master #7580 completed

Build mesa 7580 completed Commit bde12f75e1 by Kenneth Graunke on 4/10/2018 11:01 PM: i965: Don't stomp initial kflags for program cache.\n\nWe want to flag EXEC_OBJECT_CAPTURE, but we ought to preserve any\nexisting kflags. Today, there are none (as the progr

[Mesa-dev] [Bug 106151] [amdgpu][vulkan] GPU hang (Vega 56) while running game (Rise of the Tomb Raider)

https://bugs.freedesktop.org/show_bug.cgi?id=106151 --- Comment #11 from Samuel Pitoiset --- Created attachment 139232 --> https://bugs.freedesktop.org/attachment.cgi?id=139232&action=edit patch Guys, can you apply the attached patch and let me know if it improves the situation? -- You are r

Re: [Mesa-dev] [PATCH] swr: Fix include for createInstructionCombiningPass with llvm-7.0.

This patch does not address all the compile issues with llvm trunk (at least the ones that I see in my build). The following patch, however, works: diff --git a/src/gallium/drivers/swr/rasterizer/jitter/JitManager.cpp b/src/gallium/drivers/swr/rasterizer/jitter/JitManager.cpp index aadcca2..efb

Re: [Mesa-dev] [PATCH v3 00/13] TGSI: improved live range tracking, also including arrays

FWIW I'm not really qualified to review this, but this alleviates the concerns I had some time ago about doing spilling for r600 before sb. So this makes all sense to me. Roland Am 28.04.2018 um 21:30 schrieb Gert Wollny: > this is another update of the series I've sent before. > > v3: > - Ad

[Mesa-dev] [PATCH 12/13] i965/miptree: Split miptree_{, un}map logic and state management

From: Chris Wilson Previously the miptree map and unmap functions performed the mapping/unmapping decisions and also tracked the state of maps in the miptree structure for later unmapping. By splitting the logic and state management, a later patch will be able to make recursive use of the map fun

[Mesa-dev] [PATCH 08/13] i965/tiled_memcpy: ytiled_to_linear a cache line at a time

Similar to the transformation applied to linear_to_ytiled, also align each readback from the ytiled source to a cacheline (i.e. transfer a whole cacheline from the source before moving on to the next column). This will allow us to utilize movntqda (_mm_stream_si128) in a subsequent patch to obtain

[Mesa-dev] [PATCH 03/13] i965: Move unmap_movntdqa before map_movntdqa

From: Chris Wilson Reorder code to avoid a forward declaration in the next patch. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 24 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_

[Mesa-dev] [PATCH v2 00/13] 86 gtt maps

Here is a v2 of the 86 gtt maps series with the refactor suggestions by Chris folded in. Chris Wilson (8): i965: Move unmap_gtt before map_gtt i965: Move unmap_blit before map_blit i965: Move unmap_movntdqa before map_movntdqa i965: Move unmap_s8 before map_s8 i965: Move unmap_etc before

[Mesa-dev] [PATCH 10/13] i965/miptree: Use cpu tiling/detiling when mapping

Rename the (un)map_gtt functions to (un)map_map (map by returning a map) and add new functions (un)map_tiled_memcpy that return a shadow buffer populated with the intel_tiled_memcpy functions. Tiling/detiling with the cpu will be the only way to handle Yf/Ys tiling, when support is added for those

[Mesa-dev] [PATCH 06/13] i965: Move unmap_depthstencil before map_depthstencil

From: Chris Wilson Reorder code to avoid a forward declaration in the next patch. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 114 +- 1 file changed, 57 insertions(+), 57 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipm

[Mesa-dev] [PATCH 05/13] i965: Move unmap_etc before map_etc

From: Chris Wilson Reorder code to avoid a forward declaration in the next patch. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 42 +-- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipm

[Mesa-dev] [PATCH 09/13] i965/tiled_memcpy: inline movntdqa loads in tiled_to_linear

The reference for MOVNTDQA says: For WC memory type, the nontemporal hint may be implemented by loading a temporary internal buffer with the equivalent of an aligned cache line without filling this data to the cache. [...] Subsequent MOVNTDQA reads to unread portions of the WC

[Mesa-dev] [PATCH 13/13] i965/miptree: recurse to miptree_map for depth in map_depthstencil

Call back to intel_miptree_map when mapping the separate depth miptree in map_depthstencil. This brings us back to the mapping method decision tree in miptree_map where we will then find the best mapping method for depth. --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 58 -

[Mesa-dev] [PATCH 01/13] i965: Move unmap_gtt before map_gtt

From: Chris Wilson Reorder code to avoid a forward declaration in the next patch. Signed-off-by: Chris Wilson Reviewed-by: Samuel Iglesias Gonsálvez --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mesa/driv

[Mesa-dev] [PATCH 07/13] i965: Record mipmap resolver for unmapping

From: Chris Wilson When mapping a region of the mipmap_tree, record which complementary method to use to unmap it afterwards. By doing so we can avoid duplicating the decision tree used when mapping and thereby eliminate trivial errors that can be introduced if the two if-chains become out of syn

[Mesa-dev] [PATCH 11/13] i965/miptree: Map with movntdqa for linear buffers only

Removes a place where gtt mapping is used. Reviewed-by: Nanley Chery Reviewed-by: Chris Wilson --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel

[Mesa-dev] [PATCH 02/13] i965: Move unmap_blit before map_blit

From: Chris Wilson Reorder code to avoid a forward declaration in the next patch. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 44 +-- 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipm

[Mesa-dev] [PATCH 04/13] i965: Move unmap_s8 before map_s8

From: Chris Wilson Reorder code to avoid a forward declaration in the next patch. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 60 +-- 1 file changed, 30 insertions(+), 30 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipm

Re: [Mesa-dev] [PATCH] tgsi: use enums instead of unsigned in ureg code

Reviewed-by: Charmaine Lee From: Brian Paul Sent: Monday, April 30, 2018 7:42 AM To: mesa-dev@lists.freedesktop.org Cc: Charmaine Lee; Neha Bhende Subject: [PATCH] tgsi: use enums instead of unsigned in ureg code --- src/gallium/auxiliary/tgsi/tgsi_ure

[Mesa-dev] [AppVeyor] mesa 18.1 #7579 failed

Build mesa 7579 failed Commit 7a1f220b26 by Leo Liu on 4/27/2018 12:32 PM: st/omx/enc: fix blit setup for YUV LoadImage\n\nThe blit here involves scaling since it's copying from I8 format to R8G8 format.\nHalf of source will be filtered out with PIPE_TEX_FILTER

Re: [Mesa-dev] [Mesa-stable] [PATCH] st/omx/enc: fix blit setup for YUV LoadImage

On 04/30/2018 12:47 PM, Juan A. Suarez Romero wrote: On Fri, 2018-04-27 at 08:32 -0400, Leo Liu wrote: The blit here involves scaling since it's copying from I8 format to R8G8 format. Half of source will be filtered out with PIPE_TEX_FILTER_NEAREST instruction, it looks that GPU always uses th

Re: [Mesa-dev] [Mesa-stable] [PATCH] st/omx/enc: fix blit setup for YUV LoadImage

On Fri, 2018-04-27 at 08:32 -0400, Leo Liu wrote: > The blit here involves scaling since it's copying from I8 format to R8G8 > format. > Half of source will be filtered out with PIPE_TEX_FILTER_NEAREST instruction, > it > looks that GPU always uses the second half as source. Currently we use "1"

[Mesa-dev] [Bug 106304] glcpp/tests/glcpp-test-cr-lf and glcpp/tests/glcpp-test fail

https://bugs.freedesktop.org/show_bug.cgi?id=106304 Dylan Baker changed: What|Removed |Added Assignee|mesa-dev@lists.freedesktop. |baker.dyla...@gmail.com

[Mesa-dev] [Bug 106290] meson: missing radeon option in dri-drivers section of meson_options.txt

https://bugs.freedesktop.org/show_bug.cgi?id=106290 Dylan Baker changed: What|Removed |Added Status|ASSIGNED|NEW --- Comment #1 from Dylan Baker ---

[Mesa-dev] [AppVeyor] mesa master #7577 completed

Build mesa 7577 completed Commit 1c5f4f4e17 by Leo Liu on 4/27/2018 12:32 PM: st/omx/enc: fix blit setup for YUV LoadImage\n\nThe blit here involves scaling since it's copying from I8 format to R8G8 format.\nHalf of source will be filtered out with PIPE_TEX_FIL

Re: [Mesa-dev] [PATCH] dri3: Only update number of back buffers in loader_dri3_get_buffers

On 27 April 2018 at 16:56, Michel Dänzer wrote: > And only free no longer needed back buffers there as well. > > We want to stick to the same back buffer throughout a frame, otherwise > we can run into various issues. Thanks for dealing with this Michel! Acked-by: Daniel Stone _

[Mesa-dev] [PATCH] glsl/tests: add GLSL_TYPE_UINT8, GLSL_TYPE_INT8 cases to switch statements

To silence warnings about unhandled switch values. Untested otherwise. --- src/compiler/glsl/tests/uniform_initializer_utils.cpp | 6 ++ 1 file changed, 6 insertions(+) diff --git a/src/compiler/glsl/tests/uniform_initializer_utils.cpp b/src/compiler/glsl/tests/uniform_initializer_utils.cpp

[Mesa-dev] [PATCH] tgsi: use enums instead of unsigned in ureg code

--- src/gallium/auxiliary/tgsi/tgsi_ureg.c | 14 +++--- src/gallium/auxiliary/tgsi/tgsi_ureg.h | 10 +- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/src/gallium/auxiliary/tgsi/tgsi_ureg.c b/src/gallium/auxiliary/tgsi/tgsi_ureg.c index 393e015..7d2b9af 100644 --

Re: [Mesa-dev] [PATCH v7 0/4] Implement Various Conservative Rasterization Extensions

On 04/27/2018 11:34 AM, Rhys Perry wrote: This patch-set adds support for GL_NV_conservative_raster and GL_NV_conservative_raster_dilate on GM2xx and newer. It also adds support for GL_NV_conservative_raster_pre_snap_triangles on GP1xx. In doing so, it implements various functions in mesa core,

Re: [Mesa-dev] [PATCH] dri3: Only update number of back buffers in loader_dri3_get_buffers

Hi, On 27.04.2018 18:56, Michel Dänzer wrote: From: Michel Dänzer And only free no longer needed back buffers there as well. We want to stick to the same back buffer throughout a frame, otherwise we can run into various issues. Bugzilla: https://bugs.freedesktop.org/105906 Fixes: 3160cb86aa9

[Mesa-dev] [PATCH v2 18/18] anv/device: expose shaderInt16 support in gen8+

Reviewed-by: Jason Ekstrand --- src/intel/vulkan/anv_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c index b456d3d4c5..d123ae16ec 100644 --- a/src/intel/vulkan/anv_device.c +++ b/src/intel/vulkan/anv_device

[Mesa-dev] [PATCH v2 17/18] anv/pipeline: support SpvCapabilityInt16 in gen8+

Reviewed-by: Jason Ekstrand --- src/intel/vulkan/anv_pipeline.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index 56bea7bf0d..87788de10a 100644 --- a/src/intel/vulkan/anv_pipeline.c +++ b/src/intel/vulkan/anv_pipeline.c @@

[Mesa-dev] [PATCH v2 16/18] compiler/spirv: add implementation to check for SpvCapabilityInt16 support

Reviewed-by: Jason Ekstrand --- src/compiler/shader_info.h| 1 + src/compiler/spirv/spirv_to_nir.c | 4 +++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/src/compiler/shader_info.h b/src/compiler/shader_info.h index 53a0ef21f6..afc53a8840 100644 --- a/src/compiler/shader_

[Mesa-dev] [PATCH v2 14/18] compiler/spirv: implement 16-bit bitcasts

--- src/compiler/spirv/vtn_alu.c | 31 ++- 1 file changed, 22 insertions(+), 9 deletions(-) diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c index 3134849ba9..3708a9dc0c 100644 --- a/src/compiler/spirv/vtn_alu.c +++ b/src/compiler/spirv/vtn_alu.

[Mesa-dev] [PATCH v2 12/18] nir/lower_64bit_packing: extend the pass to handle packing from / to 16-bit.

With 16-bit support we can now do 32-bit packing, a follow-up patch will rename the pass to something more generic. --- src/compiler/nir/nir_lower_64bit_packing.c | 64 +++--- 1 file changed, 59 insertions(+), 5 deletions(-) diff --git a/src/compiler/nir/nir_lower_64bit_pa

[Mesa-dev] [PATCH v2 15/18] intel/compiler: implement 16-bit pack/unpack opcodes

--- src/intel/compiler/brw_fs_nir.cpp | 10 ++ 1 file changed, 10 insertions(+) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index d590a00385..25e85b9b25 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -1313,

[Mesa-dev] [PATCH v2 13/18] compiler/lower_64bit_packing: rename the pass to be more generic

It can do 32-bit packing too now. --- src/amd/vulkan/radv_shader.c| 2 +- src/compiler/Makefile.sources | 2 +- src/compiler/nir/meson.build| 2 +- src/compiler/nir/nir.h

[Mesa-dev] [PATCH v2 11/18] nir: add opcodes for 16-bit packing and unpacking

Noitice that we don't need 'split' versions of the 64-bit to / from 16-bit opcodes which we require during pack lowering to implement these operations. This is because these operations can be expressed as a collection of 32-bit from / to 16-bit and 64-bit to / from 32-bit operations, so we don't ne

[Mesa-dev] [PATCH v2 09/18] intel/compiler: lower some 16-bit integer operations to 32-bit

These are not supported in hardware for 16-bit integers. We do the lowering pass after the optimization loop to ensure that we lower ALU operations injected by algebraic optimizations too. --- src/intel/compiler/brw_nir.c | 21 + 1 file changed, 21 insertions(+) diff --git a/

[Mesa-dev] [PATCH v2 07/18] intel/compiler: fix brw_negate_immediate for 16-bit types

From: Jose Maria Casanova Crespo From Intel Skylake PRM, vol 07, "Immediate" section (page 768): "For a word, unsigned word, or half-float immediate data, software must replicate the same 16-bit immediate value to both the lower word and the high word of the 32-bit immediate field in a GEN instr

[Mesa-dev] [PATCH v2 08/18] compiler/nir: add a lowering pass to convert the bit size of ALU operations

Not all bit-sizes may be supported natively in hardware for all operations. This pass allows drivers to lower such operations to a bit-size that is actually supported and then converts the result back to the original bit-size. Compiler backends control which operations and wich bit-sizes require t

[Mesa-dev] [PATCH v2 10/18] intel/compiler: fix 16-bit comparisons

NIR assumes that booleans are always 32-bit, but Intel hardware produces 16-bit booleans for 16-bit comparisons. This means that we need to convert the 16-bit result to 32-bit. In the future we want to add an optimization pass to clean this up and hopefully remove the conversions. --- src/intel/c

[Mesa-dev] [PATCH v2 06/18] intel/compiler: fix brw_imm_w for negative 16-bit integers

From: Jose Maria Casanova Crespo 16-bit immediates need to replicate the 16-bit immediate value in both words of the 32-bit value. This needs to be careful to avoid sign-extension, which the previous implementation was not handling properly. For example, with the previous implementation, storing

[Mesa-dev] [PATCH v2 05/18] intel/compiler: implement nir_instr_type_load_const for 16-bit constants

From: Jose Maria Casanova Crespo Reviewed-by: Jason Ekstrand --- src/intel/compiler/brw_fs_nir.cpp | 5 + 1 file changed, 5 insertions(+) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 300884de05..b9d8ade4cf 100644 --- a/src/intel/compiler/brw_fs_

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