Re: [Mesa-dev] [PATCH v4 6/6] i965: gl_BaseVertex must be zero for non-indexed draw calls

On Fri, Apr 6, 2018 at 2:53 PM, Ian Romanick wrote: > From: Antia Puentes > > We keep 'firstvertex' as it is and move gl_BaseVertex to the drawID > vertex element. The previous Vertex Elements order was: > > * VE 1: > * VE 2: > > and now it is: > > * VE 1: > * VE 2: > > To move the B

Re: [Mesa-dev] [PATCH v4 5/6] nir: Offset vertex_id by first_vertex instead of base_vertex

The first 5 are Reviewed-by: Jason Ekstrand I meant to just skim and ACK the Vulkan bits but then I did a full review. Oh, well. :-) On Fri, Apr 6, 2018 at 2:53 PM, Ian Romanick wrote: > From: Neil Roberts > > base_vertex will be zero for non-indexed calls and in that case we > need vertex_i

Re: [Mesa-dev] [PATCH v4 4/6] spirv: Lower BaseVertex to FIRST_VERTEX instead of BASE_VERTEX

On Fri, Apr 6, 2018 at 2:53 PM, Ian Romanick wrote: > From: Neil Roberts > > The base vertex in Vulkan is different from GL in that for non-indexed > primitives the value is taken from the firstVertex parameter instead > of being set to zero. This coincides with the new SYSTEM_VALUE_FIRST_VERTEX

Re: [Mesa-dev] [PATCH v3 026/104] nir: Support deref instructions in propagate_invariant

On Fri, Apr 6, 2018 at 4:22 PM, Caio Marcelo de Oliveira Filho < caio.olive...@intel.com> wrote: > > +static nir_variable * > > +intrinsic_get_var(nir_intrinsic_instr *intrin, unsigned i) > > +{ > > + if (nir_intrinsic_infos[intrin->intrinsic].num_variables == 0) > > + return nir_deref_inst

Re: [Mesa-dev] [PATCH v3 023/104] nir/deref: Add a deref cleanup function

On Fri, Apr 6, 2018 at 2:05 PM, Caio Marcelo de Oliveira Filho < caio.olive...@intel.com> wrote: > On Tue, Apr 03, 2018 at 11:32:50AM -0700, Jason Ekstrand wrote: > > Sometimes it's useful for a pass to be able to clean up its own derefs > > instead of waiting for DCE. This little helper makes it

Re: [Mesa-dev] [PATCH v3 022/104] nir: Support deref instructions in lower_indirect_derefs

On Fri, Apr 6, 2018 at 2:23 PM, Caio Marcelo de Oliveira Filho < caio.olive...@intel.com> wrote: > Hi, > > > +static void > > +emit_load_store_deref(nir_builder *b, nir_intrinsic_instr *orig_instr, > > + nir_deref_instr *parent, > > + nir_deref_instr **der

Re: [Mesa-dev] [PATCH v3 024/104] nir: Support deref instructions in lower_system_values

On Fri, Apr 6, 2018 at 2:47 PM, Caio Marcelo de Oliveira Filho < caio.olive...@intel.com> wrote: > On Tue, Apr 03, 2018 at 11:32:51AM -0700, Jason Ekstrand wrote: > > --- > > src/compiler/nir/nir_lower_system_values.c | 13 ++--- > > 1 file changed, 10 insertions(+), 3 deletions(-) > > >

Re: [Mesa-dev] [PATCH v3 016/104] nir: Use nir_builder in lower_io_to_temporaries

On Fri, Apr 6, 2018 at 2:51 PM, Caio Marcelo de Oliveira Filho < caio.olive...@intel.com> wrote: > On Tue, Apr 03, 2018 at 11:32:43AM -0700, Jason Ekstrand wrote: > > --- > > src/compiler/nir/nir_lower_io_to_temporaries.c | 37 > -- > > 1 file changed, 17 insertions(+), 20

[Mesa-dev] [PATCH 1/3] radeonsi: implement mechanism for IBs without partial flushes at the end (v6)

From: Marek Olšák (This patch doesn't enable the behavior. It will be enabled in a later commit.) Draw calls from multiple IBs can be executed in parallel. v2: do emit partial flushes on SI v3: invalidate all shader caches at the beginning of IBs v4: don't call si_emit_cache_flush in si_flush_g

[Mesa-dev] [PATCH 2/3] winsys/amdgpu: always set AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE

From: Marek Olšák There is a kernel patch that adds the new flag. Reviewed-by: Samuel Pitoiset --- src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 36 ++- 1 file changed, 26 insertions(+), 10 deletions(-) diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c b/src/ga

[Mesa-dev] [PATCH 3/3] radeonsi: don't emit partial flushes for internal CS flushes only

From: Marek Olšák --- src/gallium/drivers/radeonsi/si_buffer.c| 6 +++--- src/gallium/drivers/radeonsi/si_dma_cs.c| 2 +- src/gallium/drivers/radeonsi/si_fence.c | 5 - src/gallium/drivers/radeonsi/si_gfx_cs.c| 4 ++-- src/gallium/drivers/radeonsi/si_pipe.

[Mesa-dev] [PATCH] radeonsi: don't emit partial flushes at the end of IBs for internal flushes (v5)

From: Marek Olšák Now draw calls from multiple IBs can be executed in parallel. v2: do emit partial flushes on SI v3: invalidate all shader caches at the beginning of IBs v4: squash with the AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE change, don't call si_emit_cache_flush in si_flush_gfx_cs if not

[Mesa-dev] [PATCH] radeonsi: don't emit partial flushes at the end of IBs for internal flushes (v4)

From: Marek Olšák Now draw calls from multiple IBs can be executed in parallel. v2: do emit partial flushes on SI v3: invalidate all shader caches at the beginning of IBs v4: squash with the AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE change, don't call si_emit_cache_flush in si_flush_gfx_cs if not

[Mesa-dev] [PATCH] intel: aubinator: print out addresses of invalid instructions

Signed-off-by: Lionel Landwerlin --- src/intel/tools/gen_batch_decoder.c | 22 +- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/src/intel/tools/gen_batch_decoder.c b/src/intel/tools/gen_batch_decoder.c index 1a8794c84e7..b56aea53f1d 100644 --- a/src/intel/too

Re: [Mesa-dev] [PATCH 04/11] gallium: Use Array._DrawVAO in st_atom_array.c.

So interleaved attribs are unsupported, right? is_interleaved_arrays was probably slowing things down, so I'm OK with that. Marek On Sun, Apr 1, 2018 at 2:13 PM, wrote: > From: Mathias Fröhlich > > Finally make use of the binding information in the VAO when > setting up arrays for draw. > > S

Re: [Mesa-dev] [PATCH v3 026/104] nir: Support deref instructions in propagate_invariant

> +static nir_variable * > +intrinsic_get_var(nir_intrinsic_instr *intrin, unsigned i) > +{ > + if (nir_intrinsic_infos[intrin->intrinsic].num_variables == 0) > + return nir_deref_instr_get_variable(nir_src_as_deref(intrin->src[i])); > + else > + return intrin->variables[0]->var; Sho

[Mesa-dev] [Bug 105846] Assertion failure @ st_atom_array.c:675 when playing Natural Selection 2

https://bugs.freedesktop.org/show_bug.cgi?id=105846 --- Comment #12 from l...@protonmail.ch --- Just crashed with MESA_VERBOSE=all and MESA_DEBUG=context, but I got a nice error message: Mesa: User error: GL_INVALID_OPERATION in glVertexAttribPointer(non-VBO array) ns2_linux: ../src/mesa/state_tra

[Mesa-dev] [Bug 105932] OpenGL scene corrupt using VMware driver

https://bugs.freedesktop.org/show_bug.cgi?id=105932 Logan McNaughton changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Mesa-dev] [PATCH v4 2/6] intel/compiler: Add a uses_firstvertex flag

From: Neil Roberts Reviewed-by: Kenneth Graunke --- src/intel/compiler/brw_compiler.h | 1 + src/intel/compiler/brw_vec4.cpp | 4 2 files changed, 5 insertions(+) diff --git a/src/intel/compiler/brw_compiler.h b/src/intel/compiler/brw_compiler.h index d3ae6499b91..ffcf577d3d1 100644 --

[Mesa-dev] [PATCH v4 1/6] compiler: Add SYSTEM_VALUE_FIRST_VERTEX and instrinsics

From: Antia Puentes This VS system value will contain the value passed as for indexed draw calls or the value passed as for non-indexed draw calls. It can be used to calculate the gl_VertexID as SYSTEM_VALUE_VERTEX_ID_ZERO_BASE plus SYSTEM_VALUE_FIRST_VERTEX. From the OpenGL 4.6 spec, 10.4 "Dr

[Mesa-dev] [PATCH v4 3/6] intel: Handle firstvertex in an identical way to BaseVertex

From: Antia Puentes Until we set gl_BaseVertex to zero for non-indexed draw calls both have an identical value. The Vertex Elements are kept like that: * VE 1: * VE 2: v2 (idr): Mark nir_intrinsic_load_first_vertex as "unreachable" in emit_system_values_block and fs_visitor::nir_emit_vs_intri

[Mesa-dev] [PATCH v4 6/6] i965: gl_BaseVertex must be zero for non-indexed draw calls

From: Antia Puentes We keep 'firstvertex' as it is and move gl_BaseVertex to the drawID vertex element. The previous Vertex Elements order was: * VE 1: * VE 2: and now it is: * VE 1: * VE 2: To move the BaseVertex keeping VE1 as it is, allows to keep pointing the vertex buffer ass

[Mesa-dev] [PATCH v4 4/6] spirv: Lower BaseVertex to FIRST_VERTEX instead of BASE_VERTEX

From: Neil Roberts The base vertex in Vulkan is different from GL in that for non-indexed primitives the value is taken from the firstVertex parameter instead of being set to zero. This coincides with the new SYSTEM_VALUE_FIRST_VERTEX instead of BASE_VERTEX. Reviewed-by: Ian Romanick --- src/c

[Mesa-dev] [PATCH v4 5/6] nir: Offset vertex_id by first_vertex instead of base_vertex

From: Neil Roberts base_vertex will be zero for non-indexed calls and in that case we need vertex_id to be offset by the ‘first’ parameter instead. That is what we get with first_vertex. This is true for both GL and Vulkan. The freedreno driver is also setting vertex_id_zero_based on nir_options

Re: [Mesa-dev] [PATCH v3 016/104] nir: Use nir_builder in lower_io_to_temporaries

On Tue, Apr 03, 2018 at 11:32:43AM -0700, Jason Ekstrand wrote: > --- > src/compiler/nir/nir_lower_io_to_temporaries.c | 37 > -- > 1 file changed, 17 insertions(+), 20 deletions(-) This one could land before the rest of the series. Reviewed-by: Caio Marcelo de Oliveira

Re: [Mesa-dev] [PATCH v3 024/104] nir: Support deref instructions in lower_system_values

On Tue, Apr 03, 2018 at 11:32:51AM -0700, Jason Ekstrand wrote: > --- > src/compiler/nir/nir_lower_system_values.c | 13 ++--- > 1 file changed, 10 insertions(+), 3 deletions(-) > > diff --git a/src/compiler/nir/nir_lower_system_values.c > b/src/compiler/nir/nir_lower_system_values.c > i

[Mesa-dev] [PATCH] st/nine: Do not use scratch for face register

Scratch registers are reused every instructions. Since vFace is reused, a new temporary register should be used. Fixes: https://github.com/iXit/Mesa-3D/issues/311 Signed-off-by: Axel Davy CC: "17.3 18.0" --- src/gallium/state_trackers/nine/nine_shader.c | 2 +- 1 file changed, 1 insertion(+),

[Mesa-dev] [Bug 105846] Assertion failure @ st_atom_array.c:675 when playing Natural Selection 2

https://bugs.freedesktop.org/show_bug.cgi?id=105846 --- Comment #11 from l...@protonmail.ch --- (In reply to Timothy Arceri from comment #5) > (In reply to las from comment #2) > > link to coredump (also uploading as attachment): > > https://doc-0o-4k-docs.googleusercontent.com/docs/securesc/ > >

Re: [Mesa-dev] [PATCH v2] meson: fix warnings about comparing unlike types

> v2: - Use dependency('', required : false) instead of > declare_dependency(), the later will always report that it is > found, which is not what we want. > > Signed-off-by: Dylan Baker > --- > meson.build | 89 > --- > src/

[Mesa-dev] [Bug 105846] Assertion failure @ st_atom_array.c:675 when playing Natural Selection 2

https://bugs.freedesktop.org/show_bug.cgi?id=105846 --- Comment #10 from l...@protonmail.ch --- Seems like it's not mesa_glthread causing it. It just happened again with mesa_glthread=false. -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the

Re: [Mesa-dev] [PATCH v3 022/104] nir: Support deref instructions in lower_indirect_derefs

Hi, > +static void > +emit_load_store_deref(nir_builder *b, nir_intrinsic_instr *orig_instr, > + nir_deref_instr *parent, > + nir_deref_instr **deref_arr, > + nir_ssa_def **dest, nir_ssa_def *src) > +{ > + for (; *deref_arr; deref_ar

[Mesa-dev] [PATCH v2] meson: fix warnings about comparing unlike types

In the old days (0.42.x), when mesa's meson system was written the recommendation for handling conditional dependencies was to define them as empty lists. When meson would evaluate the dependencies of a target it would recursively flatten all of the arguments, and empty lists would be removed. Ther

Re: [Mesa-dev] [PATCH v3 023/104] nir/deref: Add a deref cleanup function

On Tue, Apr 03, 2018 at 11:32:50AM -0700, Jason Ekstrand wrote: > Sometimes it's useful for a pass to be able to clean up its own derefs > instead of waiting for DCE. This little helper makes it very easy. > --- > src/compiler/nir/nir.h | 2 ++ > src/compiler/nir/nir_deref.c | 13 +

Re: [Mesa-dev] [Mesa-stable] [PATCH] radeon/vce: move feedback command inside of destroy function

On 04/04/2018 11:30 AM, Mark Janes wrote: > Emil Velikov writes: > >> On 4 April 2018 at 17:40, Mark Janes wrote: >>> Leo Liu writes: >>> On the CI family, firmware requires the destory command have to be the last command in the IB, moving feedback command after destroy is causing >>>

[Mesa-dev] [Bug 105871] Discolored KDE panels after updating to Mesa 18.0 on Intel broadwell

https://bugs.freedesktop.org/show_bug.cgi?id=105871 --- Comment #21 from Alexey Min --- (In reply to Tapani Pälli from comment #20) > Problem is that kwin_x11 cannot easily avoid this because there is only one > 32bit visual exposed and without the patch mentioned in bug #103699 it > always has s

[Mesa-dev] [Bug 105932] OpenGL scene corrupt using VMware driver

https://bugs.freedesktop.org/show_bug.cgi?id=105932 Bug ID: 105932 Summary: OpenGL scene corrupt using VMware driver Product: Mesa Version: 17.2 Hardware: Other OS: All Status: NEW Severity: normal

[Mesa-dev] [Bug 94957] dEQP failures on llvmpipe

https://bugs.freedesktop.org/show_bug.cgi?id=94957 --- Comment #11 from Roland Scheidegger --- (In reply to msdhedhi007 from comment #10) > I am also seeing this same issue on Mesa 17.3.6. I wanted to know if there > is an update /patch available for this issue. There is no goal as such to pass

Re: [Mesa-dev] [Mesa-stable] [PATCH] radeon/vce: move feedback command inside of destroy function

Emil Velikov writes: > (Dropping Leo, since it doesn't affect him. He's already subscribed to > the list.) > > On 6 April 2018 at 19:20, Mark Janes wrote: > >> I agree with you, however our release process still has a gap. We >> (Intel) test commits on master, and file bugs when we find them in

Re: [Mesa-dev] [Mesa-stable] [PATCH] radeon/vce: move feedback command inside of destroy function

(Dropping Leo, since it doesn't affect him. He's already subscribed to the list.) On 6 April 2018 at 19:20, Mark Janes wrote: > I agree with you, however our release process still has a gap. We > (Intel) test commits on master, and file bugs when we find them in i965 > or other components. > >

Re: [Mesa-dev] [PATCH] RFC: Externd IMG_context_priority with NV_context_priority_realtime

On 18-03-31 12:00:16, Chris Wilson wrote: Quoting Kenneth Graunke (2018-03-30 19:20:57) On Friday, March 30, 2018 7:40:13 AM PDT Chris Wilson wrote: > For i915, we are proposing to use a quality-of-service parameter in > addition to that of just a priority that usurps everyone. Due to our HW, >

Re: [Mesa-dev] [PATCH 3/3] egl/x11: Handle both depth 30 formats for eglCreateImage().

On 04/06/2018 06:41 PM, Michel Dänzer wrote: On 2018-04-06 06:18 PM, Mario Kleiner wrote: On Fri, Apr 6, 2018 at 12:01 PM, Michel Dänzer wrote: On 2018-03-27 07:53 PM, Daniel Stone wrote: On 12 March 2018 at 20:45, Mario Kleiner wrote: We need to distinguish if a backing pixmap of a window

[Mesa-dev] [Bug 105904] Needed to delete mesa shader cache after driver upgrade for 32 bit wine vulkan programs to work.

https://bugs.freedesktop.org/show_bug.cgi?id=105904 --- Comment #2 from Snubb --- I'm sorry but I can't be more specific than that the game "World of tanks" that i've been playing didn't start after driver update, no window. Nothing. When It didn't start I tried to run 64 bit cube.exe from LunarG

[Mesa-dev] [Bug 94957] dEQP failures on llvmpipe

https://bugs.freedesktop.org/show_bug.cgi?id=94957 --- Comment #10 from msdhedhi...@gmail.com --- I am also seeing this same issue on Mesa 17.3.6. I wanted to know if there is an update /patch available for this issue. Thanks. -- You are receiving this mail because: You are the assignee for the

Re: [Mesa-dev] [Mesa-stable] [PATCH] radeon/vce: move feedback command inside of destroy function

Emil Velikov writes: > On 5 April 2018 at 20:33, Mark Janes wrote: >> Emil Velikov writes: >> >>> On 4 April 2018 at 22:50, Mark Janes wrote: Leo Liu writes: > On 04/04/2018 12:40 PM, Mark Janes wrote: >> Leo Liu writes: >> >>> On the CI family, firmware requires th

Re: [Mesa-dev] [PATCH] dri3: Prevent multiple freeing of buffers.

Hi, On 04/06/2018 04:51 PM, Daniel Stone wrote: Hi Sergii, On 6 April 2018 at 09:12, Sergii Romantsov wrote: Commit 3160cb86aa92 adds optimization with flag 'reallocate'. Processing of flag causes buffers freeing while pointer is still hold in caller stack and than again used to be freed. Th

Re: [Mesa-dev] Nouveau driver problem when using EGL_LINUX_DMA_BUF_EXT

Is the dma buf backed by a GEM object? In nouveau_screen_bo_from_handle, we assume that it's a PRIME handle, and look up the associated GEM object. https://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/nouveau/nouveau_screen.c#n90 https://cgit.freedesktop.org/mesa/drm/tree/nouveau/nouvea

Re: [Mesa-dev] [Mesa-stable] [PATCH] radeon/vce: move feedback command inside of destroy function

On 5 April 2018 at 20:33, Mark Janes wrote: > Emil Velikov writes: > >> On 4 April 2018 at 22:50, Mark Janes wrote: >>> Leo Liu writes: >>> On 04/04/2018 12:40 PM, Mark Janes wrote: > Leo Liu writes: > >> On the CI family, firmware requires the destory command have to be the >

[Mesa-dev] Nouveau driver problem when using EGL_LINUX_DMA_BUF_EXT

Not sure if this is the right mailing list, or if the problem may belong to the libdrm part. I'm currently trying to import a DMABUF from V4L2 UVC source (using VIDIOC_EXPBUF) into OpenGL using EGL_LINUX_DMA_BUF_EXT. While this is working fine with the i915 driver it fails with the Nouveau drive

[Mesa-dev] [PATCH 1/8] radv: add radv_get_cmask_fast_clear_value() helper

DCC for MSAA textures are currently unsupported but that will be used later on. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_meta_clear.c | 23 ++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_m

[Mesa-dev] [PATCH 6/8] radv: rename radv_image_is_tc_compat_htile()

... to radv_use_tc_compat_htile_for_image(). This function name makes more sense to me because we want to know if and only if TC-compat HTILE should be used. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_image.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/s

[Mesa-dev] [PATCH 5/8] radv: simplify a check in radv_initialise_color_surface()

If the image has FMASK metadata, the number of samples is > 1 because radv_image_can_enable_fmask() handles that already. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vul

[Mesa-dev] [PATCH 7/8] radv: add radv_use_dcc_for_image() helper

And add some TODOs. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_image.c | 98 +++-- 1 file changed, 68 insertions(+), 30 deletions(-) diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index dc4781231d9..86d97ff83bf 100644 -

[Mesa-dev] [PATCH 0/8] radv: some cleanups & preliminary work for DCC MSAA

Hi, This small series is a preliminary work before doing some improvements in the DCC/CMASK/FMASK codepaths. What I plan to do is: - implement DCC for MSAA textures (I have a WIP branch) - implement TC-compatible CMASK - implement DCC for mipmaps and arrays And probably some other improvements/c

[Mesa-dev] [PATCH 4/8] radv: clean up radv_vi_dcc_enabled()

And rename to radv_dcc_enabled() to be consistent. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_device.c | 2 +- src/amd/vulkan/radv_image.c | 2 +- src/amd/vulkan/radv_private.h | 16 ++-- 3 files changed, 12 insertions(+), 8 deletions(-) diff --git a/src/amd/vulkan/

[Mesa-dev] [PATCH 3/8] radv: clean up radv_htile_enabled()

Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_private.h | 15 +-- 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 4847afc7424..fbdaa7d1601 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/am

[Mesa-dev] [PATCH 8/8] radv: add radv_image_is_tc_compat_htile() helper

Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_device.c | 10 +- src/amd/vulkan/radv_image.c | 10 +- src/amd/vulkan/radv_meta_clear.c | 2 +- src/amd/vulkan/radv_meta_copy.c | 2 +- src/amd/vulkan/radv_private.h| 9 + 5 files changed, 21 insertion

[Mesa-dev] [PATCH 2/8] radv: add radv_image_has_{cmask, fmask, dcc, htile}() helpers

Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_cmd_buffer.c | 18 +- src/amd/vulkan/radv_device.c | 10 +- src/amd/vulkan/radv_image.c | 14 +++--- src/amd/vulkan/radv_meta_clear.c | 12 ++-- src/amd/vulkan/radv_meta_cop

Re: [Mesa-dev] [PATCH] mesa: Assert base format before truncating to unsigned short

Reviewed-by: Marek Olšák Marek On Fri, Apr 6, 2018 at 10:26 AM, Topi Pohjolainen < topi.pohjolai...@gmail.com> wrote: > CID: 1433709 > Fixes: ca721b3d8: mesa: use GLenum16 in a few more places > CC: Marek Olšák > CC: Brian Paul > > Signed-off-by: Topi Pohjolainen > --- > src/mesa/main/texim

Re: [Mesa-dev] [PATCH] nir: rename variables in nir_lower_io_to_temporaries for clarity

On Wed, Apr 4, 2018 at 4:16 PM, Caio Marcelo de Oliveira Filho < caio.olive...@intel.com> wrote: > In the emit_copies() function, the use of "newv" and "temp" names made > sense when only copies from temporaries to the new variables were > being done. But now there are other calls to copy with oth

Re: [Mesa-dev] [PATCH 17/17] winsys/amdgpu: always set AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE

On Fri, Apr 6, 2018 at 3:05 AM, Samuel Pitoiset wrote: > > > On 04/05/2018 10:54 PM, Marek Olšák wrote: > >> On Thu, Apr 5, 2018 at 4:22 AM, Samuel Pitoiset < >> samuel.pitoi...@gmail.com > wrote: >> >> Patches 16-17 are: >> >> Reviewed-by: Samuel Pitoise

Re: [Mesa-dev] [PATCH 02/17] ac/surface: don't set the display flag for obviously unsupported cases

On Fri, Apr 6, 2018 at 11:41 AM, Michel Dänzer wrote: > On 2018-04-06 03:25 PM, Marek Olšák wrote: > > On Thu, Apr 5, 2018, 3:09 AM Michel Dänzer wrote: > >> On 2018-04-04 07:35 PM, Marek Olšák wrote: > >>> On Wed, Apr 4, 2018 at 9:01 AM, Michel Dänzer > >> wrote: > On 2018-04-04 02:57 PM,

[Mesa-dev] [PATCH 1/4] ac/surface: don't set the display flag for obviously unsupported cases (v2)

From: Marek Olšák This enables the tile swizzle for some cases of the displayable micro mode, and it also fixes an addrlib assertion failure on Vega. --- src/amd/common/ac_surface.c| 34 +++--- src/amd/common/ac_surface.h| 1 + src/amd

[Mesa-dev] [PATCH 2/4] radeonsi: make sure CP DMA is idle at the end of IBs

From: Marek Olšák --- src/gallium/drivers/radeonsi/si_cp_dma.c | 12 +++- src/gallium/drivers/radeonsi/si_gfx_cs.c | 5 - src/gallium/drivers/radeonsi/si_pipe.h | 1 + 3 files changed, 16 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_cp_dma.c b/src/

[Mesa-dev] [PATCH 4/4] radeonsi: relax DCC format compatibility contraints

From: Marek Olšák The swizzle has no effect on DCC encoding. --- src/gallium/drivers/radeonsi/si_texture.c | 10 ++ 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c index 5a29624f1fa..1f0d

[Mesa-dev] [PATCH 3/4] radeonsi: add shader binary padding for UMR

From: Marek Olšák --- src/gallium/drivers/radeonsi/si_shader.c | 18 +++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index c18915488e5..8c62d53e2ad 100644 --- a/src/gallium/driv

Re: [Mesa-dev] [PATCH 3/3] egl/x11: Handle both depth 30 formats for eglCreateImage().

On 2018-04-06 06:18 PM, Mario Kleiner wrote: > On Fri, Apr 6, 2018 at 12:01 PM, Michel Dänzer wrote: >> On 2018-03-27 07:53 PM, Daniel Stone wrote: >>> On 12 March 2018 at 20:45, Mario Kleiner wrote: We need to distinguish if a backing pixmap of a window is XRGB2101010 or XBGR2101010, a

Re: [Mesa-dev] [PATCH 3/3] egl/x11: Handle both depth 30 formats for eglCreateImage().

On Fri, Apr 6, 2018 at 12:01 PM, Michel Dänzer wrote: > On 2018-03-27 07:53 PM, Daniel Stone wrote: >> On 12 March 2018 at 20:45, Mario Kleiner wrote: >>> We need to distinguish if a backing pixmap of a window is >>> XRGB2101010 or XBGR2101010, as different gpu hw supports >>> different formats.

[Mesa-dev] [Bug 105871] Discolored KDE panels after updating to Mesa 18.0 on Intel broadwell

https://bugs.freedesktop.org/show_bug.cgi?id=105871 --- Comment #20 from Tapani Pälli --- (In reply to Alexey Min from comment #18) > (In reply to Tasev from comment #16) > > (In reply to sergio.callegari from comment #13) > > > As an alternate/complement solution to the patched xserver-xorg-core

Re: [Mesa-dev] [PATCH] i965/miptree: Initialize mcs buffer only until clear color

On Fri, Apr 06, 2018 at 08:53:39AM -0700, Jason Ekstrand wrote: > On Fri, Apr 6, 2018 at 8:22 AM, Rafael Antognolli < > rafael.antogno...@intel.com> wrote: > > > On Fri, Apr 06, 2018 at 06:07:52PM +0300, Topi Pohjolainen wrote: > > > Otherwise even the clear color gets initialised to 0xFF. This >

Re: [Mesa-dev] [PATCH v3 019/104] nir: Support deref instructions in lower_var_copies

On Thu, Apr 05, 2018 at 01:53:46PM -0700, Jason Ekstrand wrote: > On Thu, Apr 5, 2018 at 12:55 PM, Caio Marcelo de Oliveira Filho < > caio.olive...@intel.com> wrote: > > > Hello, > > > > > +static nir_deref_instr * > > > +build_deref_to_next_wildcard(nir_builder *b, > > > +

[Mesa-dev] [Bug 105846] Assertion failure @ st_atom_array.c:675 when playing Natural Selection 2

https://bugs.freedesktop.org/show_bug.cgi?id=105846 --- Comment #9 from l...@protonmail.ch --- NVM it just happened again, exact same error too. -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.__

Re: [Mesa-dev] [PATCH] i965/miptree: Initialize mcs buffer only until clear color

On Fri, Apr 6, 2018 at 8:22 AM, Rafael Antognolli < rafael.antogno...@intel.com> wrote: > On Fri, Apr 06, 2018 at 06:07:52PM +0300, Topi Pohjolainen wrote: > > Otherwise even the clear color gets initialised to 0xFF. This > > allows enabling of color fast clears on ICL without regressing > > multi

Re: [Mesa-dev] [PATCH 02/17] ac/surface: don't set the display flag for obviously unsupported cases

On 2018-04-06 03:25 PM, Marek Olšák wrote: > On Thu, Apr 5, 2018, 3:09 AM Michel Dänzer wrote: >> On 2018-04-04 07:35 PM, Marek Olšák wrote: >>> On Wed, Apr 4, 2018 at 9:01 AM, Michel Dänzer >> wrote: On 2018-04-04 02:57 PM, Marek Olšák wrote: > On Wed, Apr 4, 2018, 6:18 AM Michel Dänzer

Re: [Mesa-dev] [PATCH] i965/miptree: Initialize mcs buffer only until clear color

On Fri, Apr 06, 2018 at 06:07:52PM +0300, Topi Pohjolainen wrote: > Otherwise even the clear color gets initialised to 0xFF. This > allows enabling of color fast clears on ICL without regressing > multisampling tests. > > CC: Rafael Antognolli > CC: Jason Ekstrand > CC: Nanley Chery > Signed-of

[Mesa-dev] [Bug 105871] Discolored KDE panels after updating to Mesa 18.0 on Intel broadwell

https://bugs.freedesktop.org/show_bug.cgi?id=105871 Alexey Min changed: What|Removed |Added CC||alexey@gmail.com -- You are receiving

[Mesa-dev] [PATCH] i965/miptree: Initialize mcs buffer only until clear color

Otherwise even the clear color gets initialised to 0xFF. This allows enabling of color fast clears on ICL without regressing multisampling tests. CC: Rafael Antognolli CC: Jason Ekstrand CC: Nanley Chery Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 7 +++

Re: [Mesa-dev] [PATCH] dri3: Prevent multiple freeing of buffers.

Hi Sergii, On 6 April 2018 at 09:12, Sergii Romantsov wrote: > Commit 3160cb86aa92 adds optimization with flag 'reallocate'. > Processing of flag causes buffers freeing while pointer > is still hold in caller stack and than again used to be freed. Thanks a lot for writing this. I take it the cor

Re: [Mesa-dev] [PATCH v3 000/104] nir: Move to using instructions for derefs

On Tue, Apr 3, 2018 at 2:32 PM, Jason Ekstrand wrote: > This is something that Connor and I have been talking about for some time > now. The basic idea is to replace the current singly linked nir_deref list > with deref instructions. This is similar to what LLVM does and it offers > quite a bit

[Mesa-dev] [Bug 105871] Discolored KDE panels after updating to Mesa 18.0 on Intel broadwell

https://bugs.freedesktop.org/show_bug.cgi?id=105871 --- Comment #19 from Tasev --- (In reply to Alexey Min from comment #18) > (In reply to Tasev from comment #16) > > (In reply to sergio.callegari from comment #13) > > > As an alternate/complement solution to the patched xserver-xorg-core on >

Re: [Mesa-dev] [PATCH v2 0/3] mesa/i965: Add support for INTEL_blackhole_render

I should have added the branch where you can check this out : https://github.com/djdeath/mesa/tree/wip/intel-blackhole-render Thanks! On 06/04/18 15:31, Lionel Landwerlin wrote: Hi all, This is an update after Emil's feedback and a different implementation in i965. Cheers, Lionel Landwerlin

[Mesa-dev] [PATCH v2 0/3] mesa/i965: Add support for INTEL_blackhole_render

Hi all, This is an update after Emil's feedback and a different implementation in i965. Cheers, Lionel Landwerlin (3): include: bump GL/GLES headers & registry mesa: add INTEL_blackhole_render i965: enable INTEL_blackhole_render include/GL/glcorearb.h | 52 +- inc

[Mesa-dev] [PATCH v2 3/3] i965: enable INTEL_blackhole_render

v2: condition the extension on context isolation support from the kernel (Chris) v3: (Lionel) The initial version of this change used a feature of the Gen7+ command parser to turn the primitive instructions into no-ops. Unfortunately this doesn't play well with how we're using the

[Mesa-dev] [PATCH v2 2/3] mesa: add INTEL_blackhole_render

v2: Implement missing Enable/Disable (Emil) Signed-off-by: Lionel Landwerlin --- src/mesa/main/clear.c| 2 +- src/mesa/main/enable.c | 14 ++ src/mesa/main/extensions_table.h | 1 + src/mesa/main/mtypes.h | 7 +++ 4 files changed, 23 insertions(

[Mesa-dev] [PATCH] mesa: Assert base format before truncating to unsigned short

CID: 1433709 Fixes: ca721b3d8: mesa: use GLenum16 in a few more places CC: Marek Olšák CC: Brian Paul Signed-off-by: Topi Pohjolainen --- src/mesa/main/teximage.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c index

Re: [Mesa-dev] [RFC] - Rewrite mesa website in Sphinx

On Fri, Apr 6, 2018 at 8:30 AM, Emil Velikov wrote: > On 6 April 2018 at 10:40, Daniel Stone wrote: >> Hi all, >> >> On 5 April 2018 at 23:55, Laura Ekstrand wrote: >>> So I spoke with Daniel Stone today about the infrastructure. He estimates >>> it will be ready to deploy the website in 2-3 we

[Mesa-dev] Mesa 18.1.0 release plan

Hi all, Here is the tentative release plan for 18.1.0. While it hasn't been on the mesa3d.org website, it shouldn't be a surprise for anyone. Apr 20 2017 - Feature freeze/Release candidate 1 Apr 27 2017 - Release candidate 2 May 04 2017 - Release candidate 3 May 11 2017 - Release candidate 4/

[Mesa-dev] [Bug 105928] [TRACKER] Mesa 18.1 feature tracker

https://bugs.freedesktop.org/show_bug.cgi?id=105928 Bug ID: 105928 Summary: [TRACKER] Mesa 18.1 feature tracker Product: Mesa Version: unspecified Hardware: All OS: All Status: NEW Severity: normal

Re: [Mesa-dev] [PATCH] dri3: Prevent multiple freeing of buffers.

Hi, I tested this on KBL GT2. Compiz crashes during 3h test run dropped from 30 to none. There were couple of percent changes in few synthetic tests, but I think that's just because Compiz is now running properly. -> looks good! - Eero Tested-by: Eero Tamminen On 06.04.2018 11

Re: [Mesa-dev] [PATCH 02/17] ac/surface: don't set the display flag for obviously unsupported cases

On Thu, Apr 5, 2018, 3:09 AM Michel Dänzer wrote: > On 2018-04-04 07:35 PM, Marek Olšák wrote: > > On Wed, Apr 4, 2018 at 9:01 AM, Michel Dänzer > wrote: > >> On 2018-04-04 02:57 PM, Marek Olšák wrote: > >>> On Wed, Apr 4, 2018, 6:18 AM Michel Dänzer >>> > wrote: > >>

Re: [Mesa-dev] [PATCH 4/4] radv: implement VK_AMD_shader_core_properties

On Fri, Apr 6, 2018 at 3:28 PM, Samuel Pitoiset wrote: > Simple extension that only returns information for AMD hw. > > Signed-off-by: Samuel Pitoiset > --- > src/amd/vulkan/radv_device.c | 71 > +++ > src/amd/vulkan/radv_extensions.py | 1 + > 2 files

Re: [Mesa-dev] [PATCH 4/4] radv: implement VK_AMD_shader_core_properties

On 04/06/2018 03:01 PM, Nils Wallménius wrote: Hi Samuel, a question below Den fre 6 apr. 2018 14:28Samuel Pitoiset > skrev: Simple extension that only returns information for AMD hw. Signed-off-by: Samuel Pitoiset mailto:samuel.pitoi...@gmail.com>>

Re: [Mesa-dev] [PATCH 4/4] radv: implement VK_AMD_shader_core_properties

Hi Samuel, a question below Den fre 6 apr. 2018 14:28Samuel Pitoiset skrev: > Simple extension that only returns information for AMD hw. > > Signed-off-by: Samuel Pitoiset > --- > src/amd/vulkan/radv_device.c | 71 > +++ > src/amd/vulkan/radv_extensions

[Mesa-dev] [Bug 105871] Discolored KDE panels after updating to Mesa 18.0 on Intel broadwell

https://bugs.freedesktop.org/show_bug.cgi?id=105871 --- Comment #18 from Alexey Min --- (In reply to Tasev from comment #16) > (In reply to sergio.callegari from comment #13) > > As an alternate/complement solution to the patched xserver-xorg-core on the > > Padoka ppa, for those using kde plasma

Re: [Mesa-dev] [PATCH] radv: add radv_clear_{cmask,dcc} helpers

On 04/06/2018 02:35 PM, Emil Velikov wrote: On 6 April 2018 at 11:25, Samuel Pitoiset wrote: --- a/src/amd/vulkan/radv_meta.h +++ b/src/amd/vulkan/radv_meta.h @@ -195,6 +195,11 @@ void radv_blit_to_prime_linear(struct radv_cmd_buffer *cmd_buffer, struct radv_

Re: [Mesa-dev] [PATCH] radv: add radv_clear_{cmask,dcc} helpers

On 6 April 2018 at 11:25, Samuel Pitoiset wrote: > --- a/src/amd/vulkan/radv_meta.h > +++ b/src/amd/vulkan/radv_meta.h > @@ -195,6 +195,11 @@ void radv_blit_to_prime_linear(struct radv_cmd_buffer > *cmd_buffer, >struct radv_image *image, >

Re: [Mesa-dev] [RFC] - Rewrite mesa website in Sphinx

On 6 April 2018 at 10:40, Daniel Stone wrote: > Hi all, > > On 5 April 2018 at 23:55, Laura Ekstrand wrote: >> So I spoke with Daniel Stone today about the infrastructure. He estimates >> it will be ready to deploy the website in 2-3 weeks, at the most. So I'd >> say the infrastructure will be

[Mesa-dev] [PATCH 4/4] radv: implement VK_AMD_shader_core_properties

Simple extension that only returns information for AMD hw. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_device.c | 71 +++ src/amd/vulkan/radv_extensions.py | 1 + 2 files changed, 72 insertions(+) diff --git a/src/amd/vulkan/radv_device.c b/s

[Mesa-dev] [PATCH 3/4] radv: add RADV_NUM_PHYSICAL_VGPRS constant

Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_shader.c | 6 -- src/amd/vulkan/radv_shader.h | 2 ++ 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index 59ad2f3819..eaf24dcdee 100644 --- a/src/amd/vulkan/radv

[Mesa-dev] [PATCH 1/4] vulkan: Update the XML and headers to 1.1.72

Signed-off-by: Samuel Pitoiset --- include/vulkan/vulkan_android.h | 66 ++ include/vulkan/vulkan_core.h| 144 +++- src/vulkan/registry/vk.xml | 286 +--- 3 files changed, 445 insertions(+), 51 deletions(-) diff --git a/includ

[Mesa-dev] [PATCH 2/4] radv: add radv_get_num_physical_sgprs() helper

Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_shader.c | 15 --- src/amd/vulkan/radv_shader.h | 6 ++ 2 files changed, 10 insertions(+), 11 deletions(-) diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index f46beab8c1..59ad2f3819 100644 --- a/sr

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