On 21/03/18 22:10, Vinson Lee wrote:
This patch fixes these build errors with GCC 4.4.
Compiling src/gallium/auxiliary/util/u_debug_stack.c ...
src/gallium/auxiliary/util/u_debug_stack.c: In function
‘debug_backtrace_capture’:
src/gallium/auxiliary/util/u_debug_stack.c:268: error: #pragma GC
Reviewed-by: Timothy Arceri
As talked about on IRC I'll probably push this tomorrow morning unless
you get to it first.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
On 03/22/2018 04:43 AM, Lin, Johnson wrote:
Hi, Thanks for the comments.
I just noticed it does not check the extension support for
EXT_color_buffer_float neither?
That is probably because it is enabled as 'dummy_true' (see
extensions_table.h) so it's always enabled on any driver. I wonde
Hi Vinson,
Thanks for the patch.
I was considering moving the gcc stuff out into its own function e.g
get_gcc_frame_pointer() which could then be wrapped with #pragma GCC
diagnostic which gcc 4.4 should be able to handle.
However I'm not too worried about GCC 4.4 and lower so this patch is
The subject line should have read:
"st/glsl_to_nir: fix driver location for dual-slot packed doubles"
This should also partially fix packed arrays although more is needed to
make sure those work since an array can be packed across multiple other
arrays so we need to make sure everything is ass
Hi, Thanks for the comments.
I just noticed it does not check the extension support for
EXT_color_buffer_float neither?
-Original Message-
From: Palli, Tapani
Sent: Wednesday, March 21, 2018 6:57 PM
To: Alejandro Piñeiro ; Lin, Johnson
; mesa-dev@lists.freedesktop.org
Subject: Re: [Me
Aaron Watry writes:
> The opencl 1.0 langstandard was renamed in 5.0+
>
> v2: Move preprocessor check into compat.hpp
>
> Cc: Mark Janes
> Cc: Francisco Jerez
Reviewed-by: Francisco Jerez
> ---
> src/gallium/state_trackers/clover/llvm/compat.hpp | 2 ++
> src/gallium/state_trackers/clov
The opencl 1.0 langstandard was renamed in 5.0+
v2: Move preprocessor check into compat.hpp
Cc: Mark Janes
Cc: Francisco Jerez
---
src/gallium/state_trackers/clover/llvm/compat.hpp | 2 ++
src/gallium/state_trackers/clover/llvm/invocation.cpp | 2 +-
2 files changed, 3 insertions(+), 1 del
Hi Emil,
From radv perspective we seem to have one bug in CTS to debug, but all
games I tested that are expected to work seemed to work ok. Per
discussion with Dave I'd like to give the go ahead for releasing this
wrt radv.
Thanks,
Bas
On Wed, Mar 21, 2018 at 3:50 PM, Emil Velikov wrote:
> The
On Thu, Mar 8, 2018 at 12:59 PM, James Legg wrote:
> This avoids bug 105396 somehow. I suspect it is a VI and GFX9 hardware
> bug which PAL calls WaTcCompatZRange, but I don't know for sure.
>
> In the VK_FORMAT_D32_SFLOAT case, TILE_STENCIL_DISABLE is not set for
> tc compatible image formats reg
From: Ian Romanick
Now that i965 recognizes that a-b generates the same conditions as 'a <
b', there is no reason to condition this transformation on 'is not used
by conditional.'
Since this was the only user of the is_not_used_by_conditional function,
delete it.
All Gen6+ platforms had similar
From: Ian Romanick
This method is similar to the existing ::equals methods. Instead of
testing that two src_regs are equal to each other, it tests that one is
the negation of the other.
v2: Simplify various checks based on suggestions from Matt. Use
src_reg::type instead of fixed_hw_reg.type i
From: Ian Romanick
The math inside the add and the cmp in this instruction sequence is the
same. We can utilize this to eliminate the compare.
add(8) g5<1>F g2<8,8,1>F g64.5<0,1,0>F { align1 1Q
compacted };
cmp.z.f0(8) null<1>Fg2<8,8,1>F -g64.5<0,1,0>F
From: Ian Romanick
No shader-db changes. This source must have been written by a previous
instruction, so it cannot be a uniform or a shader input. However, this
change allows the next commit to help more shaders.
Signed-off-by: Ian Romanick
---
src/intel/compiler/brw_vec4_cmod_propagation.c
From: Ian Romanick
No shader-db changes. This source must have been written by a previous
instruction, so it cannot be a uniform or a shader input. However, this
change allows the next commit to help about 900 more shaders.
Signed-off-by: Ian Romanick
---
src/intel/compiler/brw_fs_cmod_propa
From: Ian Romanick
No changes on Broadwell and later becuase those plaforms do not use the
vec4 backend at all.
Ivy Bridge and Haswell had similar results. (Ivy Bridge shown)
total instructions in shared programs: 11682119 -> 11681056 (<.01%)
instructions in affected programs: 150403 -> 149340 (
https://bugs.freedesktop.org/show_bug.cgi?id=77449
Bug 77449 depends on bug 105426, which changed state.
Bug 105426 Summary: [regression] Mesa-18.0rc4 - black screen in some Valve
games when run under Wine
https://bugs.freedesktop.org/show_bug.cgi?id=105426
What|Removed
To all X.Org Foundation Members:
The X.Org Foundation's annual election is now open and will remain
open until 23:59 UTC on 5 April 2018.
Four of the eight director seats are open during this election, with
the four nominees receiving the highest vote totals serving as
directors for two year term
Just one bit of feedback, for the rest I either agree or have no opinion:
On Wed, Mar 21, 2018 at 8:28 PM, Emil Velikov wrote:
> * unfit and late nominations:
> * any rejections that are unfit based on the existing criteria can
> be merged as long as:
>* subsystem specific patc
Hi all,
Having gone through the thread a few times, I believe it can be
summarised as follows:
* Greater transparency is needed.
* Subsystem/team maintainers.
* Unfit and late nominations.
* Developers/everyone should be more involved.
* Greater automation must be explored.
NOTES:
* Some o
https://bugs.freedesktop.org/show_bug.cgi?id=105670
Bug ID: 105670
Summary: [regression][hang] Trine1EE hangs GPU after loading
screen on Mesa3D-17.3 and later
Product: Mesa
Version: 17.3
Hardware: Other
OS:
Am 22.03.2018 um 00:43 schrieb Ilia Mirkin:
> On Wed, Mar 21, 2018 at 7:37 PM, Roland Scheidegger
> wrote:
>> Personally I'm not a big proponent on propagating single-vendor
>> extensions (which are useless for anything but one specific driver) more
>> or less directly through to gallium.
>> Ther
The indentation error shall be fixed.
no_error="true" does mean there's a separate no-error variant of the
function. I create such variants for consistency with other functions
in viewport.c
On Wed, Mar 21, 2018 at 11:40 PM, Ilia Mirkin wrote:
> On Wed, Mar 21, 2018 at 7:11 PM, pendingchaos
>
I haven't tested on Maxwell as I don't have easy access to one but I
think I can do so sometime tomorrow.
I'll gate on GM200 with the second revision of the patch-set.
prec_bias should always fit in the max value of an immed, 2**12-1, as
the maximum subpixel precision bias is 8 on GM200 and later
On Wed, Mar 21, 2018 at 7:37 PM, Roland Scheidegger wrote:
> Personally I'm not a big proponent on propagating single-vendor
> extensions (which are useless for anything but one specific driver) more
> or less directly through to gallium.
> There's an intel extension doing similar things already t
Hey Robert,
On Wed, Mar 21, 2018 at 4:16 PM, Robert Foss wrote:
> Hey,
>
> I've started looking into removing the gralloc method
> GRALLOC_MODULE_PERFORM_GET_DRM_FD.
>
> The issues around this seems to be two parts:
> 1) Finding the right device to open
> 2) Sharing the device between components
On Wed, Mar 21, 2018 at 7:11 PM, pendingchaos wrote:
> Although the specs write it against compatibility GL 4.3 and allows core
> profile and GLES2+, it is exposed for GL 1.0+ and GLES1 and GLES2+.
> ---
> src/mapi/glapi/gen/gl_API.xml | 47 +++
> src/mapi/glapi/gen/gl_genexec.
Personally I'm not a big proponent on propagating single-vendor
extensions (which are useless for anything but one specific driver) more
or less directly through to gallium.
There's an intel extension doing similar things already too.
Ideally we'd end up with some bits in gallium which can do whate
On Wed, Mar 21, 2018 at 7:11 PM, pendingchaos wrote:
> Subpixel precision bias, dilation and the post-snap mode are supported on
> GM2xx and newer. The pre-snap mode is supported for triangle primitives on
> GP1xx.
> ---
> src/gallium/drivers/nouveau/nvc0/nvc0_3d.xml.h | 5 +
> src/g
Subpixel precision bias, dilation and the post-snap mode are supported on
GM2xx and newer. The pre-snap mode is supported for triangle primitives on
GP1xx.
---
src/gallium/drivers/nouveau/nvc0/nvc0_3d.xml.h | 5 +
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 18 +++
Although the specs write it against compatibility GL 4.3 and allows core
profile and GLES2+, it is exposed for GL 1.0+ and GLES1 and GLES2+.
---
src/mapi/glapi/gen/gl_API.xml | 47 +++
src/mapi/glapi/gen/gl_genexec.py| 1 +
src/mesa/Makefile.sources | 2
---
src/mesa/state_tracker/st_atom_rasterizer.c | 12 ++
src/mesa/state_tracker/st_atom_viewport.c | 4
src/mesa/state_tracker/st_context.c | 2 ++
src/mesa/state_tracker/st_extensions.c | 34 +
4 files changed, 52 insertions(+)
diff --git
---
src/gallium/docs/source/cso/rasterizer.rst | 18 ++
src/gallium/docs/source/screen.rst | 18 ++
src/gallium/drivers/etnaviv/etnaviv_screen.c | 10 ++
src/gallium/drivers/freedreno/freedreno_screen.c | 10 ++
src/gallium/dr
This patch-set adds support for GL_NV_conservative_raster and
GL_NV_conservative_raster_dilate on GM2xx and newer. It also adds support for
GL_NV_conservative_raster_pre_snap_triangles on GP1xx.
In doing so, it implements various functions in mesa core, extends the Gallium
API, connects the new me
Aaron Watry writes:
> On Wed, Mar 21, 2018, 4:49 PM Francisco Jerez wrote:
>
>> Aaron Watry writes:
>>
>> > The opencl 1.0 langstandard was renamed in 5.0+
>> >
>> > Cc: Mark Janes
>> > ---
>> > src/gallium/state_trackers/clover/llvm/invocation.cpp | 4
>> > 1 file changed, 4 insertions(
On Wed, Mar 21, 2018, 4:49 PM Francisco Jerez wrote:
> Aaron Watry writes:
>
> > The opencl 1.0 langstandard was renamed in 5.0+
> >
> > Cc: Mark Janes
> > ---
> > src/gallium/state_trackers/clover/llvm/invocation.cpp | 4
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/src/galli
Matt Turner writes:
> On Wed, Mar 21, 2018 at 2:56 PM, Francisco Jerez
> wrote:
>> Matt Turner writes:
>>
>>> From Message Descriptor section in gfxspecs:
>>>
>>> "Memory fence messages without Commit Enable set do not return
>>>anything to the thread (response length is 0 and destinatio
On Wed, Mar 21, 2018 at 2:56 PM, Francisco Jerez wrote:
> Matt Turner writes:
>
>> From Message Descriptor section in gfxspecs:
>>
>> "Memory fence messages without Commit Enable set do not return
>>anything to the thread (response length is 0 and destination
>>register is null)."
>>
>>
Matt Turner writes:
> From Message Descriptor section in gfxspecs:
>
> "Memory fence messages without Commit Enable set do not return
>anything to the thread (response length is 0 and destination
>register is null)."
>
> This fixes a GPU hang in simulation in the piglit test
> arb_shade
This patch fixes these build errors with GCC 4.4.
Compiling src/gallium/auxiliary/util/u_debug_stack.c ...
src/gallium/auxiliary/util/u_debug_stack.c: In function
‘debug_backtrace_capture’:
src/gallium/auxiliary/util/u_debug_stack.c:268: error: #pragma GCC diagnostic
not allowed inside functio
On Wed, Mar 21, 2018 at 2:52 PM, Kenneth Graunke wrote:
> On Wednesday, March 21, 2018 2:06:19 PM PDT Matt Turner wrote:
>> From: Anuj Phogat
>>
>> Disabling fast color clear makes fbo-clearmipmap test render correct
>> texture in base miplevel. Fast color clear is anyways disabled for
>> non-bas
On Wednesday, March 21, 2018 2:06:16 PM PDT Matt Turner wrote:
> From Message Descriptor section in gfxspecs:
>
> "Memory fence messages without Commit Enable set do not return
>anything to the thread (response length is 0 and destination
>register is null)."
>
> This fixes a GPU hang i
On Wednesday, March 21, 2018 2:06:21 PM PDT Matt Turner wrote:
> ---
> src/intel/compiler/test_eu_validate.cpp | 39
> +
> 1 file changed, 39 insertions(+)
I'd be tempted to write this as
!devinfo.has_64bit_types && type_sz(inst[i].dst_type) == 8 &&
inst[i]
On Wednesday, March 21, 2018 2:06:17 PM PDT Matt Turner wrote:
> From: Jason Ekstrand
>
> Otherwise all our render target writes go no where.
> ---
> src/intel/compiler/brw_eu_emit.c | 3 +++
> src/intel/compiler/brw_inst.h| 3 +++
> 2 files changed, 6 insertions(+)
>
> diff --git a/src/int
On Wed, Mar 21, 2018 at 2:51 PM, Kenneth Graunke wrote:
> On Wednesday, March 21, 2018 2:06:18 PM PDT Matt Turner wrote:
>> From: Anuj Phogat
>>
>> When source or destination datatype is 64b or operation is integer
>> DWord multiply, DepCtrl must not be used.
>> We had this restriction on few pre
On Wednesday, March 21, 2018 2:06:19 PM PDT Matt Turner wrote:
> From: Anuj Phogat
>
> Disabling fast color clear makes fbo-clearmipmap test render correct
> texture in base miplevel. Fast color clear is anyways disabled for
> non-base miplevels.
> ---
> src/mesa/drivers/dri/i965/brw_blorp.c | 4
On Wednesday, March 21, 2018 2:06:18 PM PDT Matt Turner wrote:
> From: Anuj Phogat
>
> When source or destination datatype is 64b or operation is integer
> DWord multiply, DepCtrl must not be used.
> We had this restriction on few previous intel platforms. It has been
> brought back on Gen11+.
>
On Wednesday, March 21, 2018 2:06:12 PM PDT Matt Turner wrote:
> We all know the platform names, and I don't want to update this list
> continually.
> ---
> src/intel/tools/aubinator.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/intel/tools/aubinator.c b/src/intel
Aaron Watry writes:
> The opencl 1.0 langstandard was renamed in 5.0+
>
> Cc: Mark Janes
> ---
> src/gallium/state_trackers/clover/llvm/invocation.cpp | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/src/gallium/state_trackers/clover/llvm/invocation.cpp
> b/src/gallium/state_tracke
This patch fixes the clover build for Clang 4.0, which is what the Intel
CI uses.
Tested-by: Mark Janes
Aaron Watry writes:
> The opencl 1.0 langstandard was renamed in 5.0+
>
> Cc: Mark Janes
> ---
> src/gallium/state_trackers/clover/llvm/invocation.cpp | 4
> 1 file changed, 4 inserti
Matches the bspec.
Reviewed-by: Rafael Antognolli
On Wed, Mar 21, 2018 at 02:06:20PM -0700, Matt Turner wrote:
> From: Anuj Phogat
>
> ---
> include/pci_ids/i965_pci_ids.h | 9 +
> 1 file changed, 9 insertions(+)
>
> diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_
On Wed, Mar 21, 2018 at 02:06:14PM -0700, Matt Turner wrote:
> From: Anuj Phogat
>
> On gen11+ AUX_HIZ is not a supported value for surfaces being
> sampled by the 3D sampler.
Reviewed-by: Rafael Antognolli
> ---
> src/intel/dev/gen_device_info.c | 1 +
> 1 file changed, 1 insertion(+)
>
> d
On Wed, Mar 21, 2018 at 02:06:12PM -0700, Matt Turner wrote:
> We all know the platform names, and I don't want to update this list
> continually.
Reviewed-by: Rafael Antognolli
> ---
> src/intel/tools/aubinator.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/int
Reviewed-by: Bas Nieuwenhuizen
for the series.
On Wed, Mar 21, 2018 at 9:30 PM, Samuel Pitoiset
wrote:
> The hardware only supports 32-bit depth surfaces, but we can
> enable TC-compat HTILE for 16-bit depth surfaces if no Z planes
> are compressed.
>
> The main benefit is to reduce the number
The opencl 1.0 langstandard was renamed in 5.0+
Cc: Mark Janes
---
src/gallium/state_trackers/clover/llvm/invocation.cpp | 4
1 file changed, 4 insertions(+)
diff --git a/src/gallium/state_trackers/clover/llvm/invocation.cpp
b/src/gallium/state_trackers/clover/llvm/invocation.cpp
index af
From Message Descriptor section in gfxspecs:
"Memory fence messages without Commit Enable set do not return
anything to the thread (response length is 0 and destination
register is null)."
This fixes a GPU hang in simulation in the piglit test
arb_shader_image_load_store-shader-mem-barrie
Now that the PCI IDs are upstream, this can be readded.
---
src/intel/compiler/test_eu_validate.cpp | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/intel/compiler/test_eu_validate.cpp
b/src/intel/compiler/test_eu_validate.cpp
index e36f50a2d7e..79401222d78 100644
--- a/src/intel/compiler/
From: Anuj Phogat
Rafael ran piglit with the test code enabled and saw no additional GPU
hangs.
---
src/intel/compiler/brw_compiler.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/compiler/brw_compiler.h
b/src/intel/compiler/brw_compiler.h
index 0e27c898203..d3ae
From: Anuj Phogat
On gen11+ AUX_HIZ is not a supported value for surfaces being
sampled by the 3D sampler.
---
src/intel/dev/gen_device_info.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/intel/dev/gen_device_info.c b/src/intel/dev/gen_device_info.c
index 3365bdd4dd6..9e684b78a09 1006
From: Anuj Phogat
ICL uses the same L3 configs as CNL, just leaving the SLM configs out.
---
src/intel/common/gen_l3_config.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/src/intel/common/gen_l3_config.c b/src/intel/common/gen_l3_config.c
index 7d58ad8d7c8..b977c6ab136
From: Anuj Phogat
When source or destination datatype is 64b or operation is integer
DWord multiply, DepCtrl must not be used.
We had this restriction on few previous intel platforms. It has been
brought back on Gen11+.
---
src/intel/compiler/brw_vec4.cpp | 8 ++--
1 file changed, 6 insertio
From: Jason Ekstrand
Otherwise all our render target writes go no where.
---
src/intel/compiler/brw_eu_emit.c | 3 +++
src/intel/compiler/brw_inst.h| 3 +++
2 files changed, 6 insertions(+)
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index fe7fa8723e1..9
---
src/intel/compiler/test_eu_validate.cpp | 39 +
1 file changed, 39 insertions(+)
diff --git a/src/intel/compiler/test_eu_validate.cpp
b/src/intel/compiler/test_eu_validate.cpp
index 8169f951b2d..e36f50a2d7e 100644
--- a/src/intel/compiler/test_eu_validate.cpp
From: Anuj Phogat
---
include/pci_ids/i965_pci_ids.h | 9 +
1 file changed, 9 insertions(+)
diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h
index feb9c582b19..925655e9908 100644
--- a/include/pci_ids/i965_pci_ids.h
+++ b/include/pci_ids/i965_pci_ids.h
@@ -19
From: Anuj Phogat
Disabling fast color clear makes fbo-clearmipmap test render correct
texture in base miplevel. Fast color clear is anyways disabled for
non-base miplevels.
---
src/mesa/drivers/dri/i965/brw_blorp.c | 4
1 file changed, 4 insertions(+)
diff --git a/src/mesa/drivers/dri/i96
We all know the platform names, and I don't want to update this list
continually.
---
src/intel/tools/aubinator.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/tools/aubinator.c b/src/intel/tools/aubinator.c
index 8029dc12155..2a72efa8a2c 100644
--- a/src/intel/tool
There's nothing to worry about here -- the A channel just gets dropped by
the blit. This avoids a segfault in the fallback path when copying from a
RGBA16_SINT renderbuffer to a RGB16_SINT destination represented by an
RGBA16_SINT texture (the fallback path tries to get/fetch to float
buffers, but
On Wed, Mar 21, 2018 at 2:52 PM, Aaron Watry wrote:
> On Wed, Mar 21, 2018 at 2:37 PM, Mark Janes wrote:
>> Aaron, this patch breaks the meson build-test in our CI:
>>
>> ../src/gallium/state_trackers/clover/llvm/invocation.cpp:88:36: error:
>> ‘lang_opencl10’ is not a member of ‘clang::LangSta
On 14 March 2018 at 20:13, Andres Gomez wrote:
> On Wed, 2018-03-14 at 16:02 +, Emil Velikov wrote:
>
> [...]
>>
>> Just double-checking:
>> I would suspect you're not suggesting removing the existing email/poke
>> scheme?
>
> Partially. The "announce" mail for the pre-branching period will s
Instead of that huge conditional that's going to be crazy.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_image.c | 56 -
1 file changed, 45 insertions(+), 11 deletions(-)
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_device.c | 51
1 file changed, 37 insertions(+), 14 deletions(-)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 36ba0c3833..22500bfc13 100644
--- a/src/amd/vulkan/r
The hardware only supports 32-bit depth surfaces, but we can
enable TC-compat HTILE for 16-bit depth surfaces if no Z planes
are compressed.
The main benefit is to reduce the number of depth decompression
passes. Also, we don't need to implement DB->CB copies which is
fine.
This improves Serious
On Wed, Mar 21, 2018 at 2:37 PM, Mark Janes wrote:
> Aaron, this patch breaks the meson build-test in our CI:
>
> ../src/gallium/state_trackers/clover/llvm/invocation.cpp:88:36: error:
> ‘lang_opencl10’ is not a member of ‘clang::LangStandard’
> { 100, clang::LangStandard::lang_opencl10
Aaron, this patch breaks the meson build-test in our CI:
../src/gallium/state_trackers/clover/llvm/invocation.cpp:88:36: error:
‘lang_opencl10’ is not a member of ‘clang::LangStandard’
{ 100, clang::LangStandard::lang_opencl10},
configured with:
meson -Dbuild-tests=true
-Dgallium-dri
The SPIR-V spec doesn’t specify a size requirement for these and the
equivalent functions in the GLSL spec have explicit alternatives for
doubles. Refract is a little bit more complicated due to the fact that
the final argument is always supposed to be a scalar 32- or 16- bit
float regardless of th
The only change neccessary is to change the type of the constant used
to compare against.
This has been tested against the arb_gpu_shader_fp64/execution/
fs-isinf-dvec tests using the ARB_gl_spirv branch.
v2: Use nir_imm_floatN_t for the constant.
---
src/compiler/spirv/vtn_alu.c | 7 ---
1
There is an existing macro that is used to choose between either a
float or a double immediate constant based on the bit size of the
first operand to the builtin. This is now changed to use the new
nir_imm_floatN_t helper function to reduce the number of places that
make this decision.
---
src/com
This lets you easily build float immediates just given the bit size.
If we have this single place here to handle this then it will be
easier to add support for 16-bit floats later.
---
src/compiler/nir/nir_builder.h | 13 +
1 file changed, 13 insertions(+)
diff --git a/src/compiler/ni
This adds support for doubles in some of the builtin functions. The
last two patches have been posted already and are a v2 based on
Jason’s feedback.
These patches come out of testing using the ARB_gl_spirv branch of
Mesa and Piglit. However they also affect Vulkan and can be tested
with VkRunner
On March 21, 2018 6:47:48 PM UTC, Dylan Baker wrote:
> Quoting Emil Velikov (2018-03-21 10:53:08)
> > On 21 March 2018 at 17:09, Eric Engestrom
> wrote:
> > > Cc: Maxin B. John
> > > Cc: Khem Raj
> > > Suggested-by: Jon Turney
> > > Signed-off-by: Eric Engestrom
> > > ---
> > > configure.a
Quoting Emil Velikov (2018-03-21 10:53:08)
> On 21 March 2018 at 17:09, Eric Engestrom wrote:
> > Cc: Maxin B. John
> > Cc: Khem Raj
> > Suggested-by: Jon Turney
> > Signed-off-by: Eric Engestrom
> > ---
> > configure.ac| 1 +
> > meson.build | 2 +-
> > src/util/u_endian.h |
Quoting Emil Velikov (2018-03-21 10:57:09)
> On 21 March 2018 at 17:54, Eric Engestrom wrote:
> > On Wednesday, 2018-03-21 10:45:35 -0700, Dylan Baker wrote:
> >> Quoting Eric Engestrom (2018-03-21 10:09:17)
> >> > Cc: Maxin B. John
> >> > Cc: Khem Raj
> >> > Suggested-by: Jon Turney
> >> > Sig
---
src/intel/genxml/gen10.xml | 23 +++
src/intel/genxml/gen11.xml | 23 +++
src/intel/genxml/gen7.xml | 22 ++
src/intel/genxml/gen75.xml | 25 +
src/intel/genxml/gen8.xml | 23 +++
src/inte
---
src/intel/genxml/gen10.xml | 27 +++
src/intel/genxml/gen11.xml | 27 +++
src/intel/genxml/gen7.xml | 19 +++
src/intel/genxml/gen75.xml | 17 +
src/intel/genxml/gen8.xml | 24
src/intel/
---
src/intel/genxml/gen10.xml | 18 ++
src/intel/genxml/gen11.xml | 18 ++
src/intel/genxml/gen7.xml | 20
src/intel/genxml/gen75.xml | 22 ++
src/intel/genxml/gen8.xml | 18 ++
src/intel/genxml/gen9.xml |
Decode SC_INSTDONE, ROW_INSTDONE and SAMPLER_INSTDONE.
---
src/intel/tools/aubinator_error_decode.c | 12
1 file changed, 12 insertions(+)
diff --git a/src/intel/tools/aubinator_error_decode.c
b/src/intel/tools/aubinator_error_decode.c
index db880d74a9e..9abd05fd75a 100644
--- a/src
https://bugs.freedesktop.org/show_bug.cgi?id=105240
--- Comment #1 from Hleb Valoshka <375...@gmail.com> ---
Works on Devuan 2 (Debian 9) with Linux 4.9 and 4.15 and Mesa 13.0.6, so I
assume that the problem is in Mesa.
--
You are receiving this mail because:
You are the assignee for the bug.___
https://bugs.freedesktop.org/show_bug.cgi?id=105240
Hleb Valoshka <375...@gmail.com> changed:
What|Removed |Added
Assignee|dri-devel@lists.freedesktop |mesa-dev@lists.freedes
On Wednesday, 2018-03-21 10:11:45 -0700, Matt Turner wrote:
> On Wed, Mar 21, 2018 at 2:39 AM, Eric Engestrom
> wrote:
> > On Tuesday, 2018-03-20 13:39:25 -0700, Scott D Phillips wrote:
> >> When building intel_tiled_memcpy for i686, the stack will only be
> >> 4-byte aligned. This isn't sufficien
On Wednesday, 2018-03-21 17:53:08 +, Emil Velikov wrote:
> On 21 March 2018 at 17:09, Eric Engestrom wrote:
> > Cc: Maxin B. John
> > Cc: Khem Raj
> > Suggested-by: Jon Turney
> > Signed-off-by: Eric Engestrom
> > ---
> > configure.ac| 1 +
> > meson.build | 2 +-
> > src/
On Tue, Mar 20, 2018 at 9:26 AM, Tomasz Figa wrote:
> On Wed, Mar 21, 2018 at 12:58 AM, Emil Velikov
> wrote:
>> On 20 March 2018 at 14:24, Tomasz Figa wrote:
>>> On Tue, Mar 20, 2018 at 10:44 PM, Emil Velikov
>>> wrote:
On 20 March 2018 at 04:40, Tomasz Figa wrote:
> On Tue, Mar 20
On 21 March 2018 at 17:54, Eric Engestrom wrote:
> On Wednesday, 2018-03-21 10:45:35 -0700, Dylan Baker wrote:
>> Quoting Eric Engestrom (2018-03-21 10:09:17)
>> > Cc: Maxin B. John
>> > Cc: Khem Raj
>> > Suggested-by: Jon Turney
>> > Signed-off-by: Eric Engestrom
>> > ---
>> > configure.ac
On Wednesday, 2018-03-21 17:54:02 +, Eric Engestrom wrote:
> On Wednesday, 2018-03-21 10:45:35 -0700, Dylan Baker wrote:
> > Quoting Eric Engestrom (2018-03-21 10:09:17)
> > > Cc: Maxin B. John
> > > Cc: Khem Raj
> > > Suggested-by: Jon Turney
> > > Signed-off-by: Eric Engestrom
> > > ---
>
On Wednesday, 2018-03-21 10:45:35 -0700, Dylan Baker wrote:
> Quoting Eric Engestrom (2018-03-21 10:09:17)
> > Cc: Maxin B. John
> > Cc: Khem Raj
> > Suggested-by: Jon Turney
> > Signed-off-by: Eric Engestrom
> > ---
> > configure.ac| 1 +
> > meson.build | 2 +-
> > src/util/u
On 21 March 2018 at 17:09, Eric Engestrom wrote:
> Cc: Maxin B. John
> Cc: Khem Raj
> Suggested-by: Jon Turney
> Signed-off-by: Eric Engestrom
> ---
> configure.ac| 1 +
> meson.build | 2 +-
> src/util/u_endian.h | 2 +-
> 3 files changed, 3 insertions(+), 2 deletions(-)
>
>
Quoting Eric Engestrom (2018-03-21 10:09:17)
> Cc: Maxin B. John
> Cc: Khem Raj
> Suggested-by: Jon Turney
> Signed-off-by: Eric Engestrom
> ---
> configure.ac| 1 +
> meson.build | 2 +-
> src/util/u_endian.h | 2 +-
> 3 files changed, 3 insertions(+), 2 deletions(-)
>
> diff
From: Marek Olšák
---
src/mesa/state_tracker/st_draw.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/src/mesa/state_tracker/st_draw.c b/src/mesa/state_tracker/st_draw.c
index b95a2522b2e..73f936bb4a9 100644
--- a/src/mesa/state_tracker/st_draw.c
+++ b/src/mesa/state_tracker/st_draw.
On Wednesday, 2018-03-21 10:11:55 -0700, Dylan Baker wrote:
> Quoting Jon Turney (2018-03-21 09:47:23)
> > On 21/03/2018 15:09, Emil Velikov wrote:
> > > Hi Maxin,
> > >
> > > Welcome back ;-)
> > >
> > > On 21 March 2018 at 14:52, wrote:
> > >> From: Khem Raj
> > >>
> > >> endianness check is
Quoting Jon Turney (2018-03-21 09:47:23)
> On 21/03/2018 15:09, Emil Velikov wrote:
> > Hi Maxin,
> >
> > Welcome back ;-)
> >
> > On 21 March 2018 at 14:52, wrote:
> >> From: Khem Raj
> >>
> >> endianness check is OS wide and not specific to libc.
> >> Fixes build with musl libc
> >>
> >> Sig
On Wed, Mar 21, 2018 at 2:39 AM, Eric Engestrom
wrote:
> On Tuesday, 2018-03-20 13:39:25 -0700, Scott D Phillips wrote:
>> When building intel_tiled_memcpy for i686, the stack will only be
>> 4-byte aligned. This isn't sufficient for SSE temporaries which
>> require 16-byte alignment. Use the for
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