Ken, do you have any comments about this patch? I'd like to push it
otherwise.
Iago
On Thu, 2018-01-04 at 14:24 -0800, Jason Ekstrand wrote:
> Reviewed-by: Jason Ekstrand
>
> Ken?
>
> On Wed, Jan 3, 2018 at 6:55 PM, Iago Toral Quiroga > wrote:
> > Although on gen8+ platforms we can in theory
Rename the (un)map_gtt functions to (un)map_map (map by
returning a map) and add new functions (un)map_tiled_memcpy that
return a shadow buffer populated with the intel_tiled_memcpy
functions.
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 95 ---
1 file changed, 86 in
In all current uses, the linear surface is only allocated starting
at (xt1, yt1) anyway, so this improves the calling ergonomics.
---
src/mesa/drivers/dri/i965/intel_pixel_read.c | 2 +-
src/mesa/drivers/dri/i965/intel_tex_image.c| 4 ++--
src/mesa/drivers/dri/i965/intel_tiled_memcpy.c | 1
Instead of gtt mapping, call out to other map functions (map_map
or map_tiled_memcpy) for the depth surface. Removes a place where
gtt mapping is used.
---
This is a bit icky, perhaps something like mapping z_mt with
BRW_MAP_DIRECT_BIT could be cleaner (but in that case the
depthstencil mapping and
Removes a place where gtt mapping is used.
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index e4a3f163d2..fa4ae06399 100644
---
When initializing mcs, map with MAP_RAW and fill in the linear
map. Removes a place where gtt mapping is used.
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri
From: Dave Airlie
The normal ssa renumbering isn't sufficient for LDS queue access,
this uses two stacks, one for the lds queue, and one for the
lds r/w ordering.
The LDS oq values are incremented in their use in a linear
fashion.
The LDS rw values are incremented in their definitions and used
i
From: Dave Airlie
Don't apply this until we have a lot more tests passing
this disables SB for barrier usage (as those will be a lot of
"fun")
---
src/gallium/drivers/r600/r600_shader.c | 11 ---
src/gallium/drivers/r600/r600_shader.h | 1 +
2 files changed, 5 insertions(+), 7 deletion
From: Dave Airlie
This has some hacks in it that in the end make heaven run
---
src/gallium/drivers/r600/sb/sb_bc_builder.cpp | 2 +-
src/gallium/drivers/r600/sb/sb_bc_decoder.cpp | 1 +
src/gallium/drivers/r600/sb/sb_bc_finalize.cpp | 10 +++-
src/gallium/drivers/r600/sb/sb_gcm.cpp
From: Dave Airlie
if no destination:
a) convert _RET instructions to non _RET variants if no dst
b) set src0 to undefined if it's a READ, this should get DCE then.
---
src/gallium/drivers/r600/sb/sb_peephole.cpp | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/src/gall
From: Dave Airlie
You have to schedule LDS_READ_RET _, x and MOV reg, LDS_OQ_A_POP
in the same basic block/clause. This makes sure once we've issues
and MOV we don't add another block until we balance it with an
LDS read.
---
src/gallium/drivers/r600/sb/sb_gcm.cpp | 15 ++-
src/galli
From: Dave Airlie
Don't try and fold LDS using expressions.
---
src/gallium/drivers/r600/sb/sb_expr.cpp | 11 +++
1 file changed, 11 insertions(+)
diff --git a/src/gallium/drivers/r600/sb/sb_expr.cpp
b/src/gallium/drivers/r600/sb/sb_expr.cpp
index 7a5d62c8e8..7d43ef1d1d 100644
--- a/sr
From: Dave Airlie
So LDS ops have to be SLOT_X,
and LDS OQ reads have read port restrictions so we try
and force those into only having one per slot and avoiding
bank swizzles.
---
src/gallium/drivers/r600/sb/sb_bc.h | 3 +++
src/gallium/drivers/r600/sb/sb_sched.cpp | 4
2 files change
From: Dave Airlie
This adds support for tracking the lds oq read/writes
so can avoid scheduling other things in between.
This patch just adds the tracking and assert to show
problems.
---
src/gallium/drivers/r600/sb/sb_sched.cpp | 13 ++---
src/gallium/drivers/r600/sb/sb_sched.h | 5
From: Dave Airlie
This tries to avoid an lds queue read getting scheduled separately
from an lds ret read, the non-sb code uses the same style of hammer,
this isn't foolproof.
We can do better, but it's a bit tricky, as you have to scan ahead
and either schedule more lds oq moves and more lds re
From: Dave Airlie
This adds lds to the geom emit handling
---
src/gallium/drivers/r600/sb/sb_bc_finalize.cpp | 2 +-
src/gallium/drivers/r600/sb/sb_sched.cpp | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/r600/sb/sb_bc_finalize.cpp
b/src/gallium
From: Dave Airlie
This field is ignored for tf writes so should be 0.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/eg_asm.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/r600/eg_asm.c
b/src/gallium/drivers/r600/eg_asm.c
index 8f9d1b85f
From: Dave Airlie
This handles parsing the LDS ops and queue accessess.
---
src/gallium/drivers/r600/sb/sb_bc_parser.cpp | 52 ++--
1 file changed, 50 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/r600/sb/sb_bc_parser.cpp
b/src/gallium/drivers/r600/sb/s
From: Dave Airlie
Although these are op3s they don't have a dst reg.
---
src/gallium/drivers/r600/sb/sb_bc_dump.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/r600/sb/sb_bc_dump.cpp
b/src/gallium/drivers/r600/sb/sb_bc_dump.cpp
index 72a1b24467..3b5d9
From: Dave Airlie
Some tess shaders were doing MOVA_INT _, c0.x on cayman, and then
hitting an assert in sb_bc_finalize.cpp:translate_kcache.
This makes sure the toplevel kcache tracker gets updated,
and the clause gets fixed up.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/sb/sb_s
From: Dave Airlie
This fixes bad interactions with the LDS special values.
---
src/gallium/drivers/r600/sb/sb_core.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/r600/sb/sb_core.cpp
b/src/gallium/drivers/r600/sb/sb_core.cpp
index cdc2862d36..5049b677
From: Dave Airlie
It's rare to have a final alu clause on normal shaders (exports)
but tess shaders write to LDS as their output, so we see some
alu clauses, and the CF_END get put in the wrong place.
This makes sure to update last_cf correctly.
Signed-off-by: Dave Airlie
---
src/gallium/driv
From: Dave Airlie
This adds support for GDS ops to sb backend.
This seems to work for atomics and tess factor writes.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_isa.h| 2 +-
src/gallium/drivers/r600/sb/sb_bc.h| 7
src/gallium/drivers/r600/sb/sb
From: Dave Airlie
This stops them being optimised out.
---
src/gallium/drivers/r600/sb/sb_bc_parser.cpp | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/r600/sb/sb_bc_parser.cpp
b/src/gallium/drivers/r600/sb/sb_bc_parser.cpp
index ae92a767b4..de3984f59
From: Dave Airlie
For LDS read/write ordering we use the LDS_RW value, reads
will wait on previous writes.
For LDS read/read from LDS queue ordering we use the LDS_OQ
values, we define two for now, though initially we'll just
support OQA.
Also add the check for the lds oq values
Signed-off-by:
From: Dave Airlie
We need to convert these to the hw special registers.
---
src/gallium/drivers/r600/sb/sb_bc_finalize.cpp | 12
1 file changed, 12 insertions(+)
diff --git a/src/gallium/drivers/r600/sb/sb_bc_finalize.cpp
b/src/gallium/drivers/r600/sb/sb_bc_finalize.cpp
index 2ec4
This is an attempt to add tessellation support to the SB backend.
The main things needed are GDS access which is used for tess
factor storage (also used for atomic counters), and LDS access
which is needed to pass all the data between stages.
The first 19 patches are the stuff I'm happy with, the
From: Dave Airlie
Just saves a pointless a = a + 0;
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_shader.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_shader.c
b/src/gallium/drivers/r600/r600_shader.c
index 1b
Fixes the follow test for radeonsi nir:
tests/spec/arb_tessellation_shader/execution/quads.shader_test
Also stops 8 other tests from crashing, they now just fail e.g.
tcs-output-array-float-index-rd-after-barrier.shader_test
---
src/amd/common/ac_nir_to_llvm.c | 11 ++-
src/amd
Hi Marek;
This one works but only if you add
DRI_CONF_ALLOW_RGB10_CONFIGS("false")
to the DRI_CONF_SECTION_MISCELLANEOUS section in intel_screen. With that
change: Reviewed-by: Tapani Pälli
On 01/09/2018 04:04 PM, Marek Olšák wrote:
From: Marek Olšák
This is unused because it's for libG
On 01/09/2018 05:05 PM, Eric Engestrom wrote:
On Tuesday, 2018-01-09 09:48:19 +0200, Tapani Pälli wrote:
Cache set and get are called in similar fashion as what is happening
with disk cache. Functionality requires ARB_get_program_binary and
EGL_ANDROID_blob_cache support.
Signed-off-by: Tapan
On 01/09/2018 07:15 PM, srol...@vmware.com wrote:
From: Roland Scheidegger
We've seen some problems internally due to macro redefinition.
Fix this by adding HAVE_FUNC_ATTRIBUTE_NORETURN to c99_compat.h,
and defining it for msvc.
And avoid redefinition just in case.
---
include/c99_compat.h |
On 10 January 2018 at 12:34, Bas Nieuwenhuizen wrote:
> Tested with a modified deferred demo and no regressions in a 1.0.2
> mustpass run.
For the series:
Reviewed-by: Dave Airlie
> ---
> src/amd/vulkan/radv_cmd_buffer.c | 51
> +++
> src/amd/vulkan/radv_
Signed-off-by: Karol Herbst
---
src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 8
1 file changed, 8 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
index 0a78c6a593..e60d21bc8a 10
Signed-off-by: Karol Herbst
v2: user bitfield_insert instead of bfi
rework switch helper macros
remove some lowering code (LoweringHelper is now used for this)
v3: add pack_half_2x16_split
add unpack_half_2x16_split_x/y
---
.../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 486 +++
v2: use mkOp
Signed-off-by: Karol Herbst
---
src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 15 +++
1 file changed, 15 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
index ee
v2: add vote_eq support
use the new subop intrinsic helper
add ballot
v3: add read_(first_)invocation
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 41 ++
1 file changed, 41 insertions(+)
diff --git a/src/gallium/drivers/nouveau
v4: use loadFrom helper
Signed-off-by: Karol Herbst
---
src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 13 +
1 file changed, 13 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
v3: fix compiler warnings
v4: use loadFrom helper
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 276 +++--
1 file changed, 258 insertions(+), 18 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
b/src/galli
v3: and load_output
v4: use smarter getIndirect helper
use new getSlotAddress helper
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 38 ++
1 file changed, 38 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from
v3: add workaround for RA issues
indirects have to be multiplied by 0x10
fix indirect access
v4: use smarter getIndirect helper
use storeTo helper
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 43 ++
1 file changed, 43 insert
Signed-off-by: Karol Herbst
---
src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 15 +++
1 file changed, 15 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
index 748d7740de..8573
v2: support more sys values
fixed a bug where for multi component reads all values ended up in x
v3: add load_patch_vertices_in
v4: add subgroup stuff
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 108 +
1 file changed, 108 insertion
a lot of those fields are not valid for a lot of tex ops. Not quite sure if
it's worth the effort to check for those or just keep it like that. It seems
to kind of work.
v2: reworked offset handling
add tex support with indirect R/S arguments
handle GLSL_SAMPLER_DIM_EXTERNAL
drop refer
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 19 +++
1 file changed, 19 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
index 7010e4e468..9c0
v4: use smarter getIndirect helper
use new getSlotAddress helper
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 25 ++
1 file changed, 25 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
b/src/gall
v4: use smarter getIndirect helper
use new getSlotAddress helper
use loadFrom helper
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 25 ++
1 file changed, 25 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_
v4: use loadFrom helper
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 86 ++
1 file changed, 86 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.
Signed-off-by: Karol Herbst
---
src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 11 +++
1 file changed, 11 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
index f7b51339c2..aeeca94f
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 255 -
1 file changed, 253 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
inde
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 24 ++
1 file changed, 24 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
index 58c627371b..ef0
we store those arrays in local memory and reserve some space for each of the
arrays. The arrays are stored in a packed format, because we know quite easily
the context of each index. We don't do that in TGSI so far.
This causes various issues to come up in the MemoryOpt pass, because ld/st with
in
v2: use new getIndirect helper
fixes symbols for 64 bit types
v4: use smarter getIndirect helper
simplify address calculation
use loadFrom helper
Signed-off-by: Karol Herbst
---
src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 10 ++
1 file changed, 10 insertions(+)
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 47 ++
1 file changed, 47 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
index f3cd22622d..6ea
v2: parse a few more fields
v3: add special handling for GL_ISOLINES
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 58 ++
1 file changed, 58 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
b/src/gall
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 20
1 file changed, 20 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
index 66ec4460d9..701
not all those nir options are actually required, it just made the work a
little easier.
v2: fix asserts
parse compute shaders
don't lower bitfield_insert
v3: fix memory leak
v4: don't lower fmod32
Signed-off-by: Karol Herbst
---
src/gallium/drivers/nouveau/Makefile.sources | 1 +
v2: add support for geometry shaders
set idx
add some missing mappings
fix for 64bit inputs/outputs
fix up some FP color output index messup
parse centroid flag
v3: fix arrays in outputs as well
fix input/ouput size calculation for tessellation shaders
v4: add getSlotAddress
this is mostly usefull for lazy IR converters not wanting to deal with 64 bit
lowering and other illegal stuff
Signed-off-by: Karol Herbst
---
src/gallium/drivers/nouveau/Makefile.sources | 2 +
.../nouveau/codegen/nv50_ir_lowering_helper.cpp| 250 +
.../nouveau/c
this helps with a bunch of piglit tests testing 64 bit types
Signed-off-by: Karol Herbst
---
src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
b/src/gallium/drivers/nouveau/c
v2: add helper function for indirects
v4: add new getIndirect overload for easier use
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 136 +
1 file changed, 136 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_n
v4: treat imul as unsigned
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 117 +
1 file changed, 117 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_
v2: allow for non debug builds as well
v3: move reading out env var more global
disable tg4 with multiple offsets with nir
disable caps for 64 bit types
Signed-off-by: Karol Herbst
---
src/gallium/drivers/nouveau/nouveau_screen.c | 4
src/gallium/drivers/nouveau/nouveau_screen.h
v2: add constant_folding
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 40 ++
1 file changed, 40 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir
this makes debugging the shader header a little easier
Signed-off-by: Karol Herbst
---
src/gallium/drivers/nouveau/nvc0/nvc0_program.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
index e615
significant changes to last series:
* fixing TF with GS for gallium nir drivers
* RA fix for 64 bit values and compounds
* completed support for 64 bit types
* random piglit fixes
Tested with unigine heaven/valley, gputest and RealisticRenderer
piglit run -x glx -x egl -x streaming-texture-leak -
From: Timothy Arceri
Allows nir drivers to either use a single or dual locations for
vs double inputs.
i965 uses dual locations for both OpenGL and Vulkan drivers, for
now gallium OpenGL drivers only use a single location.
The following patch will also make use of this option when
calling nir_s
From: Rob Clark
This was handled for VS, but not for GS.
Fixes for gallium drivers using nir:
spec@arb_gpu_shader5@arb_gpu_shader5-xfb-streams-without-invocations
spec@arb_gpu_shader5@arb_gpu_shader5-xfb-streams*
spec@arb_transform_feedback3@arb_transform_feedback3-ext_interleaved_two_bufs_gs*
s
From: Connor Abbott
In order to reduce moves when coalescing multiple registers into a
larger register, RA will try to coalesce MERGE instructions with their
definitions. For example, for something like this in GLSL:
uint a = ...;
uint b = ...;
uint64 x = packUint2x32(a, b);
The compiler will t
From: Timothy Arceri
First we move double_inputs_read into a vs struct in the union,
double_inputs_read is only used for vs inputs so this will
save space and also allows us to add a new double_inputs field.
We add the new field because c2acf97fcc9b changed the behaviour
of double_inputs_read, a
From: Timothy Arceri
c2acf97fcc9b32e changed the use of double_inputs_read to be
inconsitent with its previous meaning. Here we re-enable the
gather info code that was removed as the modified code from
c2acf97fcc9b32e now uses the double_inputs member rather than
double_inputs_read.
This change
v2: remove TGSI related bits
Signed-off-by: Karol Herbst
---
src/gallium/drivers/nouveau/Makefile.sources | 2 +
.../nouveau/codegen/nv50_ir_from_common.cpp| 107 +
.../drivers/nouveau/codegen/nv50_ir_from_common.h | 58 +++
.../drivers/nouveau/codeg
On 5 January 2018 at 01:14, Michal Srb wrote:
> From: =?UTF-8?q?Tom=C3=A1=C5=A1=20Chv=C3=A1tal?=
>
> Makes the egd_tables.py compatible with both python 2 and 3.
This appears to break the build here, I get a few () lines in the output.
I suspect print() needs to be print('')
Dave.
> ---
> sr
Tested with a modified deferred demo and no regressions in a 1.0.2
mustpass run.
---
src/amd/vulkan/radv_cmd_buffer.c | 51 +++
src/amd/vulkan/radv_device.c | 6 +
src/amd/vulkan/radv_extensions.py | 1 +
src/amd/vulkan/radv_pipeline.c| 35 ++
The EXT values are really large, e.g.
VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT = 199000, so 1 << value
is not going to fit into a 32-bit mask.
---
src/amd/vulkan/radv_cmd_buffer.c | 36 ++---
src/amd/vulkan/radv_pipeline.c | 49 +++-
From: Roland Scheidegger
We've seen some problems internally due to macro redefinition.
Fix this by adding HAVE_FUNC_ATTRIBUTE_NORETURN to c99_compat.h,
and defining it for msvc.
And avoid redefinition just in case.
---
include/c99_compat.h | 1 +
src/util/macros.h| 12
2 files
https://bugs.freedesktop.org/show_bug.cgi?id=104553
--- Comment #3 from Timothy Arceri ---
(In reply to Ilia Mirkin from comment #1)
> Ian Romanick (idr) wrote a test generator which generated random shader_test
> files with different ubo arrangements. It caught a lot of bugs back in the
> day, b
I tested the destination register type W => UW change to move 0x76543210V.
It fixed 1000+ piglit failures on Cannonlake.
On Tue, Jan 9, 2018 at 4:56 PM, Jason Ekstrand wrote:
> Gen 10 has a strange hardware bug involving V immediates with W types.
> It appears that a mov(8) g2<1>W 0x76543210V wil
From: Dave Airlie
---
docs/features.txt | 2 +-
src/gallium/drivers/r600/r600_pipe.c | 2 +-
src/gallium/drivers/r600/r600_shader.c | 29 ++---
src/gallium/drivers/r600/r600_sq.h | 3 ++-
4 files changed, 30 insertions(+), 6 deletions(-)
dif
Gen 10 has a strange hardware bug involving V immediates with W types.
It appears that a mov(8) g2<1>W 0x76543210V will actually result in g2
getting the value {3, 2, 1, 0, 3, 2, 1, 0}. In particular, the bottom
four nibbles are repeated instead of the top four being taken. (A mov
of 0x3210V
We already had to switch all of the W types to UW to prevent issues
with vector immediates on gen10. We may as well use unsigned types
everywhere.
---
src/intel/compiler/brw_fs.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/
On Tue, Jan 9, 2018 at 5:40 PM, Christopher Egert wrote:
> I'm not too familiar with gallium3d, but this fixes
> crashes with 3DMark2001 and GTA3 in wine-staging.
>
> This should be fixed properly in the future.
>
> Signed-off-by: Christopher Egert
> ---
> src/gallium/drivers/i915/i915_clear.c
On Mon, Nov 27, 2017 at 07:06:06PM -0800, Jason Ekstrand wrote:
> This is a bit less awkward than passing in the subpass because it means
> we don't have to extract the subpass id from the subpass.
> ---
> src/intel/vulkan/genX_cmd_buffer.c | 12 +---
> 1 file changed, 5 insertions(+), 7 d
On Mon, Nov 27, 2017 at 07:06:05PM -0800, Jason Ekstrand wrote:
> Having begin/end_subpass is a bit nicer than the begin/next/end hooks
> that Vulkan gives us.
> ---
> src/intel/vulkan/genX_cmd_buffer.c | 55
> +-
> 1 file changed, 31 insertions(+), 24 deletion
I'm not too familiar with gallium3d, but this fixes
crashes with 3DMark2001 and GTA3 in wine-staging.
This should be fixed properly in the future.
Signed-off-by: Christopher Egert
---
src/gallium/drivers/i915/i915_clear.c| 3 ++-
src/gallium/drivers/i915/i915_state_static.c | 4 +++-
2
On Mon, Nov 27, 2017 at 07:06:04PM -0800, Jason Ekstrand wrote:
> This seems slightly more correct because it means that the flushes
> happen before any clears or resolves implied by the subpass transition.
> ---
> src/intel/vulkan/genX_cmd_buffer.c | 8
> 1 file changed, 4 insertions(+),
Signed-off-by: Grazvydas Ignotas
---
src/util/crc32.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/util/crc32.c b/src/util/crc32.c
index 44d637c..f2e01c6 100644
--- a/src/util/crc32.c
+++ b/src/util/crc32.c
@@ -109,11 +109,11 @@ util_crc32_table[256] = {
* @sa http://
The next change wants to use some optional zlib functionality, however
not all platforms currently use it. Based on earlier Jordan Justen's
patches and their review feedback.
Signed-off-by: Grazvydas Ignotas
---
Android.common.mk | 1 +
configure.ac | 1 +
meson.build | 1 +
3 files c
zlib provides a faster slice-by-4 CRC32 implementation than the
traditional single byte lookup one used by mesa. As most supported
platforms now link zlib unconditionally, we can easily use it.
Improvement for a 1MB buffer (avg MB/s, n=100, zlib 1.2.8):
i5-6600KC2D E4500
mes
Reviewed-by: Bas Nieuwenhuizen
for the series.
On Tue, Jan 9, 2018 at 6:09 PM, Samuel Pitoiset
wrote:
> It makes more sense to rely on nir_intrinsic_load_push_constant
> instead of the pipeline layout.
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/common/ac_nir_to_llvm.c | 6 +++---
> s
Reviewed-by: Bas Nieuwenhuizen
for the series.
On Tue, Jan 9, 2018 at 4:01 PM, Samuel Pitoiset
wrote:
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_shader.c | 13 ++---
> 1 file changed, 10 insertions(+), 3 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_shader.c b/sr
On Mon, Jan 08, 2018 at 04:00:37PM -0800, Jason Ekstrand wrote:
> On Mon, Jan 8, 2018 at 2:29 PM, Nanley Chery wrote:
>
> > On Fri, Dec 15, 2017 at 02:53:29PM -0800, Rafael Antognolli wrote:
> > > gen10 can emit the clear color by setting it on a buffer somewhere, and
> > > then adding only the a
On Tue, Jan 09, 2018 at 11:26:26AM -0800, Jason Ekstrand wrote:
> On Tue, Jan 9, 2018 at 10:33 AM, Nanley Chery wrote:
>
> > On Mon, Jan 08, 2018 at 04:03:47PM -0800, Jason Ekstrand wrote:
> > > On Mon, Jan 8, 2018 at 3:00 PM, Nanley Chery
> > wrote:
> > >
> > > > On Fri, Dec 15, 2017 at 02:53:3
On Mon, Jan 08, 2018 at 04:33:25PM -0800, Rafael Antognolli wrote:
> On Mon, Jan 08, 2018 at 04:03:47PM -0800, Jason Ekstrand wrote:
> > On Mon, Jan 8, 2018 at 3:00 PM, Nanley Chery wrote:
> >
> > On Fri, Dec 15, 2017 at 02:53:30PM -0800, Rafael Antognolli wrote:
> > > On Gen10+, if we us
More Coffee Lake PCI IDs have been added to the spec.
Cc: Rodrigo Vivi
Signed-off-by: Anuj Phogat
---
include/pci_ids/i965_pci_ids.h | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h
index 0dd01a4343..96
Matt Turner writes:
> On Mon, Jan 8, 2018 at 5:01 PM, Scott D Phillips
> wrote:
>> Matt Turner writes:
>>
>>> Some cases weren't handled, such as stride 4 which is needed for 64-bit
>>> operations. Presumably fixes the assertion failure mentioned in commit
>>> 2d0457203871 (Revert "i965/fs: Use
On Mon, Jan 8, 2018 at 5:01 PM, Scott D Phillips
wrote:
> Matt Turner writes:
>
>> Some cases weren't handled, such as stride 4 which is needed for 64-bit
>> operations. Presumably fixes the assertion failure mentioned in commit
>> 2d0457203871 (Revert "i965/fs: Use align1 mode on ternary instruc
On Tue, Jan 9, 2018 at 10:33 AM, Nanley Chery wrote:
> On Mon, Jan 08, 2018 at 04:03:47PM -0800, Jason Ekstrand wrote:
> > On Mon, Jan 8, 2018 at 3:00 PM, Nanley Chery
> wrote:
> >
> > > On Fri, Dec 15, 2017 at 02:53:30PM -0800, Rafael Antognolli wrote:
> > > > On Gen10+, if we use the clear sta
On Mon, Jan 08, 2018 at 04:03:47PM -0800, Jason Ekstrand wrote:
> On Mon, Jan 8, 2018 at 3:00 PM, Nanley Chery wrote:
>
> > On Fri, Dec 15, 2017 at 02:53:30PM -0800, Rafael Antognolli wrote:
> > > On Gen10+, if we use the clear state address field in the surface state
> > > instead of the clear c
On Monday, January 8, 2018 3:00:30 PM PST Rafael Antognolli wrote:
> On Thu, Jan 04, 2018 at 11:36:48AM -0800, Kenneth Graunke wrote:
> > Apparently, Geminilake requires you to whack a chicken bit to select
> > either compute or tessellation mode for barriers. The recommendation
> > is to switch b
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