If we free the bo, then the PTE may get deallocated immediately. We have
to make sure that the submission includes a ref to the old bo so that it
remains mapped for the duration of the command execution.
Signed-off-by: Ilia Mirkin
---
v1 -> v2:
Ben pointed out that not deleting the BO is not e
Am 05.01.2018 um 02:45 schrieb Marek Olšák:
> On Thu, Jan 4, 2018 at 2:46 AM, Roland Scheidegger wrote:
>> Deos AMD degrade these chips to d3d10.1 on windows?
>> Just asking because d3d11 requires 8x msaa ;-).
>>
>> (But I won't say what I think about this patch...)
>
> It's legal in GL 4.5.
No
On 04/01/18 16:16, Dieter Nützel wrote:
Hello Tim,
this third version didn't make it into Patchwork.
Do you have a pointer?
That's odd. I've just pushed all but the last three patches to master :)
Thanks and a
Happy New Year
to you!
Happy New year.
Dieter
Am 03.01.2018 06:04, schrieb
Ping!
On 08/12/17 20:57, Timothy Arceri wrote:
We will need this for ARB_get_program_binary binary support.
---
src/mesa/state_tracker/st_program.c | 21 -
src/mesa/state_tracker/st_program.h | 12
src/mesa/state_tracker/st_shader_cache.c | 15 +
On Thu, Jan 4, 2018 at 2:46 AM, Roland Scheidegger wrote:
> Deos AMD degrade these chips to d3d10.1 on windows?
> Just asking because d3d11 requires 8x msaa ;-).
>
> (But I won't say what I think about this patch...)
It's legal in GL 4.5.
Marek
___
mes
On Thu, Jan 4, 2018 at 10:25 AM, Samuel Pitoiset
wrote:
> How about performance?
>
> Few weeks ago, I fixed a bug (5f81a43535e8512cef26ea3dcd1e3a489bd5a1bb)
> which affected F1 2017 and DOW3 on RADV, and it was also a nice performance
> boost, this is why I'm asking.
No idea. This just decreases
On Thu, Jan 4, 2018 at 8:36 PM, Ian Romanick wrote:
> If nobody uses this method, removing it seems fine. Does this imply
> that nobody implements an accelerated glGetCompressedTexSubImage, or is
> the acceleration just implemented differently (in a way that I don't
> recall off the top of my hea
Quoting Igor Gnatenko (2018-01-04 13:43:51)
> -BEGIN PGP SIGNED MESSAGE-
> Hash: SHA256
>
> On Thu, 2018-01-04 at 10:28 -0800, Dylan Baker wrote:
> > This patch adds a complete meson build system, including tests and
> > install. It has the necessary hooks to allow it be used as a subproje
Reviewed-by: Jason Ekstrand
Ken?
On Wed, Jan 3, 2018 at 6:55 PM, Iago Toral Quiroga
wrote:
> Although on gen8+ platforms we can in theory use 3DSTATE_VF_SGVS
> to put these beyond the last vertex element it seems that we still
> need to allocate the SVGS element, otherwise we have observed cas
Reviewed-by: Samuel Pitoiset
On 01/04/2018 07:49 PM, Marek Olšák wrote:
From: Marek Olšák
---
src/gallium/drivers/radeonsi/si_pm4.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_pm4.c
b/src/gallium/drivers/radeonsi/si_pm4.c
index 9
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA256
On Thu, 2018-01-04 at 10:28 -0800, Dylan Baker wrote:
> This patch adds a complete meson build system, including tests and
> install. It has the necessary hooks to allow it be used as a subproject
> for other meson based builds such as mesa.
Builds
On January 4, 2018 14:21:17 Ilia Mirkin wrote:
On Thu, Jan 4, 2018 at 3:07 PM, Jason Ekstrand wrote:
On January 4, 2018 14:02:25 Ilia Mirkin wrote:
On Thu, Jan 4, 2018 at 2:57 PM, Karol Herbst wrote:
On Thu, Jan 4, 2018 at 8:56 PM, Jason Ekstrand
wrote:
What is the nature of the imme
On Thu, Jan 4, 2018 at 3:07 PM, Jason Ekstrand wrote:
> On January 4, 2018 14:02:25 Ilia Mirkin wrote:
>
>> On Thu, Jan 4, 2018 at 2:57 PM, Karol Herbst wrote:
>>>
>>> On Thu, Jan 4, 2018 at 8:56 PM, Jason Ekstrand
>>> wrote:
What is the nature of the immediate problem? We may have a
On January 4, 2018 14:02:25 Ilia Mirkin wrote:
On Thu, Jan 4, 2018 at 2:57 PM, Karol Herbst wrote:
On Thu, Jan 4, 2018 at 8:56 PM, Jason Ekstrand wrote:
What is the nature of the immediate problem? We may have a similar issue.
we don't do rescheduling, so all the immediates are at the t
On Thu, Jan 4, 2018 at 2:57 PM, Karol Herbst wrote:
> On Thu, Jan 4, 2018 at 8:56 PM, Jason Ekstrand wrote:
>> What is the nature of the immediate problem? We may have a similar issue.
>
> we don't do rescheduling, so all the immediates are at the top of the shader.
The implication being that
On January 4, 2018 13:58:00 Karol Herbst wrote:
On Thu, Jan 4, 2018 at 8:56 PM, Jason Ekstrand wrote:
On January 4, 2018 12:51:15 Karol Herbst wrote:
On Thu, Jan 4, 2018 at 7:06 PM, Ilia Mirkin wrote:
On Thu, Jan 4, 2018 at 10:01 AM, Karol Herbst wrote:
significant changes to last se
On Thu, Jan 4, 2018 at 8:56 PM, Jason Ekstrand wrote:
> On January 4, 2018 12:51:15 Karol Herbst wrote:
>
>> On Thu, Jan 4, 2018 at 7:06 PM, Ilia Mirkin wrote:
>>>
>>> On Thu, Jan 4, 2018 at 10:01 AM, Karol Herbst wrote:
significant changes to last series:
* arb_gpu_shader5 inter
On January 4, 2018 12:51:15 Karol Herbst wrote:
On Thu, Jan 4, 2018 at 7:06 PM, Ilia Mirkin wrote:
On Thu, Jan 4, 2018 at 10:01 AM, Karol Herbst wrote:
significant changes to last series:
* arb_gpu_shader5 interpolateat* (those nir ops don't map well to nvir)
no good plan on how to proper
The XML is usually organized as
It looks like the 4.6 XML already doesn't follow that, so I won't give
you grief about not using that organization in this patch either. I
would, however, accept a follow-up patch that moves all the enums to the
top of the block. :D
Either way, this p
On 01/03/2018 01:27 PM, Jason Ekstrand wrote:
> This patch looks good in isolation and you can have my rb. However,
> this all a bit concerning and it makes me wonder if we're papering over
> the real bug.
It may be a bit of both. There's also some debate in the bugzilla about
whether or not thi
Apparently, Geminilake requires you to whack a chicken bit to select
either compute or tessellation mode for barriers. The recommendation
is to switch between them at PIPELINE_SELECT time.
We may not need to do this all the time, but I don't know that it hurts
either. PIPELINE_SELECT is already
If nobody uses this method, removing it seems fine. Does this imply
that nobody implements an accelerated glGetCompressedTexSubImage, or is
the acceleration just implemented differently (in a way that I don't
recall off the top of my head)?
On 01/03/2018 01:50 PM, Marek Olšák wrote:
> From: Marek
On 01/04/2018 08:18 AM, Alejandro Piñeiro wrote:
> Used to handle how many ubo you can define on the context. Minimimum
> defined as 36 on ARB_uniform_buffer_object spec, up to 84 on OpenGL
> 4.6 (12 per stage at each moment).
> ---
> src/compiler/glsl/standalone.cpp | 4
> 1 file changed, 4
Reviewed-by: Bruce Cherniak
> On Jan 4, 2018, at 10:33 AM, Tim Rowley wrote:
>
> Should be 0x8000 instead of 0x800.
>
> Cc: mesa-sta...@lists.freedesktop.org
> ---
> src/gallium/drivers/swr/rasterizer/common/simdlib_128_avx512.inl | 2 +-
> src/gallium/drivers/swr/rasterizer/common/simd
On Thu, Jan 4, 2018 at 1:49 PM, Marek Olšák wrote:
> From: Marek Olšák
>
Reviewed-by: Alex Deucher
> ---
> src/gallium/drivers/radeonsi/si_pm4.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_pm4.c
> b/src/gallium/drivers/radeonsi
Using a gather for elements less than 32-bits in size can cause
pagefaults when loading the last elements in a page-aligned-sized
buffer.
---
.../drivers/swr/rasterizer/jitter/fetch_jit.cpp| 61 +-
1 file changed, 60 insertions(+), 1 deletion(-)
diff --git a/src/gallium/dr
---
.../drivers/swr/rasterizer/jitter/builder.cpp | 76 +-
.../drivers/swr/rasterizer/jitter/builder.h| 45 +++---
.../drivers/swr/rasterizer/jitter/builder_misc.cpp | 133
.../drivers/swr/rasterizer/jitter/builder_misc.h | 50 +++---
.../drivers/swr/rast
Results in far smaller and useful IR output.
---
.../swr/rasterizer/codegen/templates/gen_llvm.hpp | 23 ++
1 file changed, 15 insertions(+), 8 deletions(-)
diff --git a/src/gallium/drivers/swr/rasterizer/codegen/templates/gen_llvm.hpp
b/src/gallium/drivers/swr/rasterizer/co
Bake in USE_SIMD16_BUILDER code paths (for USE_SIMD16_SHADER defined),
remove USE_SIMD16_BUILDER define, remove deprecated psuedo-SIMD16 code
paths.
---
.../drivers/swr/rasterizer/jitter/fetch_jit.cpp| 1118 +++-
1 file changed, 383 insertions(+), 735 deletions(-)
diff --git a
---
src/gallium/drivers/swr/Makefile.sources | 1 +
.../drivers/swr/rasterizer/jitter/JitManager.cpp | 36 +-
.../drivers/swr/rasterizer/jitter/JitManager.h | 46 +--
.../drivers/swr/rasterizer/jitter/blend_jit.cpp| 3 +-
.../drivers/swr/rasterizer/jitter/builder.
Highlights include simd16 cleanup (renaming and removing old
codepaths), fixing a potential crash with the fetch shader, and code
cleanups.
Tim Rowley (6):
swr/rast: SIMD16 builder - cleanup naming (simd2 -> simd16)
swr/rast: shuffle header files for msvc pre-compiled header usage
swr/rast:
Allows for call-stack and exception handling for jitted functions.
---
src/gallium/drivers/swr/rasterizer/jitter/JitManager.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/swr/rasterizer/jitter/JitManager.cpp
b/src/gallium/drivers/swr/rasterizer/jit
Reviewed-by: Bas Nieuwenhuizen
On Thu, Dec 28, 2017 at 10:55 PM, Samuel Pitoiset
wrote:
> Similar to RadeonSI.
>
> This fixes:
> dEQP-VK.image.texel_view_compatible.graphic.basic.attachment_read.bc*r16g16b16a16_sfloat
> dEQP-VK.image.extended_usage_bit.attachment_write.r16_sfloat
>
> Signed-off-
On Thu, Jan 4, 2018 at 7:06 PM, Ilia Mirkin wrote:
> On Thu, Jan 4, 2018 at 10:01 AM, Karol Herbst wrote:
>> significant changes to last series:
>> * arb_gpu_shader5 interpolateat* (those nir ops don't map well to nvir)
>> no good plan on how to properly implement those
>
> What's the issue? Th
From: Marek Olšák
---
src/gallium/drivers/radeonsi/si_pm4.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_pm4.c
b/src/gallium/drivers/radeonsi/si_pm4.c
index 96e4e1d..06b3fe8 100644
--- a/src/gallium/drivers/radeonsi/si_pm4.c
+++ b/src/g
This is a very good series. Patches 18 and 19 need some tiny changes.
With my comments on patches 8 and 12 addressed:
Patch 1-17, 20 are:
Reviewed-by: Marek Olšák
Marek
On Wed, Jan 3, 2018 at 6:04 AM, Timothy Arceri wrote:
> Simplifies the logic a little and asserts index is 0.
>
> Suggested
On Wed, Jan 3, 2018 at 6:04 AM, Timothy Arceri wrote:
> Fixes the following piglit tests in radeonsi:
>
> vs-tcs-tes-tessinner-tessouter-inputs-quads.shader_test
> vs-tcs-tes-tessinner-tessouter-inputs-tris.shader_test
> vs-tes-tessinner-tessouter-inputs-quads.shader_test
> vs-tes-tessinner-tessou
This patch adds a complete meson build system, including tests and
install. It has the necessary hooks to allow it be used as a subproject
for other meson based builds such as mesa.
v4: - fix freedreno kgls check
Signed-off-by: Dylan Baker
---
.editorconfig | 4 +-
amdgpu/.edito
Signed-off-by: Dylan Baker
---
README | 21 ++---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/README b/README
index 26cab9d..58e55bc 100644
--- a/README
+++ b/README
@@ -15,9 +15,24 @@ with an older kernel.
Compiling
-
-libdrm is a standard autot
This is a third iteration of the meson build system for libdrm. This
version is significantly cleaned up from the last version and uses a
style more like the build system in mesa.
It builds all of the drivers and tests, and the tests can be run via
`ninja test`.
It has support for being used as a
Signed-off-by: Dylan Baker
---
Makefile.am | 30 +-
1 file changed, 29 insertions(+), 1 deletion(-)
diff --git a/Makefile.am b/Makefile.am
index 7b86214..66f70ca 100644
--- a/Makefile.am
+++ b/Makefile.am
@@ -135,7 +135,35 @@ if HAVE_VMWGFX
klibdrminclude_HEADERS +=
If we have a color attachment, but its writes are masked, this would
have still returned true. This is inconsistent with how HasWriteableRT
in 3DSTATE_PS_BLEND is set, which does take the mask into account.
This could lead to PixelShaderHasUAV not being set in 3DSTATE_PS_EXTRA
if the fragment shad
On Thu, Jan 4, 2018 at 10:01 AM, Karol Herbst wrote:
> significant changes to last series:
> * arb_gpu_shader5 interpolateat* (those nir ops don't map well to nvir)
> no good plan on how to properly implement those
What's the issue? They should map as well as the TGSI ones. (Since the
TGSI ones
On Wed, Jan 3, 2018 at 6:04 AM, Timothy Arceri wrote:
> Reviewed-by: Nicolai Hähnle
> ---
> src/gallium/drivers/radeonsi/si_shader_nir.c | 29
>
> 1 file changed, 29 insertions(+)
>
> diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c
> b/src/gallium/drivers
On Wed, Jan 3, 2018 at 6:04 AM, Timothy Arceri wrote:
> Reviewed-by: Nicolai Hähnle
> ---
> src/gallium/drivers/radeonsi/si_shader.c | 124
> +++
> 1 file changed, 124 insertions(+)
>
> diff --git a/src/gallium/drivers/radeonsi/si_shader.c
> b/src/gallium/drivers/ra
On January 4, 2018 11:50:12 Karol Herbst wrote:
On Thu, Jan 4, 2018 at 6:39 PM, Jason Ekstrand wrote:
I'm fairly pleased that you were able to get this far with only 3k lines.
How much is that compared to your TGSI consumer?
around 4,3k, but keep in mind, that we really only want to conve
---
This is just a rebase of the patch with a minor conflict resolution.
src/mapi/glapi/gen/GL4x.xml | 22 ++
1 file changed, 22 insertions(+)
diff --git a/src/mapi/glapi/gen/GL4x.xml b/src/mapi/glapi/gen/GL4x.xml
index 0a80941..4b2703c 100644
--- a/src/mapi/glapi/gen/GL4x.x
On Thu, Jan 4, 2018 at 6:39 PM, Jason Ekstrand wrote:
> I'm fairly pleased that you were able to get this far with only 3k lines.
> How much is that compared to your TGSI consumer?
>
>
around 4,3k, but keep in mind, that we really only want to convert
things here and all the RA, optimizations and
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/si_cmd_buffer.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index 7d75d69a9a..9f68d3530e 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_
I'm fairly pleased that you were able to get this far with only 3k lines.
How much is that compared to your TGSI consumer?
On January 4, 2018 09:02:24 Karol Herbst wrote:
significant changes to last series:
* support for geometry, tessellation and compute shaders
* support for more intrinsi
Passes
dEQP-VK.api.smoke.*
dEQP-VK.wsi.android.*
with android-cts-7.1_r12 .
Unlike the initial anv implementation this does
use syncobjs instead of waiting on the CPU.
This is missing meson build coverage for now.
One possible todo is that linux 4.15 now has a
sycall that allows us to expor
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_device.c | 2 ++
src/amd/vulkan/radv_private.h | 1 +
src/amd/vulkan/radv_shader.c | 5 -
3 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 5f78af624b..528d35
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_descriptor_set.c | 6 --
src/amd/vulkan/radv_device.c | 4 +++-
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/src/amd/vulkan/radv_descriptor_set.c
b/src/amd/vulkan/radv_descriptor_set.c
index e815939a67..19a560a6
Needed for the following commit.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c | 40 +++
1 file changed, 23 insertions(+), 17 deletions(-)
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c
b/src/amd/vulkan/winsys/amdgpu/radv_a
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_radeon_winsys.h | 1 +
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c | 4 +++-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_radeon_winsys.h
b/src/amd/vulkan/radv_radeon_winsys.h
index 45f58f063a
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c | 17 +++--
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
index 4578a9b548..0ee56f9144 10064
If we import an image, we might not have space in the
buffer for CMASK, even though it is compatible.
---
src/amd/vulkan/radv_image.c | 43 ---
src/amd/vulkan/radv_private.h | 1 +
2 files changed, 25 insertions(+), 19 deletions(-)
diff --git a/src/amd/v
---
src/amd/vulkan/Makefile.am | 6 +-
src/amd/vulkan/radv_entrypoints_gen.py | 4 +++-
src/amd/vulkan/radv_extensions.py | 1 +
3 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/src/amd/vulkan/Makefile.am b/src/amd/vulkan/Makefile.am
index 6b352aebf9..e1a04e8c7f
On 2018-01-04 12:33 PM, Marek Olšák wrote:
Is the renaming necessary? It looks like everything would be fine if
we used the "fence" name for semaphores.
The rename was requested by nha. We could keep going with the fences
name. Or we could do the whole rename afterwards. I'm fine with eith
On Thursday, 2018-01-04 10:17:49 -0600, Rob Herring wrote:
> On Thu, Jan 4, 2018 at 8:16 AM, Eric Engestrom
> wrote:
> > On Wednesday, 2018-01-03 10:28:37 -0600, Rob Herring wrote:
> >> Commit 2f421651aca9 ("egl: let each platform decided how to handle
> >> LIBGL_ALWAYS_SOFTWARE") broke the build
Is the renaming necessary? It looks like everything would be fine if
we used the "fence" name for semaphores.
Marek
On Fri, Dec 22, 2017 at 1:41 AM, Andres Rodriguez wrote:
> Rename fences -> semaphores in preparation for upgrading fence
> functionality.
>
> This series renames the following sym
Reviewed-by: Marek Olšák
Marek
On Thu, Jan 4, 2018 at 4:01 PM, Karol Herbst wrote:
> this is enough to get tessellation working in Unigine heaven
>
> Signed-off-by: Karol Herbst
> ---
> src/mesa/state_tracker/st_glsl_to_nir.cpp | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> di
Reviewed-by: Marek Olšák
Marek
On Thu, Jan 4, 2018 at 4:24 PM, Samuel Pitoiset
wrote:
> This might decrease VGPR spilling, because we no longer
> have to use v4i32 for 2D fetches when level == 0. We now
> use v2i32 for those cases.
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/common/ac_
With the comments below addressed, this patch is
Reviewed-by: Pierre Moreau
On 2018-01-04 — 16:01, Karol Herbst wrote:
> v2: remove TGSI related bits
>
> Signed-off-by: Karol Herbst
> ---
> src/gallium/drivers/nouveau/Makefile.sources | 2 +
> .../nouveau/codegen/nv50_ir_from_common.c
On Thursday, 2017-12-21 04:05:59 +, co...@sdf.org wrote:
> On Wed, Dec 20, 2017 at 09:54:09AM -0600, Rob Herring wrote:
> > Android could be added here. Android has had getprogname since
> > Lollipop and we don't support versions older than that. It could be a
> > follow-on patch too.
>
> Atta
Should be 0x8000 instead of 0x800.
Cc: mesa-sta...@lists.freedesktop.org
---
src/gallium/drivers/swr/rasterizer/common/simdlib_128_avx512.inl | 2 +-
src/gallium/drivers/swr/rasterizer/common/simdlib_256_avx512.inl | 2 +-
src/gallium/drivers/swr/rasterizer/common/simdlib_512_avx512.inl |
Using 4, as it is the default value on mesa. See mesa/main/config.h
and the following commit that introduced the value:
15ac66e331abdab12e882d80a6b4f647bc905298
---
src/compiler/glsl/standalone.cpp | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/compiler/glsl/standalone.cpp b/src/compil
Used to handle how many ubo you can define on the context. Minimimum
defined as 36 on ARB_uniform_buffer_object spec, up to 84 on OpenGL
4.6 (12 per stage at each moment).
---
src/compiler/glsl/standalone.cpp | 4
1 file changed, 4 insertions(+)
diff --git a/src/compiler/glsl/standalone.cpp
ARB_transform_feedback3 sets a minimum of 1, ARB_gpu_shader5 a minimum
of 4. It shouldn't matter too much, so choosing the later.
---
src/compiler/glsl/standalone.cpp | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/compiler/glsl/standalone.cpp b/src/compiler/glsl/standalone.cpp
index 34
Using a shader as simple as this:
layout(location=1) out vec4 outVar;
layout(binding=2) uniform U
{
vec4 a;
};
void main()
{
outVar = a;
}
Start to complains because MaxUniformBufferBindings, MaxVertexStreams
and MaxTransformFeedbackBuffers has values too small (0, -1, etc)
Seem
Every now and then I execute the standalone compiler, get the
non-version error, and need to remember what I'm doing wrong
---
src/compiler/glsl/main.cpp | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/compiler/glsl/main.cpp b/src/compiler/glsl/main.cpp
index 123e41f9dc
On Thu, Jan 4, 2018 at 8:16 AM, Eric Engestrom
wrote:
> On Wednesday, 2018-01-03 10:28:37 -0600, Rob Herring wrote:
>> Commit 2f421651aca9 ("egl: let each platform decided how to handle
>> LIBGL_ALWAYS_SOFTWARE") broke the build due to copy-n-paste of misnamed
>> function parameter.:
>>
>> src/egl
Reviewed-by: Bas Nieuwenhuizen
On Thu, Jan 4, 2018 at 4:24 PM, Samuel Pitoiset
wrote:
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_cmd_buffer.c | 7 ++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/src/amd/vulkan/radv_cmd_buffer.c
> b/src/amd/vulkan/ra
On Thu, Jan 4, 2018 at 4:43 AM, Mao, David wrote:
> Hi Bas,
> AMD does not support ETC2 officially on the GFX9.
> It would be risky for Radv to export that feature for gfx9 family.
> Anyway, t’s just a heads up, and it is up to you to make the final call.
> FYI: AMDVLK and proprietary AMD vulkan d
On Fri, 2017-12-22 at 21:09 +0900, Tomasz Figa wrote:
> On Fri, Dec 22, 2017 at 10:09 AM, Gurchetan Singh
> wrote:
> > So the plan is for alloc_handle_t to not be sub-classed by the
> > implementations, but have all necessary information that an
> > implementation
> > would need?
> >
> > If so, h
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_cmd_buffer.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 6dc80acef0..a6975097b9 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/am
This might decrease VGPR spilling, because we no longer
have to use v4i32 for 2D fetches when level == 0. We now
use v2i32 for those cases.
Signed-off-by: Samuel Pitoiset
---
src/amd/common/ac_nir_to_llvm.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/amd/common/ac_
From: =?UTF-8?q?Tom=C3=A1=C5=A1=20Chv=C3=A1tal?=
Makes the egd_tables.py compatible with both python 2 and 3.
---
src/gallium/drivers/r600/egd_tables.py | 52 +-
1 file changed, 26 insertions(+), 26 deletions(-)
diff --git a/src/gallium/drivers/r600/egd_tables.py
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 97 ++
1 file changed, 97 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
index 18b998d22c..9d3
Signed-off-by: Karol Herbst
---
src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 11 +++
1 file changed, 11 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
index 9f865bad10..c0783bed
Signed-off-by: Karol Herbst
---
src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 14 ++
1 file changed, 14 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
index 252092a391..18b99
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 287 +++--
1 file changed, 269 insertions(+), 18 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
ind
v2: add vote_eq support
use the new subop intrinsic helper
add ballot
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 25 ++
1 file changed, 25 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
b
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 31 ++
1 file changed, 31 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
index 1ac5436153..252
we store those arrays in local memory and reserve some space for each of the
arrays. The arrays are stored in a packed format, because we know quite easily
the context of each index. We don't do that in TGSI so far.
This causes various issues to come up in the MemoryOpt pass, because ld/st with
in
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 24 ++
1 file changed, 24 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
index 9391f57f87..cb8
a lot of those fields are not valid for a lot of tex ops. Not quite sure if
it's worth the effort to check for those or just keep it like that. It seems
to kind of work.
v2: reworked offset handling
add tex support with indirect R/S arguments
handle GLSL_SAMPLER_DIM_EXTERNAL
drop refer
v2: use mkOp
Signed-off-by: Karol Herbst
---
src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 15 +++
1 file changed, 15 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
index a1
v2: support more sys values
fixed a bug where for multi component reads all values ended up in x
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 81 ++
1 file changed, 81 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/
v2: use new getIndirect helper
fixes symbols for 64 bit types
Signed-off-by: Karol Herbst
---
src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 16
1 file changed, 16 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
b/src/gallium
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 30 ++
1 file changed, 30 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
index 8a3b897e26..679
Signed-off-by: Karol Herbst
v2: user bitfield_insert instead of bfi
rework switch helper macros
remove some lowering code (LoweringHelper is now used for this)
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 468 -
1 file changed,
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir_from_nir.cpp| 17 +
1 file changed, 17 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
index eeefadbfd0..e84
Signed-off-by: Karol Herbst
---
src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 15 +++
1 file changed, 15 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
index 6795baa704..d5b6
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 47 ++
1 file changed, 47 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
index 9835b916bf..8a3
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 20
1 file changed, 20 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
index 82645f5ef1..eee
v2: add support for geometry shaders
set idx
add some missing mappings
fix for 64bit inputs/outputs
fix up some FP color output index messup
parse centroid flag
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 531 +
1 f
this helps with a bunch of piglit tests testing 64 bit types
Signed-off-by: Karol Herbst
---
src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
b/src/gallium/drivers/nouveau/c
v2: add helper function for indirects
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 125 +
1 file changed, 125 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
b/src/gallium/drivers/nouveau/codegen/nv
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 255 -
1 file changed, 253 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
inde
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