https://bugs.freedesktop.org/show_bug.cgi?id=102992
Bug ID: 102992
Summary: Fedora see two monitors as one.
Product: Mesa
Version: 17.1
Hardware: Other
OS: All
Status: NEW
Severity: normal
Priori
Hi,
AFAIK, for all shader types both binding table entry count and number of
samplers can be zero; the hardware uses those values to pre-fetch data. The
docs say one may wish to leave it at zero if there is a risk of state thrashing
if the number (for either) is large. FWIW, my main reason for
On 22/09/17 19:41, Juan A. Suarez Romero wrote:
On Fri, 2017-09-22 at 16:38 +1000, Timothy Arceri wrote:
On 22/09/17 05:10, Juan A. Suarez Romero wrote:
Hello list,
The candidate for the Mesa 17.1.10 is now available. Currently we have:
- 41 queued
- 0 nominated (outstanding)
- and 5
From: Dave Airlie
%9903 = OpImageSampleDrefExplicitLod %float %14616 %14315 %16081 Lod %float_0
%14616 = OpSampledImage %510 %8499 %13137
%278 = OpTypeImage %float 2D 1 0 0 1 Unknown
%510 = OpTypeSampledImage %278
%8499 = OpLoad %150 %4159
%150 = OpTypeImage %float 2D 0 0 0 1 Unknown
Is being
This will allow us to insert a nir linking step in brw_link_shader().
Reviewed-by: Kenneth Graunke
Reviewed-by: Eduardo Lima Mitev
---
src/mesa/drivers/dri/i965/brw_link.cpp | 14 ++
src/mesa/drivers/dri/i965/brw_program.c | 11 ---
2 files changed, 18 insertions(+), 7 dele
The initial helpers as support for removing unused varyings between
stages.
V2:
- made the io mask helper function into this file rather than
nir.h so it's not used elsewhere considering it doesn't handle
all corner cases.
- Use bitmask rather than hash table to handle tcs ouputs (Ken)
---
sr
Reviewed-by: Kenneth Graunke
Reviewed-by: Eduardo Lima Mitev
---
src/intel/compiler/brw_nir.c | 14 +++---
src/intel/compiler/brw_nir.h | 4
2 files changed, 11 insertions(+), 7 deletions(-)
diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
index ce21c016699
Will be used in nir link pass to decided if we can remove a varying
or not.
Reviewed-by: Kenneth Graunke
Reviewed-by: Eduardo Lima Mitev
---
src/compiler/glsl/glsl_to_nir.cpp | 1 +
src/compiler/nir/nir.h| 10 ++
2 files changed, 11 insertions(+)
diff --git a/src/compiler/
For now linking is just removing unused varyings between stages.
shader-db results BDW:
total instructions in shared programs: 13198288 -> 13191693 (-0.05%)
instructions in affected programs: 48325 -> 41730 (-13.65%)
helped: 473
HURT: 0
total cycles in shared programs: 541184926 -> 541159260 (-0
This will be used by the nir linking pass so that we don't remove
otherwise unused varyings.
Reviewed-by: Kenneth Graunke
Reviewed-by: Eduardo Lima Mitev
---
src/compiler/glsl/link_varyings.cpp | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/compiler/glsl/link_varyings.cpp
b/src/com
This will help us call gather info at a later point and allow us
to do some linking in nir.
Reviewed-by: Kenneth Graunke
Reviewed-by: Eduardo Lima Mitev
---
src/mesa/drivers/dri/i965/brw_program.c | 20 +---
src/mesa/drivers/dri/i965/brw_program.h | 3 +++
2 files changed, 16 i
On Tuesday, August 29, 2017 9:24:01 AM PDT Plamena Manolova wrote:
> We can implement ARB_indirect_parameters for i965 by
> taking advantage of the conditional rendering mechanism.
> This works by issuing maxdrawcount draw calls and using
> conditional rendering to predicate each of them with
> "dr
On 2017-09-25 05:46:32, Lionel Landwerlin wrote:
> I'm genuinely surprised we didn't noticed this problem before :|
Indeed. Did jenkins show any 'fixes' from this patch?
I think this patch should be handled separately from this RFC series.
Reviewed-by: Jordan Justen
> Fixes: 71bfb44005bf ("i96
On 2017-09-25 05:30:36, Rogovin, Kevin wrote:
> Hi,
>
> The value is the number of entries, not the size in bytes;
> BindingTableEntryCount for compute/media is programmed the same way
> as for all the other shader stages (where they too are divided by
> 4).
>
> FWIW, the hardware will work
On Tuesday, August 29, 2017 9:24:00 AM PDT Plamena Manolova wrote:
> brw_draw_prims needs to be refactored prior to
> ARB_indirect_parameters implementation.
>
> Signed-off-by: Plamena Manolova
> ---
> src/mesa/drivers/dri/i965/brw_draw.c | 343
> +++
> 1 file ch
On Sunday, September 24, 2017 4:56:00 PM PDT Timothy Arceri wrote:
> On 23/09/17 04:33, Kenneth Graunke wrote:
[snip]
> > This is duplicating the code in nir_gather_info.c pretty hard, but it
> > doesn't handle patch variables, or scalar arrays with var->data.compact
> > set (i.e. gl_ClipDistance a
On 26/09/17 08:47, Kenneth Graunke wrote:
On Tuesday, September 12, 2017 4:37:35 PM PDT Timothy Arceri wrote:
For now linking is just removing unused varyings between stages.
shader-db results BDW:
total instructions in shared programs: 13198288 -> 13191693 (-0.05%)
instructions in affected
On Tuesday, September 12, 2017 4:37:35 PM PDT Timothy Arceri wrote:
> For now linking is just removing unused varyings between stages.
>
> shader-db results BDW:
>
> total instructions in shared programs: 13198288 -> 13191693 (-0.05%)
> instructions in affected programs: 48325 -> 41730 (-13.65%)
On Tuesday, September 12, 2017 4:37:32 PM PDT Timothy Arceri wrote:
> This will help us call gather info at a later point and allow us
> to do some linking in nir.
> ---
> src/mesa/drivers/dri/i965/brw_program.c | 20 +---
> src/mesa/drivers/dri/i965/brw_program.h | 3 +++
> 2 fil
Swr caches fb contents in tiles. Those tiles are stored on a per-context
basis.
When switching contexts that share resources we need to make sure that
the tiles of the old context are being stored and the tiles of the new
context are being invalidated (marked as invalid, hence contents need
to be
No need to check if screen->pipe != pipe, so we can just assign it. Just do it.
---
src/gallium/drivers/swr/swr_state.cpp | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/src/gallium/drivers/swr/swr_state.cpp
b/src/gallium/drivers/swr/swr_state.cpp
index 893bd6e..c6da4fc 100
On Tue, Sep 26, 2017 at 6:21 AM, Tomasz Figa wrote:
> Hi Ian,
>
> On Tue, Sep 26, 2017 at 5:59 AM, Ian Romanick wrote:
>> On 09/25/2017 02:53 AM, Tomasz Figa wrote:
>>> Commit 259fc505454ea6a67aeacf6cdebf1398d9947759 added linker error for
>>> mismatching uniform precision, as required by GLES sp
We don't have vasprintf() on Windows so we need to implement it ourselves.
v2: compute actual length of output string, per Nicolai Hähnle.
---
src/util/u_string.h | 22 ++
1 file changed, 22 insertions(+)
diff --git a/src/util/u_string.h b/src/util/u_string.h
index e88e13f..4
---
src/gallium/auxiliary/util/u_log.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/gallium/auxiliary/util/u_log.c
b/src/gallium/auxiliary/util/u_log.c
index 359b3e1..dacbe05 100644
--- a/src/gallium/auxiliary/util/u_log.c
+++ b/src/gallium/auxiliary/util/u_log.c
@@ -
On Tuesday, September 12, 2017 4:37:31 PM PDT Timothy Arceri wrote:
> The initial helpers as support for removing unused varyings between
> stages.
> ---
> src/compiler/Makefile.sources | 1 +
> src/compiler/nir/nir.h | 6 ++
> src/compiler/nir/nir_linking_helpers.c |
On Mon, Sep 25, 2017 at 9:58 AM, Dylan Baker wrote:
> Hi Bas,
>
> I'll add a local workaround, but really I want to get this fix into meson
> proper
> (I wrote LLVM dependency handling for meson just for mesa). Does LLVM
> generally
> add "svn" to the end of the version if it's build from svn?
Hi Ian,
On Tue, Sep 26, 2017 at 5:59 AM, Ian Romanick wrote:
> On 09/25/2017 02:53 AM, Tomasz Figa wrote:
>> Commit 259fc505454ea6a67aeacf6cdebf1398d9947759 added linker error for
>> mismatching uniform precision, as required by GLES specification and
>> conformance test-suite.
>>
>> Several Andr
On 09/25/2017 02:53 AM, Tomasz Figa wrote:
> Commit 259fc505454ea6a67aeacf6cdebf1398d9947759 added linker error for
> mismatching uniform precision, as required by GLES specification and
> conformance test-suite.
>
> Several Android applications, including Forge of Empires, have shaders
> which vi
On September 25, 2017 11:46:18 AM Kenneth Graunke
wrote:
On Monday, September 25, 2017 8:05:29 AM PDT Chris Wilson wrote:
Quoting Jason Ekstrand (2017-09-24 22:53:04)
> I've got this a few times recently and it's really annoying. I don't know
> if this will fix anything or not but it may be
On 15/09/17 23:54, Jason Ekstrand wrote:
On Fri, Sep 15, 2017 at 7:11 AM, Lionel Landwerlin
mailto:lionel.g.landwer...@intel.com>>
wrote:
Signed-off-by: Lionel Landwerlin mailto:lionel.g.landwer...@intel.com>>
---
src/intel/vulkan/anv_descriptor_set.c | 107
+
On 18/09/17 20:27, Jason Ekstrand wrote:
On Sun, Sep 17, 2017 at 3:31 AM, Lionel Landwerlin
mailto:lionel.g.landwer...@intel.com>>
wrote:
On 15/09/17 23:36, Jason Ekstrand wrote:
struct anv_format_plane {
enum isl_format isl_format:16;
struct isl_swizzle
Mesa 17.1.10 is now available.
In this release we have:
In build and integration system, we add a dependency on libunwind when
running make distcheck, as this is optional for libgallium but we want
to catch any problem. As consequence, also force LLVM 3.3 in Travis
when building Gallium ST Other,
Patches 1 & 2: Reviewed-by: Jordan Justen
On 2017-09-24 15:09:48, Kenneth Graunke wrote:
> Embarassingly, someone enabled the ARB_shader_atomic_counter_ops
> extension for Gen7+ but never added the intrinsics to the switch
> statement in the vec4 backend, so they just hit an unreachable()
> call
Hi Bas,
I'll add a local workaround, but really I want to get this fix into meson proper
(I wrote LLVM dependency handling for meson just for mesa). Does LLVM generally
add "svn" to the end of the version if it's build from svn?
Dylan
Quoting Bas Nieuwenhuizen (2017-09-23 21:16:36)
> Hi Dylan,
>
Quoting Nicholas Miell (2017-09-23 21:17:48)
> On 09/23/2017 08:39 AM, Dylan Baker wrote:
> > diff --git a/meson_options.txt b/meson_options.txt
> > index e52cec31f11..854cba851d7 100644
> > --- a/meson_options.txt
> > +++ b/meson_options.txt
> > @@ -20,8 +20,10 @@
> >
> > option('platforms',
Quoting Kenneth Graunke (2017-09-25 17:46:11)
> On Monday, September 25, 2017 8:05:29 AM PDT Chris Wilson wrote:
> > Quoting Jason Ekstrand (2017-09-24 22:53:04)
> > > I've got this a few times recently and it's really annoying. I don't
> > > know
> > > if this will fix anything or not but it ma
https://bugs.freedesktop.org/show_bug.cgi?id=102980
Bug ID: 102980
Summary: weston crashes with egl use since wayland-drm:
constify the callbacks struct
Product: Mesa
Version: unspecified
Hardware: Other
OS:
Reviewed-by: Bruce Cherniak
> On Sep 21, 2017, at 7:46 PM, Tim Rowley wrote:
>
> Highlights: large change in the geometry shader api, cleanups.
>
> Tim Rowley (9):
> swr/rast: Add support for R10G10B10_FLOAT_A2_UNORM pixel format
> swr/rast: New GS state/context API
> swr/rast: Fetch compi
On Sep 25, 2017, at 11:31 AM, Rowley, Timothy O
mailto:timothy.o.row...@intel.com>> wrote:
Ok, made the following changes - want a full v2 commit, or ok to do this on
push?
I'm fine with doing it on push and don't need a full v2. It simply replaces a
couple magic numbers with their defines --
On Monday, September 25, 2017 8:05:29 AM PDT Chris Wilson wrote:
> Quoting Jason Ekstrand (2017-09-24 22:53:04)
> > I've got this a few times recently and it's really annoying. I don't know
> > if this will fix anything or not but it may be worth a go. I fear,
> > however, that ignoring an exec
Ok, made the following changes - want a full v2 commit, or ok to do this on
push?
--- a/src/gallium/drivers/swr/swr_shader.cpp
+++ b/src/gallium/drivers/swr/swr_shader.cpp
@@ -533,12 +533,12 @@ BuilderSWR::CompileGS(struct swr_context *ctx,
swr_jit_gs_key &key)
pGS->inputVertStride = pGS->nu
I think this is reasonable in the short term.. and looks like it was
what I intended to do, so:
Reviewed-by: Rob Clark
Doing better would require shuffling things around a bit so we could
look up the shader variant. Possibly moving some of this bookkeeping
into helper fxns that are called back
We do, based on the program... an ssbo may be marked as readonly. Not
sure if it's worth-while retrieving that info though.
On Mon, Sep 25, 2017 at 11:12 AM, Tomeu Vizoso
wrote:
> As the comments say, we don't have a way of knowing for sure that they
> will be only read, so mark them as written.
As the comments say, we don't have a way of knowing for sure that they
will be only read, so mark them as written.
Signed-off-by: Tomeu Vizoso
---
src/gallium/drivers/freedreno/freedreno_draw.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/freedreno/
Quoting Kenneth Graunke (2017-09-24 07:02:05)
> do_flush_locked isn't a great name - especially given that there's no
> locking going on in our code relating to execbuf.
Reviewed-by: Chris Wilson
-Chris
___
mesa-dev mailing list
mesa-dev@lists.freedeskto
Quoting Kenneth Graunke (2017-09-24 07:02:04)
> We have a nice utility function for this, which eliminates the need for
> locking stuff. This isn't really performance critical, but it's less
> code to use the atomic.
>
> p_atomic_inc_return does pre-increment rather than post-increment, so we
> c
Quoting Kenneth Graunke (2017-09-24 07:02:03)
> There's no real advantage or disadvantage here, it's just for stylistic
> consistency with the rest of the codebase.
Being consistent is its own reward.
Reviewed-by: Chris Wilson
-Chris
___
mesa-dev mailin
Quoting Jason Ekstrand (2017-09-24 22:53:04)
> I've got this a few times recently and it's really annoying. I don't know
> if this will fix anything or not but it may be worth a go. I fear,
> however, that ignoring an execbuf failure will lead to permanently
> corrupted rendering or even addit
Hi,
Ran several tens of rounds on 2 different 18 EU BXT devices with the
patch -> no hangs. Earlier that (internal) test-case always hung within
1-3 rounds.
Tested-by: Eero Tamminen
On 25.09.2017 16:39, Topi Pohjolainen wrote:
Fixes intermittent GPU hangs on Broxton with an Intel internal
Fixes intermittent GPU hangs on Broxton with an Intel internal
test case.
There are plenty of similar fragment shaders in piglit that do
not use any varyings and any uniforms. According to the
documentation special timing is needed between pipeline stages.
Apparently we just don't hit that with pi
I pushed the rest of the series.
See below for discussion on this patch.
On Wednesday, 2017-09-20 17:05:21 +, Jose Fonseca wrote:
> On 19/09/17 15:14, Eric Engestrom wrote:
> > Signed-off-by: Eric Engestrom
> > ---
> > scons/custom.py | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion
I'm genuinely surprised we didn't noticed this problem before :|
Fixes: 71bfb44005bf ("i965: Port brw_cs_state tracked state to genxml.")
Reviewed-by: Lionel Landwerlin
Cc: "17.2"
On 25/09/17 11:34, kevin.rogo...@intel.com wrote:
From: Kevin Rogovin
Signed-off-by: Kevin Rogovin
---
src/m
My bad, looks good :
Reviewed-by: Lionel Landwerlin
On 25/09/17 13:30, Rogovin, Kevin wrote:
Hi,
The value is the number of entries, not the size in bytes;
BindingTableEntryCount for compute/media is programmed the same way as for all
the other shader stages (where they too are divided by
Hi,
The value is the number of entries, not the size in bytes;
BindingTableEntryCount for compute/media is programmed the same way as for all
the other shader stages (where they too are divided by 4).
FWIW, the hardware will work without this patch because genX initializes the
value as 0. Wh
On 25/09/17 11:34, kevin.rogo...@intel.com wrote:
From: Kevin Rogovin
Signed-off-by: Kevin Rogovin
---
src/mesa/drivers/dri/i965/genX_state_upload.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c
b/src/mesa/drivers/dri/i965/genX_state_uplo
Reviewed-by: Lionel Landwerlin
On 25/09/17 11:34, kevin.rogo...@intel.com wrote:
From: Kevin Rogovin
Signed-off-by: Kevin Rogovin
---
src/intel/tools/disasm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/intel/tools/disasm.c b/src/intel/tools/disasm.c
index
This is needed since we don't update the number of viewports/scissors
when they are set dynamically (according to the spec). In the following
scenario:
* vkCmdSetViewport()
* vkCmdClearColorImage() (or any other meta operations)
The viewports/scissors weren't saved correctly because no pipeline
w
https://bugs.freedesktop.org/show_bug.cgi?id=102964
Sylvain BERTRAND changed:
What|Removed |Added
Resolution|--- |WORKSFORME
Status|NEW
On Mon, Sep 25, 2017 at 7:21 PM, Eric Engestrom
wrote:
> On Saturday, 2017-09-23 13:37:29 +0900, Tomasz Figa wrote:
>> On Wed, Sep 20, 2017 at 7:47 PM, Eric Engestrom
>> wrote:
>> > On Tuesday, 2017-09-19 17:19:59 +, Emil Velikov wrote:
>> >> From: Emil Velikov
>> >>
>> >> In order to build
From: Kevin Rogovin
Signed-off-by: Kevin Rogovin
---
src/intel/Makefile.tools.am| 6 +-
src/intel/tools/.gitignore | 1 +
.../tools/i965_batchbuffer_dump_show_json.cpp | 251 +
3 files changed, 257 insertions(+), 1 del
From: Kevin Rogovin
Signed-off-by: Kevin Rogovin
---
src/intel/Makefile.tools.am| 6 +-
src/intel/tools/.gitignore | 1 +
src/intel/tools/i965_batchbuffer_dump_show_xml.cpp | 215 +
3 files changed, 221 insertions(+), 1 del
From: Kevin Rogovin
Signed-off-by: Kevin Rogovin
---
src/intel/Makefile.tools.am | 21 ++-
src/intel/tools/.gitignore| 1 +
src/intel/tools/gen_shader_disassembler.c | 218 ++
3 files changed, 239 insertions(+), 1 deletion(-)
create
From: Kevin Rogovin
Signed-off-by: Kevin Rogovin
---
src/intel/tools/disasm.c | 6 +++---
src/intel/tools/gen_disasm.h | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/intel/tools/disasm.c b/src/intel/tools/disasm.c
index 251acd3..27f99e2 100644
--- a/src/intel/too
From: Kevin Rogovin
Signed-off-by: Kevin Rogovin
---
src/intel/compiler/brw_eu.c | 11 ++-
src/intel/compiler/brw_eu.h | 3 +++
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/src/intel/compiler/brw_eu.c b/src/intel/compiler/brw_eu.c
index b0bdc38..4fa40e8 100644
--- a/s
From: Kevin Rogovin
The length function is needed if one wishes to save GEN binary
shaders to file.
Signed-off-by: Kevin Rogovin
---
src/intel/tools/disasm.c | 7 +++
src/intel/tools/gen_disasm.h | 2 ++
2 files changed, 9 insertions(+)
diff --git a/src/intel/tools/disasm.c b/src/inte
From: Kevin Rogovin
Signed-off-by: Kevin Rogovin
---
src/intel/Makefile.tools.am | 5 ++
src/intel/tools/.gitignore | 1 +
src/intel/tools/i965_batchbuffer_dump_show.c | 129 +++
3 files changed, 135 insertions(+)
create mode 10064
From: Kevin Rogovin
Signed-off-by: Kevin Rogovin
---
src/intel/Makefile.tools.am | 8 ++
src/intel/tools/.gitignore| 1 +
src/intel/tools/i965_batchbuffer_logger_sh.in | 107 ++
3 files changed, 116 insertions(+)
create mode 100
From: Kevin Rogovin
Signed-off-by: Kevin Rogovin
---
src/intel/Makefile.tools.am | 4
1 file changed, 4 insertions(+)
diff --git a/src/intel/Makefile.tools.am b/src/intel/Makefile.tools.am
index 6e3e497..7845a57 100644
--- a/src/intel/Makefile.tools.am
+++ b/src/intel/Makefile.tools.am
@@
From: Kevin Rogovin
Signed-off-by: Kevin Rogovin
---
src/mesa/drivers/dri/i965/genX_state_upload.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c
b/src/mesa/drivers/dri/i965/genX_state_upload.c
index bbb47ea..32c7d22 100644
---
From: Kevin Rogovin
Without this fix, disassembling of GEN shaders with GPU commands
that the disassembler does not know would result in errors being
added to the annotator which would crash when more than one error
was added.
Signed-off-by: Kevin Rogovin
---
src/intel/compiler/intel_asm_annot
From: Kevin Rogovin
Signed-off-by: Kevin Rogovin
---
src/intel/tools/gen_disasm.h | 8
1 file changed, 8 insertions(+)
diff --git a/src/intel/tools/gen_disasm.h b/src/intel/tools/gen_disasm.h
index 24b56c9..d2764bb 100644
--- a/src/intel/tools/gen_disasm.h
+++ b/src/intel/tools/gen_di
From: Kevin Rogovin
Signed-off-by: Kevin Rogovin
---
src/intel/tools/disasm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/intel/tools/disasm.c b/src/intel/tools/disasm.c
index 361885b..251acd3 100644
--- a/src/intel/tools/disasm.c
+++ b/src/intel/tools/disasm.c
@
From: Kevin Rogovin
Without this patch, if a shader has errors, the disassembly of the
shader often stops after the first opcode that has errors.
Signed-off-by: Kevin Rogovin
---
src/intel/tools/disasm.c | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/src/inte
From: Kevin Rogovin
Signed-off-by: Kevin Rogovin
---
src/intel/common/gen_decoder.h | 7 +++
src/intel/common/gen_device_info.h | 8
2 files changed, 15 insertions(+)
diff --git a/src/intel/common/gen_decoder.h b/src/intel/common/gen_decoder.h
index cfc9f2e..1603336 100644
---
From: Kevin Rogovin
Signed-off-by: Kevin Rogovin
---
src/mesa/drivers/dri/i965/genX_state_upload.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c
b/src/mesa/drivers/dri/i965/genX_state_upload.c
index 6127616..bbb47ea 100644
--- a/src/mesa/driv
From: Kevin Rogovin
The interface for BatchbufferLogger is that it is active
only if it is LD_PRELOAD'ed. Thus, the i965 driver is to
use dlsym to see if it is there, and if so fetch the object
at intel_screen creation.
Signed-off-by: Kevin Rogovin
---
src/mesa/drivers/dri/i965/brw_bufmgr.c
From: Kevin Rogovin
The disassembler does not (and should not) be modifying the data.
Signed-off-by: Kevin Rogovin
---
src/intel/compiler/brw_eu.h | 2 +-
src/intel/compiler/brw_eu_validate.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/intel/compiler/brw
From: Kevin Rogovin
Define the driver interface for BatchbufferLogger. The
interface assumes that for any -thread- there is only
one batchbuffer to which commands are to be added. A
driver needs to provide the information on what is the
active batchbuffer on a calling thread and also a function
t
From: Kevin Rogovin
Define the output format of the BatchbufferLogger. The output
is a sequence of blocks where blocks can have member blocks
or values. The top level blocks come from the application
calling into the BatchBufferLogger when an GL/GLES API call
is started and returns.
Signed-off-b
From: Kevin Rogovin
Define the application interface to BatchbufferLogger. The
BatchbufferLogger needs from the application when a GL/GLES
API call is issues and returns. It will use this information
to correctly correlate batchbuffer additions to GL/GLES API
calls.
In addition, because the Batc
From: Kevin Rogovin
This patch series defines and implements a BatchbufferLogger
for Intel GEN. The main purpose of the BatchbufferLogger is
to strongly correlate API calls to data added to a batchbuffer.
In addition to this function, the BatchbufferLogger also tracks
GPU state (respecting HW con
On Saturday, 2017-09-23 13:37:29 +0900, Tomasz Figa wrote:
> On Wed, Sep 20, 2017 at 7:47 PM, Eric Engestrom
> wrote:
> > On Tuesday, 2017-09-19 17:19:59 +, Emil Velikov wrote:
> >> From: Emil Velikov
> >>
> >> In order to build EGL, one has to use shared glapi - libglapi.so.
> >>
> >> Thus t
Commit 259fc505454ea6a67aeacf6cdebf1398d9947759 added linker error for
mismatching uniform precision, as required by GLES specification and
conformance test-suite.
Several Android applications, including Forge of Empires, have shaders
which violate this rule, on a dead varying that will be elimina
On Sat, Sep 23, 2017 at 1:38 PM, Tomasz Figa wrote:
> On Wed, Sep 20, 2017 at 2:19 AM, Emil Velikov
> wrote:
>> From: Emil Velikov
>>
>> In order to build EGL, one has to use shared glapi - libglapi.so.
>>
>> Thus the dlopen/dlsym dance is no longer needed and we can link to the
>> library dire
https://bugs.freedesktop.org/show_bug.cgi?id=71124
Tapani Pälli changed:
What|Removed |Added
Resolution|--- |WORKSFORME
Status|NEW
On Fri, Aug 11, 2017 at 1:31 PM, Tomasz Figa wrote:
> On Fri, Aug 11, 2017 at 2:29 AM, Emil Velikov
> wrote:
>> On 10 August 2017 at 14:59, Tomasz Figa wrote:
>>> dri2_fallback_swap_interval() currently used to stub out swap interval
>>> support in Android backend does nothing besides returning
86 matches
Mail list logo
