On 25.04.2017 01:10, Samuel Pitoiset wrote:
No longer used.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Nicolai Hähnle
---
src/gallium/auxiliary/Makefile.sources | 2 -
src/gallium/auxiliary/util/u_caps.c| 267 -
src/gallium/auxiliary/util/u_caps.h
Interesting find. Is this in shaders with control flow? Perhaps with
this change, there are now more undefs in places that previously had a
phi with an unrelated use of the same TGSI temporary. Anyway, patches 1-3:
Reviewed-by: Nicolai Hähnle
On 25.04.2017 00:31, Samuel Pitoiset wrote:
4710
On 24.04.2017 15:31, Marek Olšák wrote:
On Mon, Apr 24, 2017 at 12:01 PM, Nicolai Hähnle wrote:
On 23.04.2017 01:10, Marek Olšák wrote:
From: Marek Olšák
There is no reason to check for ~0.
Also remove the incorrect comment.
---
src/mesa/state_tracker/st_draw.c | 9 ++---
1 file change
On 24.04.2017 18:22, Marek Olšák wrote:
From: Marek Olšák
Basically, don't load GRID_SIZE or BLOCK_SIZE if they are unused, determine
whether to load BLOCK_ID for each component separately, and set the number
of THREAD_ID VGPRs to load. Now we should get the maximum CS launch wave
rate in most
On 24.04.2017 18:22, Marek Olšák wrote:
From: Marek Olšák
---
src/gallium/auxiliary/tgsi/tgsi_scan.c | 47 ++
src/gallium/auxiliary/tgsi/tgsi_scan.h | 4 +++
2 files changed, 51 insertions(+)
diff --git a/src/gallium/auxiliary/tgsi/tgsi_scan.c
b/src/gallium/a
On 17-04-15 18:27:33, Jason Ekstrand wrote:
On April 14, 2017 5:37:55 PM Anuj Phogat wrote:
From: Ben Widawsky
This support was removed on gen9 (it worked before then) and was brought back
for gen10.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 +-
1 fil
https://bugs.freedesktop.org/show_bug.cgi?id=100690
Kenneth Graunke changed:
What|Removed |Added
Attachment #131008|0 |1
is obsolete|
Ben Widawsky writes:
> On 17-04-18 18:18:39, Francisco Jerez wrote:
>
> Most, if not all of the unrelated changes that snuck in were due to rebase.
> Anuj, would you mind fixing those? I tried my best to address the rest, but
> I'm
> admittedly stumbling my way through some of the l3 programming
On 17-04-18 18:18:39, Francisco Jerez wrote:
Most, if not all of the unrelated changes that snuck in were due to rebase.
Anuj, would you mind fixing those? I tried my best to address the rest, but I'm
admittedly stumbling my way through some of the l3 programming.
Anuj Phogat writes:
From: B
Thank you, and congratulations on the new card :)
On 25.04.2017 04:26, Dieter Nützel wrote:
> For the series:
>
> Tested-by: Dieter Nützel
>
> On Turks XT (6670).
>
> radeonsi (2/3) NOT yet (only compile),
> my RX 580, 8 GB, Nitro+
> is coming on Friday/Saturday, Yea ;-)
>
> Dieter
>
> A
On 25/04/17 01:43 AM, Nicolai Hähnle wrote:
> On 24.04.2017 18:32, Marek Olšák wrote:
>> On Mon, Apr 24, 2017 at 5:34 PM, Nicolai Hähnle
>> wrote:
>>> On 24.04.2017 15:22, Marek Olšák wrote:
From: Marek Olšák
>>>
>>>
>>> I don't like it. This kind of app-specific override is what drirc
It would kill nv30, I believe.
On Apr 24, 2017 10:30 PM, "Roland Scheidegger" wrote:
> Am 24.04.2017 um 23:12 schrieb Rob Clark:
> > so I guess this is likely to hurt pipe drivers that don't (yet?)
> > have a real compiler backend. (Ie. etnaviv and freedreno/a2xx.) So
> > maybe it should be op
Am 24.04.2017 um 23:12 schrieb Rob Clark:
> so I guess this is likely to hurt pipe drivers that don't (yet?)
> have a real compiler backend. (Ie. etnaviv and freedreno/a2xx.) So
> maybe it should be optional.
I suppose softpipe, too? Though that's fine, noone cares if it gets a
bit slower. Might
Am 10.03.2017 01:44, schrieb Dieter Nützel:
Hello Glenn,
I've tested this on r600g, Turks XT / HD6670, 2 GB (same as you have?).
It was hard work to apply this on master. Do you have a rebase handy?
But works so far.
Am 05.03.2017 18:26, schrieb Glenn Kennard:
This patch series implements sup
Am 12.04.2017 22:06, schrieb Dave Airlie:
On 13 April 2017 at 06:03, Markus Trippelsdorf
wrote:
On 2017.04.12 at 20:45 +0100, Emil Velikov wrote:
On 12 April 2017 at 20:34, Constantine Kharlamov
wrote:
>> I suspect this breaks because r600 more often fails to
>> compile some shaders,
>> and
Am 21.04.2017 12:11, schrieb Marek Olšák:
FWIW, I think this series can land, because glthread is not enabled by
default, and the libX11 issue is unrelated.
Marek
Gregory?
For the series:
Tested-by: Dieter Nützel
On Turks XT (6670).
Dieter
On Apr 21, 2017 4:22 AM, "Michel Dänzer" wrot
For the series:
Tested-by: Dieter Nützel
On Turks XT (6670).
radeonsi (2/3) NOT yet (only compile),
my RX 580, 8 GB, Nitro+
is coming on Friday/Saturday, Yea ;-)
Dieter
Am 23.04.2017 23:36, schrieb Constantine Kharlamov:
sb-based optimization was only used for older LLVM, whose support w
https://bugs.freedesktop.org/show_bug.cgi?id=100690
--- Comment #3 from Kenneth Graunke ---
Created attachment 131008
--> https://bugs.freedesktop.org/attachment.cgi?id=131008&action=edit
Proposed patch (git am)
I suggested two options at Khronos: ignore min/mag filters (it makes no sense
to c
https://bugs.freedesktop.org/show_bug.cgi?id=100690
--- Comment #2 from Kenneth Graunke ---
Thank you for finding and reporting this!
The game appears to be calling glCopyImageSubData() on a RGBA_UINT32 texture,
with only one miplevel, with min/mag filters set to GL_NEAREST_MIPMAP_LINEAR
and GL_
https://bugs.freedesktop.org/show_bug.cgi?id=100690
--- Comment #1 from talonz ---
I am also having this problem
latest mesa-git & llvm-svn
rx480
--
You are receiving this mail because:
You are the assignee for the bug.
You are the QA Contact for the bug.__
I agree with Jason, autogen.sh shouldn't be doing anything except configuring
autotools. Perhaps a "initial-configuration.sh" script would be more
appropriate.
Just my two cents and not a hard NAK.
Dylan
Quoting Jason Ekstrand (2017-04-24 12:29:32)
> This seems like something that would be more
Him Tim,
I hadnt had my morning coffee butdidnt you do it the other way around?
It looks like, that "_mesa_HashWalk" ist he locked and "_mesa_HashWalkLocked"
the unlocked version.
Michael
-Ursprüngliche Nachricht-
Von: mesa-dev [mailto:mesa-dev-boun...@lists.freedesktop.org] Im Auftrag
On 25/04/17 01:30, Nicolai Hähnle wrote:
On 24.04.2017 12:28, Timothy Arceri wrote:
On 24/04/17 20:13, Nicolai Hähnle wrote:
On 24.04.2017 07:28, Timothy Arceri wrote:
---
src/mesa/main/arrayobj.c | 11 +--
src/mesa/main/attrib.c | 23 +++
src/mesa/main/mtype
On Thu, Apr 6, 2017 at 12:49 PM, Thomas Helland
wrote:
> The conditional discard pass follows the same pattern, so merge the
> two, and avoid running the visitor two times.
> ---
> src/compiler/Makefile.sources | 1 -
> src/compiler/glsl/glsl_parser_extras.cpp | 1 -
> src/
On 24/04/17 22:51, Fredrik Höglund wrote:
On Monday 24 April 2017, Timothy Arceri wrote:
From the EXT_framebuffer_object spec:
"Framebuffer objects created with the commands defined
by the GL_EXT_framebuffer_object extension are defined
to be shared, while FBOs created with comman
No longer used.
Signed-off-by: Samuel Pitoiset
---
src/gallium/auxiliary/Makefile.sources | 2 -
src/gallium/auxiliary/util/u_caps.c| 267 -
src/gallium/auxiliary/util/u_caps.h| 71 -
3 files changed, 340 deletions(-)
delete mode 100644 src/gal
On Mon, Apr 24, 2017 at 03:59:07PM -0700, Kenneth Graunke wrote:
> On Monday, April 24, 2017 3:19:01 PM PDT Rafael Antognolli wrote:
> > Use an alias, so we can set the same value as the #define's.
> >
> > Signed-off-by: Rafael Antognolli
> > ---
> > src/intel/genxml/gen8.xml | 1 +
> > src/inte
On Monday, April 24, 2017 3:19:05 PM PDT Rafael Antognolli wrote:
> Rename that field name on genxml for:
>- 3DSTATE_GS - gen6+
>- 3DSTATE_DS - gen7+
>- 3DSTATE_HS - gen7+
>
> Signed-off-by: Rafael Antognolli
> ---
> src/intel/genxml/gen6.xml| 2 +-
> src/intel/genxml/gen7.xm
On Monday, April 24, 2017 3:19:01 PM PDT Rafael Antognolli wrote:
> Use an alias, so we can set the same value as the #define's.
>
> Signed-off-by: Rafael Antognolli
> ---
> src/intel/genxml/gen8.xml | 1 +
> src/intel/genxml/gen9.xml | 1 +
> 2 files changed, 2 insertions(+)
>
> diff --git a/s
On Monday, 2017-04-24 17:22:19 +0100, Emil Velikov wrote:
> From: Emil Velikov
>
> Add a page that has information which release is expected when and
> associated information.
>
> Reference to it from the "Releasing process" and "Release notes" pages.
>
> Cc: Andres Gomez
> Signed-off-by: Emil
47109 shaders in 29632 tests
Totals:
SGPRS: 1917364 -> 1916620 (-0.04 %)
VGPRS: 1165802 -> 1165202 (-0.05 %)
Spilled SGPRs: 1880 -> 1843 (-1.97 %)
Spilled VGPRs: 70 -> 65 (-7.14 %)
Private memory VGPRs: 1184 -> 1184 (0.00 %)
Scratch size: 1312 -> 1308 (-0.30 %) dwords per thread
Code Size: 60211356
The main goal of this pass to merge temporary registers in order
to reduce the total number of registers and also to produce
optimal TGSI code.
In fact, compilers seem to be confused when temporary variables
are already merged, maybe because it's done too early in the
process.
Skipping the pass,
shader-db results on GK106 (Thanks Karol):
total instructions in shared programs : 3931608 -> 3929463 (-0.05%)
total gprs used in shared programs: 481255 -> 479014 (-0.47%)
total local used in shared programs : 27481 -> 27381 (-0.36%)
total bytes used in shared programs : 36031256 -> 36011
Signed-off-by: Samuel Pitoiset
---
src/gallium/auxiliary/gallivm/lp_bld_limits.h| 1 +
src/gallium/auxiliary/tgsi/tgsi_exec.h | 1 +
src/gallium/docs/source/screen.rst | 3 +++
src/gallium/drivers/etnaviv/etnaviv_screen.c | 1 +
src/gallium/drivers/freedreno/freedr
On Monday, April 24, 2017 6:22:41 AM PDT Marek Olšák wrote:
> From: Marek Olšák
>
> ---
> src/gallium/drivers/radeonsi/si_pipe.c | 20 +
> src/gallium/drivers/radeonsi/si_pipe.h | 1 +
> src/gallium/drivers/radeonsi/si_state_draw.c | 45
>
>
v2:
- Included Louis patch that adds gen4, gen4.5 and gen5 xml's
- Merged code for gen4-5 for emit vertices and some other brw_*
functions
- Addressed Ken's comments about updating gen4 and gen5 xml.
- Included suggestion from Kristian about functions to return struct
brw_addr
From: Kenneth Graunke
This emits 3DSTATE_WM_DEPTH_STENCIL on Gen8+ or DEPTH_STENCIL_STATE
(and the relevant pointer packets) on Gen6-7.5 from a single function.
Signed-off-by: Kenneth Graunke
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/Makefile.sources| 2 +-
src/
Emits 3DSTATE_RASTER from genX_state_upload.c using pack structs from
genxml.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/brw_state.h | 1 +-
src/mesa/drivers/dri/i965/gen8_sf_state.c | 125 +---
src/mesa/drivers/dri/i965/genX_state_upload.c | 125
Set the type of some fields, instead of prefix. Also fix the
SAMPLER_BORDER_COLOR_STATE fields of gen5.xml.
Signed-off-by: Rafael Antognolli
---
src/intel/genxml/gen4.xml | 13 +-
src/intel/genxml/gen45.xml | 12 -
src/intel/genxml/gen5.xml | 52 +++-
We need to use some enums inside genX_state_upload.c, but including the
whole header will cause several conflicts between things defined in this
header and the genxml auto-generated headers.
So create a separate header that is included both by brw_eu_defines.h
and genX_state_upload.c.
Signed-off-
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/Makefile.am | 12
src/mesa/drivers/dri/i965/Makefile.sources | 9 +
src/mesa/drivers/dri/i965/brw_state.h | 1 +
3 files changed, 22 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/Makefile.am
b
Emit 3DSTATE_PS_EXTRA on Gen8+ using brw_batch_emit helper, that uses
pack structs from genxml.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/Makefile.sources| 1 +-
src/mesa/drivers/dri/i965/brw_state.h | 10 +-
src/mesa/drivers/dri/i965/gen8_ps_state.c | 138
Emit sf state on Gen6+ using brw_batch_emit helper, using pack structs
from genxml.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/brw_state.h | 3 +-
src/mesa/drivers/dri/i965/brw_util.h | 25 +-
src/mesa/drivers/dri/i965/gen6_sf_state.c | 190 +
Some code that was placed in brw_draw_upload.c and exported to be used
by gen8+ was also moved to genX_state_upload, and the respective symbols
are not exported anymore.
v2:
- Remove code from brw_draw_upload too
- Emit vertices for gen4-5 too.
- Use helper to setup brw_address (Kristian)
Emit clip state on Gen6+ using brw_batch_emit helper, using pack structs
from genxml.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/brw_state.h | 1 +-
src/mesa/drivers/dri/i965/gen6_clip_state.c | 139 +--
src/mesa/drivers/dri/i965/genX_state_upload.
On this patch, we port:
- brw_polygon_stipple
- brw_polygon_stipple_offset
- brw_line_stipple
- brw_drawing_rect
v2:
- Also emit states for gen4-5 with this code.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/Makefile.sources | 1 +-
src/mesa/drivers/dri/i
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/Makefile.sources| 1 +-
src/mesa/drivers/dri/i965/brw_state.h | 1 +-
src/mesa/drivers/dri/i965/gen6_cc.c | 90 +
src/mesa/drivers/dri/i965/genX_state_upload.c | 53 +++-
4 files cha
There are two variants:
- Clip Enable
- CLIP Enable (on gen6)
Rename everything to Clip Enable.
Signed-off-by: Rafael Antognolli
Reviewed-by: Kenneth Graunke
---
src/intel/genxml/gen4.xml | 2 +-
src/intel/genxml/gen45.xml | 2 +-
src/intel/genxml/gen5.xml | 2 +-
src/intel/genxml/gen6
Emit 3DSTATE_VS on Gen6+ using brw_batch_emit helper, that uses pack
structs from genxml.
v2:
- Use render_bo helper to setup brw_address (Kristian)
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/Makefile.sources| 2 +-
src/mesa/drivers/dri/i965/brw_state.h |
In a previous patch some enums were split out from brw_eu_defines.h, so
they could be used by genxml based code. anv can also benefit from this.
Signed-off-by: Rafael Antognolli
---
src/intel/vulkan/genX_pipeline.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/intel/
From: Kenneth Graunke
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/Makefile.sources| 15 ++-
src/mesa/drivers/dri/i965/genX_state_upload.c | 109 +++-
2 files changed, 119 insertions(+), 5 deletions(-)
create mode 100644 src/mesa/drivers/dri/i965/genX_state
Fill out "Attribute Active Component Format" possible values.
Signed-off-by: Rafael Antognolli
---
src/intel/genxml/gen9.xml | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
index ee7056b..59daa31 100644
--- a/src/int
Use an alias, so we can set the same value as the #define's.
Signed-off-by: Rafael Antognolli
---
src/intel/genxml/gen8.xml | 1 +
src/intel/genxml/gen9.xml | 1 +
2 files changed, 2 insertions(+)
diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
index 408d241..2908082 100644
-
Emit 3DSTATE_PS on Gen7+ using brw_batch_emit helper, that uses pack
structs from genxml.
v2:
- Use render_bo helper to setup brw_address (Kristian)
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/brw_state.h | 2 +-
src/mesa/drivers/dri/i965/gen7_wm_state.c | 13
Emit 3DSTATE_SBE on Gen7+ using brw_batch_emit helper, that uses pack
structs from genxml.
v2:
- Use ACTIVE_COMPONENT_XYZW from gen9.xml.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/Makefile.sources| 2 +-
src/mesa/drivers/dri/i965/brw_state.h | 2 +-
src/m
Emit 3DSTATE_WM on Gen6+ using brw_batch_emit helper, that uses pack
structs from genxml.
v2:
- Use render_bo helper to setup brw_address (Kristian)
- Remove TODO and use BRW_PSCDEPTH_OFF.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/Makefile.sources| 1 +-
src/mes
Name the options to "Pixel Location":
- PIXLOC_CENTER -> CENTER
- PIXLOC_UL_CORNER -> UL_CORNER
Signed-off-by: Rafael Antognolli
---
src/intel/blorp/blorp_genX_exec.h | 4 +---
src/intel/genxml/gen6.xml | 4 ++--
src/intel/genxml/gen7.xml | 4 ++--
src/intel/genxml/gen75.xm
Upload blend states using GENX(BLEND_STATE_ENTRY_pack), generated from
genxml.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/Makefile.sources| 1 +-
src/mesa/drivers/dri/i965/brw_state.h | 3 +-
src/mesa/drivers/dri/i965/gen6_cc.c | 216 +
s
Emit 3DSTATE_SCISSOR_STATE_POINTERS using brw_batch_emit, and pack the
scissor states using GENX(SCISSOR_RECT_pack), generated from genxml.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/brw_state.h | 1 +-
src/mesa/drivers/dri/i965/genX_state_upload.c | 89 +
- Normalize "Anti-Aliasing Enable"
- Add "Multisample Rasterization Mode" constants
- Rename "Use Point Width on Vertex" to "Vertex"
- Rename "Use Point Width from State" to "State"
Signed-off-by: Rafael Antognolli
---
src/intel/genxml/gen6.xml | 15 ++-
src/intel/genxml/gen7.xml
Ported in this patch:
- 3DSTATE_DS
- 3DSTATE_GS
- 3DSTATE_HS
- 3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/Makefile.sources | 6 +-
src/mesa/drivers/dri/i965/brw_state.h | 18 +-
src/mesa/drivers/dri/i965/gen6
The following states are ported on this patch:
- gen6_gs_push_constants
- gen6_vs_push_constants
- gen6_wm_push_constants
- gen7_tes_push_constants
v2:
- Use helper to setup brw_address (Kristian)
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/Makefile.sources
From: Kenneth Graunke
Make atoms initalization compile conditionally based on the target
platform.
---
src/mesa/drivers/dri/i965/brw_state.h | 12 +-
src/mesa/drivers/dri/i965/brw_state_upload.c | 385 +---
src/mesa/drivers/dri/i965/genX_state_upload.c | 340 +++
- "COLOR_CALC_STATE Change" -> "Color Calc State Pointer Valid"
- "Pointer to COLOR_CALC_STATE" -> "Color Calc State Pointer"
- "BackFace" -> "Backface"
Signed-off-by: Rafael Antognolli
---
src/intel/blorp/blorp_genX_exec.h | 4 ++--
src/intel/genxml/gen6.xml | 4 ++--
src/intel/
Rename that field name on genxml for:
- 3DSTATE_GS - gen6+
- 3DSTATE_DS - gen7+
- 3DSTATE_HS - gen7+
Signed-off-by: Rafael Antognolli
---
src/intel/genxml/gen6.xml| 2 +-
src/intel/genxml/gen7.xml| 6 +++---
src/intel/genxml/gen75.xml | 6 +++---
src/intel/genxml/g
Signed-off-by: Rafael Antognolli
---
src/intel/blorp/blorp_genX_exec.h | 2 +-
src/intel/genxml/gen6.xml | 2 +-
src/intel/genxml/gen7.xml | 2 +-
src/intel/genxml/gen75.xml| 2 +-
src/intel/genxml/gen8.xml | 2 +-
src/intel/genxml/gen9.xml | 2 +-
src/inte
This makes genxml create the right struct types, and generate the right
batch commands.
Signed-off-by: Rafael Antognolli
Reviewed-by: Kenneth Graunke
---
src/intel/genxml/gen6.xml | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/intel/genxml/gen6.xml b/src/intel/g
Emit 3DSTATE_TE on Gen7+ using brw_batch_emit helper.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/Makefile.sources| 1 +-
src/mesa/drivers/dri/i965/brw_state.h | 1 +-
src/mesa/drivers/dri/i965/gen7_te_state.c | 67 +
src/mesa/drivers/dri/
Emit 3DSTATE_MULTISAMPLE using brw_batch_emit.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/brw_context.h| 9 +-
src/mesa/drivers/dri/i965/brw_state.h | 2 +-
src/mesa/drivers/dri/i965/gen6_multisample_state.c | 6 +-
src/mesa/drivers/dri/i965/gen
From: Kenneth Graunke
Both GS and SOL have these fields. Some were ReorderEnable = true,
some were ReorderMode = REORDER_TRAILING, and some were just TRAILING.
Signed-off-by: Kenneth Graunke
---
src/intel/genxml/gen6.xml| 5 -
src/intel/genxml/gen7.xml| 5 -
src/intel/
This function now lives inside genX_state_upload.c.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/Makefile.sources | 1 +-
src/mesa/drivers/dri/i965/brw_state.h | 8 +-
src/mesa/drivers/dri/i965/gen6_sf_state.c | 265 +--
3 files changed, 274 deleti
Emit 3DSTATE_SOL on Gen7+ using brw_batch_emit helper, that uses pack
structs from genxml.
v2:
- Add helpers to assign struct brw_address (Kristian)
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/Makefile.sources| 1 +-
src/mesa/drivers/dri/i965/brw_state.h |
On Mon, Apr 24, 2017 at 03:03:56PM -0700, Kenneth Graunke wrote:
> On Wednesday, April 19, 2017 4:56:13 PM PDT Rafael Antognolli wrote:
> > From: Kenneth Graunke
> >
> > Both GS and SOL have these fields. Some were ReorderEnable = true,
> > some were ReorderMode = REORDER_TRAILING, and some were
On Wednesday, April 19, 2017 4:56:13 PM PDT Rafael Antognolli wrote:
> From: Kenneth Graunke
>
> Both GS and SOL have these fields. Some were ReorderEnable = true,
> some were ReorderMode = REORDER_TRAILING, and some were just TRAILING.
>
> Signed-off-by: Kenneth Graunke
> ---
> src/intel/gen
NEON is sufficiently different on arm64 that we can't just reuse this
code. Disable it on arm64 for now.
v2: Use PIPE_ARCH_ARM instead, as __ARM_ARCH may be 8 for a 32-bit build
for a v8 CPU.
Signed-off-by: Eric Anholt
Cc:
---
src/gallium/drivers/vc4/vc4_tiling_lt.c | 4 ++--
1 file chang
This will allow Raspbian's ARMv6 builds to take advantage of the new NEON
code, and could prevent problems if vc4 ends up getting used on a v7 CPU
without NEON.
v2: Drop dead NEON_SUFFIX (noted by Erik Faye-Lund)
---
src/gallium/drivers/vc4/vc4_screen.c | 3 +++
src/gallium/drivers/vc4/vc4_tilin
Android.mk was setting the flag across the entire driver, so we didn't
have non-NEON versions getting built. This was going to be a problem with
the next commit, when I start auto-detecting NEON support and use the
non-NEON version when appropriate.
---
Rob: I'm happy to just drop this patch if y
I wrote this code with reference to pixman, though I've only decided to
cover Linux (what I'm testing) and Android (seems obvious enough). Linux
has getauxval() as a cleaner interface to the /proc entry, but it's more
glibc-specific and I didn't want to add detection for that.
This will be used t
On Mon, Apr 24, 2017 at 11:59 AM, Emil Velikov wrote:
> Hi Rob,
>
> On 24 April 2017 at 17:46, Rob Herring wrote:
>> If r300g is the only radeon driver built, the Android build fails to
>> build:
>>
>> ninja: error:
>> 'out/target/product/linaro_x86_64/obj/STATIC_LIBRARIES/libmesa_pipe_radeon_int
On 04/24/2017 11:22 PM, Rob Clark wrote:
On Mon, Apr 24, 2017 at 5:18 PM, Samuel Pitoiset
wrote:
On 04/24/2017 11:12 PM, Rob Clark wrote:
so I guess this is likely to hurt pipe drivers that don't (yet?) have
a real compiler backend. (Ie. etnaviv and freedreno/a2xx.) So maybe
it should b
On Mon, Apr 24, 2017 at 5:18 PM, Samuel Pitoiset
wrote:
>
>
> On 04/24/2017 11:12 PM, Rob Clark wrote:
>>
>> so I guess this is likely to hurt pipe drivers that don't (yet?) have
>> a real compiler backend. (Ie. etnaviv and freedreno/a2xx.) So maybe
>> it should be optional.
>
>
> I can't say fo
On 04/24/2017 11:12 PM, Rob Clark wrote:
so I guess this is likely to hurt pipe drivers that don't (yet?) have
a real compiler backend. (Ie. etnaviv and freedreno/a2xx.) So maybe
it should be optional.
I can't say for these drivers, but it seems safer to add an option if
this can hurt them
so I guess this is likely to hurt pipe drivers that don't (yet?) have
a real compiler backend. (Ie. etnaviv and freedreno/a2xx.) So maybe
it should be optional.
Also I wonder about the pre-llvm radeon gen's, since sb uses the
actual instruction encoding for IR between tgsi->sb and backend opt
pa
The main goal of this pass to merge temporary registers in order
to reduce the total number of registers and also to produce
optimal TGSI code.
In fact, compilers seem to be confused when temporary variables
are already merged, maybe because it's done too early in the
process.
Removing the pass,
On 17-04-24 21:29:32, Jason Ekstrand wrote:
This seems like something that would be more appropriate to put on a
"getting started" page than autogen.sh. The very last thing I (as a
user of it) would expect autogen.sh to do is monkey with my git
config; local or otherwise.
"Otherwise" is ce
On Mon, Apr 24, 2017 at 5:06 PM, Brian Paul wrote:
> On 04/22/2017 03:46 PM, Giuseppe Bilotta wrote:
>>
>> Makes sense. As Gustaw suggests, it _shouldn't_ happen, but there's
>> nothing to lose in being cautious about it 8-). I'll respin this patch
>> with the assert+return here.
>
> I just want t
This seems like something that would be more appropriate to put on a
"getting started" page than autogen.sh. The very last thing I (as a user
of it) would expect autogen.sh to do is monkey with my git config; local or
otherwise.
On April 24, 2017 6:16:14 PM Emil Velikov wrote:
From: Emil
On 04/24/2017 06:32 PM, Marek Olšák wrote:
On Mon, Apr 24, 2017 at 5:34 PM, Nicolai Hähnle wrote:
On 24.04.2017 15:22, Marek Olšák wrote:
From: Marek Olšák
I don't like it. This kind of app-specific override is what drirc was meant
to provide. Having separate places for it is confusing.
Reviewed-by: Samuel Pitoiset
On 04/24/2017 03:22 PM, Marek Olšák wrote:
From: Marek Olšák
---
src/gallium/drivers/radeon/r600_pipe_common.h | 1 +
src/gallium/drivers/radeon/r600_query.c | 7 +++
src/gallium/drivers/radeon/r600_query.h | 1 +
src/gallium/drivers/radeonsi/
As discussed,
If you run scons with a small -j number, it would work (verified by Emil).
With that change
Reviewed-by: George Kyriazis
mailto:george.kyria...@intel.com>>
For the rest of the series, I don’t have enough experience with travis to
review..
George
On Apr 21, 2017, at 7:08 AM, Em
Samuel Iglesias Gonsálvez writes:
> On Fri, 2017-04-21 at 10:23 -0700, Francisco Jerez wrote:
>> Samuel Iglesias Gonsálvez writes:
>>
>> > On Thu, 2017-04-20 at 10:26 -0700, Francisco Jerez wrote:
>> > > Samuel Iglesias Gonsálvez writes:
>> > >
>> > > > It was setting XYWZ swizzle to all unif
https://bugs.freedesktop.org/show_bug.cgi?id=100613
--- Comment #14 from Roland Scheidegger ---
(In reply to Ray Strode [halfline] from comment #13)
> Created attachment 131000 [details] [review]
> patch that didn't help at all
>
> Hi,
> (In reply to Roland Scheidegger from comment #10)
> > I'm
On 24 April 2017 at 18:15, Eric Engestrom wrote:
> On Friday, 2017-04-21 13:08:23 +0100, Emil Velikov wrote:
>> From: Emil Velikov
>>
>> With next commits we'll add a couple of more options.
>>
>> v2: Rework check target.
>>
>> Signed-off-by: Emil Velikov
>> ---
>> .travis.yml | 18
On Mon, Apr 24, 2017 at 6:43 PM, Nicolai Hähnle wrote:
> On 24.04.2017 18:32, Marek Olšák wrote:
>>
>> On Mon, Apr 24, 2017 at 5:34 PM, Nicolai Hähnle
>> wrote:
>>>
>>> On 24.04.2017 15:22, Marek Olšák wrote:
From: Marek Olšák
>>>
>>>
>>>
>>> I don't like it. This kind of app-spec
On Friday, 2017-04-21 13:08:26 +0100, Emil Velikov wrote:
> From: Emil Velikov
>
> Signed-off-by: Emil Velikov
> ---
> .travis.yml | 39 ---
> 1 file changed, 36 insertions(+), 3 deletions(-)
>
> diff --git a/.travis.yml b/.travis.yml
> index aa2a55d7bb4..1b
On Friday, 2017-04-21 13:08:23 +0100, Emil Velikov wrote:
> From: Emil Velikov
>
> With next commits we'll add a couple of more options.
>
> v2: Rework check target.
>
> Signed-off-by: Emil Velikov
> ---
> .travis.yml | 18 +-
> 1 file changed, 13 insertions(+), 5 deletions(-)
On 21 April 2017 at 15:06, Kyriazis, George wrote:
> rasterizer.cpp takes a lot of resources to compile. Looks like the autotools
> build runs -j2, which limits the exposure, because of fewer parallel jobs,
> while scons, by default is more aggressive.
>
> Suggest running scons -j 1 or scons -j
On 22 April 2017 at 20:21, Dave Airlie wrote:
> On 22 April 2017 at 20:13, Mauro Rossi wrote:
>> Fixes following building errors due to missing include paths:
>>
>> external/mesa/src/amd/common/ac_shader_info.c:23:10: fatal error:
>> 'nir/nir.h' file not found
>> #include "nir/nir.h"
>>
>
> On Apr 24, 2017, at 10:16 AM, Brian Paul wrote:
>
> On 04/21/2017 12:25 AM, green we wrote:
>> I tried to use OSMesa to do offscreen rendering, refer to the osdemo and
>> the tutorial here: http://www.alecjacobson.com/weblog/?p=2827
>> There are obvious serrations on the edge of the model.
>
On Fri 14 Apr 2017, Jason Ekstrand wrote:
> The command is really operating on a Queue not a command buffer and the
> nearest object to that with an allocator is VkDevice.
>
> Cc: "17.0"
> ---
> src/intel/vulkan/anv_batch_chain.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
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