Mauro, is it OK that I mention you as a reference for Android in the
releasing doc?
On Mon, 2017-03-27 at 21:48 +0300, Andres Gomez wrote:
> Signed-off-by: Andres Gomez
> Cc: Emil Velikov
> Cc: Tapani Pälli
> Cc: Mauro Rossi
> ---
> docs/releasing.html | 5 +
> 1 file changed, 5 insertion
On Mon, 17 Apr 2017 11:17:42 +0900
Michel Dänzer wrote:
> On 15/04/17 05:08 PM, gregory hainaut wrote:
> > On Sat, 15 Apr 2017 00:50:15 +0200
> > Dieter Nützel wrote:
> >
> >> Am 14.04.2017 07:53, schrieb gregory hainaut:
> >>> On Fri, 14 Apr 2017 05:20:38 +0200
> >>> Dieter Nützel wrote:
> >>
The Android native fence in i965 driver has two fd, one is from
App and stored in _EGLSync.SyncFd; Another one brw_fence->sync_fd
should be the dup of the first one, not direct copy.
These two fds are closed in dri2_egl_unref_sync in sequence.
Test: Run Vulkan and GLES stress test and no crash.
S
On 18/04/17 01:02 PM, Ilia Mirkin wrote:
> On Tue, Apr 18, 2017 at 12:00 AM, Ilia Mirkin wrote:
>> val_bool and val_int are in a union. val_bool gets the first byte, which
>> happens to work on LE when setting via the int, but breaks on BE. By
>> setting the value properly, we are able to use DRI3
On 04/18/2017 03:39 PM, Jason Ekstrand wrote:
> On Mon, Apr 17, 2017 at 4:49 PM, Edward O'Callaghan
> mailto:funfunc...@folklore1984.net>> wrote:
>
>
>
> On 04/18/2017 01:13 AM, Jason Ekstrand wrote:
> > I don't see anything in here that actually implements parallel shader
> > comp
On Apr 13, 2017 20:59, "Eric Anholt" wrote:
This will allow Raspbian's ARMv6 builds to take advantage of the new NEON
code, and could prevent problems if vc4 ends up getting used on a v7 CPU
without NEON.
---
src/gallium/drivers/vc4/vc4_screen.c | 3 +++
src/gallium/drivers/vc4/vc4_tiling.h | 2
From: Timothy Arceri
V2: leave copy propagation to avoid interpolation regressions
IVB is running into some spilling issues with the loop
removed so we leave it there for gen7 and below for now.
Run time for shader-db on my machine goes from ~795 seconds to
~665 seconds.
shader-db results BDW:
These are no longer used since the previous commit.
---
src/mesa/drivers/dri/i965/Makefile.sources | 2 -
.../dri/i965/brw_fs_channel_expressions.cpp| 483 -
.../drivers/dri/i965/brw_fs_vector_splitting.cpp | 400 -
src/mesa/drivers/dri/i965/
From: Timothy Arceri
V2: mark float opts as inexact
If one of the inputs to an mul/add is the result of another
mul/add there is a chance that we can reuse the result of that
mul/add in other calls if we do the multiplication in the right
order.
Also by attempting to move all constants to the t
This series completely drops GLSL IR opts from the i965 backend for gen7.5+ (see
patch 7 for why we don't drop them for other gens yet).
The first few patches introduce optimisations which help reduce the
egressions from dropping brw_do_channel_expressions() and
brw_do_vector_splitting(). We also
From: Timothy Arceri
Didn't turn out as useful as I'd hoped, but it will help alot more on
i965 by reducing regressions when we drop brw_do_channel_expressions()
and brw_do_vector_splitting().
I'm not sure how much sense 'is_not_used_by_conditional' makes on
platforms other than i965 but since t
From: Timothy Arceri
If packing doesn't cross locations we can easily make use of
ARB_enhanced_layouts to do packing rather than using the GLSL IR
lowering pass lower_packed_varyings().
Shader-db Broadwell results:
total instructions in shared programs: 12977822 -> 12977819 (-0.00%)
instruction
From: Timothy Arceri
These should be lowered away in GLSL IR but if we don't get dead
code to clean them up it causes issues in glsl_to_nir.
We wan't to drop as many GLSL IR opts in future as we can so this
makes glsl_to_nir just ignore the vars if it sees them.
In future we will want to just u
From: Timothy Arceri
This shuffles constants down in the reverse of what the previous
patch does and applies some simpilifications that may be made
possible from doing so.
Shader-db results BDW:
total instructions in shared programs: 12980814 -> 12977822 (-0.02%)
instructions in affected progra
Currently the NIR backends depend on GLSL IR copy propagation to
fix up the interpolateAt* function params after varying packing
changes the shader input to a global. It's possible copy propagation
might not always do what we need it too, and we also shouldn't
depend on optimisations to do this typ
Patch 1, 3-9 are
Reviewed-by: Bas Nieuwenhuizen
On Tue, Apr 18, 2017 at 5:57 AM, Dave Airlie wrote:
> From: Dave Airlie
>
> There is some radv specific info we need to gather from shaders
> before we get into converting nir->llvm, so we can make
> better decisions especially around user sgpr a
On Mon, Apr 17, 2017 at 4:49 PM, Edward O'Callaghan <
funfunc...@folklore1984.net> wrote:
>
>
> On 04/18/2017 01:13 AM, Jason Ekstrand wrote:
> > I don't see anything in here that actually implements parallel shader
> > compilation. Does radeon already spawn back-end threads to compile
> As far a
On 18 April 2017 at 15:07, Bas Nieuwenhuizen wrote:
> On Tue, Apr 18, 2017 at 5:57 AM, Dave Airlie wrote:
>> From: Dave Airlie
>>
>> In practice this will probably just drop draw id in a few places.
>>
>> Signed-off-by: Dave Airlie
>> ---
>> src/amd/common/ac_nir_to_llvm.c | 42 ++
On Tue, Apr 18, 2017 at 5:57 AM, Dave Airlie wrote:
> From: Dave Airlie
>
> In practice this will probably just drop draw id in a few places.
>
> Signed-off-by: Dave Airlie
> ---
> src/amd/common/ac_nir_to_llvm.c | 42 +++---
> src/amd/common/ac_shader_info.c |
On 04/18/2017 02:02 PM, Ilia Mirkin wrote:
> On Tue, Apr 18, 2017 at 12:00 AM, Ilia Mirkin wrote:
>> val_bool and val_int are in a union. val_bool gets the first byte, which
>> happens to work on LE when setting via the int, but breaks on BE. By
>> setting the value properly, we are able to use
> @@ -623,6 +623,8 @@ static void allocate_user_sgprs(struct
> nir_to_llvm_context *ctx,
> fprintf(stderr, "radv: TODO: add support for indirect
> sgprs\n");
> /* need to add support for indirect descriptor sets */
> assert(0);
This patch will also
On Tue, Apr 18, 2017 at 12:00 AM, Ilia Mirkin wrote:
> val_bool and val_int are in a union. val_bool gets the first byte, which
> happens to work on LE when setting via the int, but breaks on BE. By
> setting the value properly, we are able to use DRI3 on BE architectures.
> Tested by running glxg
val_bool and val_int are in a union. val_bool gets the first byte, which
happens to work on LE when setting via the int, but breaks on BE. By
setting the value properly, we are able to use DRI3 on BE architectures.
Tested by running glxgears with a NV34 in a G5 PPC.
Signed-off-by: Ilia Mirkin
Cc:
From: Dave Airlie
There is some radv specific info we need to gather from shaders
before we get into converting nir->llvm, so we can make
better decisions especially around user sgpr allocation.
This is just an initial placeholder to gather if sample positions
are required in the frag shader.
S
From: Dave Airlie
We want to expose more descriptor sets to the applications,
but currently we have a 1:1 mapping between shader descriptor
sets and 2 user sgprs, limiting us to 4 per stage. This commit
check if we don't have enough user sgprs for the number of
bound sets for this shader, we can
From: Dave Airlie
Signed-off-by: Dave Airlie
---
src/amd/common/ac_nir_to_llvm.c | 13 -
src/amd/common/ac_shader_info.c | 3 +++
src/amd/common/ac_shader_info.h | 3 +++
src/amd/vulkan/radv_cmd_buffer.c | 23 +++
4 files changed, 29 insertions(+), 13 deleti
From: Dave Airlie
First step to optimising push constants.
Signed-off-by: Dave Airlie
---
src/amd/common/ac_nir_to_llvm.c | 12 ++--
src/amd/common/ac_shader_info.c | 8
src/amd/common/ac_shader_info.h | 1 +
3 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/s
From: Dave Airlie
This pre calculates the used descriptor sets.
Signed-off-by: Dave Airlie
---
src/amd/common/ac_shader_info.c | 34 ++
src/amd/common/ac_shader_info.h | 1 +
2 files changed, 35 insertions(+)
diff --git a/src/amd/common/ac_shader_info.c b/src/
amdgpu-pro advertise 32 bound descriptor sets, and we have some
possible workloads that might need more than 4.
This series add a little pre-pass to gather some radv specific info
(there are more things I want to use this for), then add support
indirect binding of the descriptor sets via a lookup
From: Dave Airlie
mostly documenting things, since with modern llvm we always have the
spill enabled.
Signed-off-by: Dave Airlie
---
src/amd/common/ac_nir_to_llvm.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_t
From: Dave Airlie
This bumps the limit to the number of sets to 32, now that
we have proper support for it. It also uses 1u in a few places
to make things a bit safer.
Signed-off-by: Dave Airlie
---
src/amd/vulkan/radv_cmd_buffer.c | 12 ++--
src/amd/vulkan/radv_descriptor_set.h |
From: Dave Airlie
This adds an initial implementation to allocate the user
sgprs and make sure we don't run out if we try to bind
a bunch of descriptor sets.
This can be enhanced further in the future if we add
support for inlining push constants.
Signed-off-by: Dave Airlie
---
src/amd/common
From: Dave Airlie
In practice this will probably just drop draw id in a few places.
Signed-off-by: Dave Airlie
---
src/amd/common/ac_nir_to_llvm.c | 42 +++---
src/amd/common/ac_shader_info.c | 26
src/amd/common/ac_shader_info.h | 5
2017-04-18 9:25 GMT+08:00 Plamena Manolova :
> Adds suppport for ARB_fragment_shader_interlock. We achieve
> the interlock and fragment ordering by issuing a memory fence
> via sendc.
>
> Signed-off-by: Plamena Manolova
> ---
> docs/features.txt| 2 +-
> docs/relnotes
On 18/04/17 11:25, Plamena Manolova wrote:
This extension provides new GLSL built-in functions
beginInvocationInterlockARB() and endInvocationInterlockARB()
that delimit a critical section of fragment shader code. For
pairs of shader invocations with "overlapping" coverage in a
given pixel, the
So atexit() is horrible and 4aea8fe7 is probably not a good idea. But
add an extra layer of duct-tape to the problem. Otherwise we hit a
situation where app using an atexit() handler that runs later than ours
doesn't hang when trying to tear down a context.
(gdb) bt
#0 util_queue_killall_and_
Adds suppport for ARB_fragment_shader_interlock. We achieve
the interlock and fragment ordering by issuing a memory fence
via sendc.
Signed-off-by: Plamena Manolova
---
docs/features.txt| 2 +-
docs/relnotes/17.1.0.html| 1 +
src/intel/compiler/b
This extension provides new GLSL built-in functions
beginInvocationInterlockARB() and endInvocationInterlockARB()
that delimit a critical section of fragment shader code. For
pairs of shader invocations with "overlapping" coverage in a
given pixel, the OpenGL implementation will guarantee that the
Whoops, feel free to review but this patch is unrelated to this series.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
V2: typo know -> known
---
docs/envvars.html | 3 +++
src/mesa/main/context.c | 3 +++
2 files changed, 6 insertions(+)
diff --git a/docs/envvars.html b/docs/envvars.html
index 6537365..a064f56 100644
--- a/docs/envvars.html
+++ b/docs/envvars.html
@@ -39,20 +39,23 @@ sometimes be useful fo
From: Timothy Arceri
Currently we were only making sure types were the same within a
single stage. This looks to have regressed with 953a0af8e3f73.
https://bugs.freedesktop.org/show_bug.cgi?id=97524
---
src/mesa/drivers/dri/i965/brw_link.cpp | 1 +
src/mesa/main/uniform_query.cpp
V2: add missing FLUSH_CURRENT() to no_error path
---
src/mesa/vbo/vbo_exec_array.c | 49 ++-
1 file changed, 39 insertions(+), 10 deletions(-)
diff --git a/src/mesa/vbo/vbo_exec_array.c b/src/mesa/vbo/vbo_exec_array.c
index 9452c65..a78edd3 100644
--- a/src
V2: move MESA_VERBOSE checks back into the common code path.
---
src/mesa/vbo/vbo_exec_array.c | 96 ---
1 file changed, 73 insertions(+), 23 deletions(-)
diff --git a/src/mesa/vbo/vbo_exec_array.c b/src/mesa/vbo/vbo_exec_array.c
index a78edd3..5b02e89 1006
These checks do not generate any errors. Move them so we can add
KHR_no_error support and still make sure we do these checks.
Reviewed-by: Nicolai Hähnle
---
src/mesa/main/api_validate.c | 43 +
src/mesa/vbo/vbo_exec_array.c | 106 ++
2 f
The only caller we don't update is update_arrays(), we leave that to the
following commit.
---
src/mesa/main/varray.c | 136 ++---
1 file changed, 73 insertions(+), 63 deletions(-)
diff --git a/src/mesa/main/varray.c b/src/mesa/main/varray.c
index 07934
Reviewed-by: Nicolai Hähnle
---
src/mesa/main/varray.c | 18 ++
1 file changed, 10 insertions(+), 8 deletions(-)
diff --git a/src/mesa/main/varray.c b/src/mesa/main/varray.c
index 7c46cb3..6da9d84 100644
--- a/src/mesa/main/varray.c
+++ b/src/mesa/main/varray.c
@@ -1783,29 +1783,
This will help us split array validation from array update.
V2: add const to ctx param
---
src/mesa/main/varray.c | 31 ---
1 file changed, 20 insertions(+), 11 deletions(-)
diff --git a/src/mesa/main/varray.c b/src/mesa/main/varray.c
index 65734df..f00a64b 100644
---
---
src/mesa/main/context.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/src/mesa/main/context.h b/src/mesa/main/context.h
index 9704a96..ccb5463 100644
--- a/src/mesa/main/context.h
+++ b/src/mesa/main/context.h
@@ -317,20 +317,27 @@ _mesa_is_gles31(const struct gl_context *ctx)
/*
---
src/mesa/main/varray.c | 352 +
1 file changed, 236 insertions(+), 116 deletions(-)
diff --git a/src/mesa/main/varray.c b/src/mesa/main/varray.c
index be5482d..7c46cb3 100644
--- a/src/mesa/main/varray.c
+++ b/src/mesa/main/varray.c
@@ -315,21 +
We also move _mesa_update_array_format() into the caller.
This gets these functions ready for KHR_no_error support.
V2: Updated function comment as suggested by Brian.
---
src/mesa/main/varray.c | 71 --
1 file changed, 45 insertions(+), 26 deletio
---
src/mesa/main/getstring.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/src/mesa/main/getstring.c b/src/mesa/main/getstring.c
index 6e90511..5da405d 100644
--- a/src/mesa/main/getstring.c
+++ b/src/mesa/main/getstring.c
@@ -297,17 +297,28 @@ invalid_pname:
*
* Returns __
V2: some bug fixes and suggestions addressed as suggested by Brian and
Nicolai.
This series adds some initial support for the KHR_no_error.
For now it can only be enabled with the MESA_NO_ERROR environment
variable. To start with I've added support to some of the api
calls that were taking a
This will be used for adding KHR_no_error support.
---
src/mesa/main/varray.c | 55 +-
1 file changed, 41 insertions(+), 14 deletions(-)
diff --git a/src/mesa/main/varray.c b/src/mesa/main/varray.c
index 233dc0d..65734df 100644
--- a/src/mesa/main/v
V2: restore lost comment, add static to validate_uniform(),
simplify array offset logic.
---
src/mesa/main/uniform_query.cpp | 74 -
1 file changed, 51 insertions(+), 23 deletions(-)
diff --git a/src/mesa/main/uniform_query.cpp b/src/mesa/main/uniform_q
On Mon, Apr 17, 2017 at 7:55 PM, Edward O'Callaghan
wrote:
>
>
> On 04/18/2017 12:22 AM, Ilia Mirkin wrote:
>> The whole point of this extension is to allow applications to query
>> compilation status without stalling, waiting for the compile. That
>> means that glCompileShader/glLinkProgram shoul
On 04/18/2017 12:22 AM, Ilia Mirkin wrote:
> The whole point of this extension is to allow applications to query
> compilation status without stalling, waiting for the compile. That
> means that glCompileShader/glLinkProgram should return immediately
Right, my question though is, what happens if
On 04/18/2017 01:13 AM, Jason Ekstrand wrote:
> I don't see anything in here that actually implements parallel shader
> compilation. Does radeon already spawn back-end threads to compile
As far as I am aware that is exactly right.
> shaders or are we just lying about it? Even if it does, the f
The return code can be simplified by using the logical not operator.
Signed-off-by: Fabio Estevam
---
src/gallium/drivers/etnaviv/etnaviv_fence.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/src/gallium/drivers/etnaviv/etnaviv_fence.c
b/src/gallium/drivers/etnaviv/e
In cases where it is used it is always 1.
Signed-off-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_descriptor_set.c | 21 ++---
src/amd/vulkan/radv_descriptor_set.h | 1 -
src/amd/vulkan/radv_private.h| 1 -
3 files changed, 10 insertions(+), 13 deletions(-)
diff --git
Signed-off-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_descriptor_set.c | 16
1 file changed, 4 insertions(+), 12 deletions(-)
diff --git a/src/amd/vulkan/radv_descriptor_set.c
b/src/amd/vulkan/radv_descriptor_set.c
index 48cb8c2a30a..26f89152d52 100644
--- a/src/amd/vulkan/r
Signed-off-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_descriptor_set.c | 67 +++-
src/amd/vulkan/radv_private.h| 4 +++
2 files changed, 55 insertions(+), 16 deletions(-)
diff --git a/src/amd/vulkan/radv_descriptor_set.c
b/src/amd/vulkan/radv_descript
https://bugs.freedesktop.org/show_bug.cgi?id=100693
--- Comment #7 from sav...@ukr.net ---
I see. Then I added ICC and MSVC logs with all thrown warnings (see
attachment). Just in case it would help to improve MESA code.
--
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https://bugs.freedesktop.org/show_bug.cgi?id=100693
--- Comment #6 from sav...@ukr.net ---
Created attachment 130879
--> https://bugs.freedesktop.org/attachment.cgi?id=130879&action=edit
ICC and MSVC build warnings
--
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You are the assignee for the bug.__
On 04/17/2017 12:11 PM, Brian Paul wrote:
On 04/17/2017 07:34 AM, Emil Velikov wrote:
Module: Mesa
Branch: master
Commit: ce562f9e3fab769d64b0e5453ec2b4f8710a31ce
URL:
https://urldefense.proofpoint.com/v2/url?u=http-3A__cgit.freedesktop.org_mesa_mesa_commit_-3Fid-3Dce562f9e3fab769d64b0e5453ec2b
https://bugs.freedesktop.org/show_bug.cgi?id=100693
--- Comment #5 from Hi-Angel ---
(In reply to sav_ix from comment #4)
> (ICC) ir.h(2254): warning #873: function "exec_node::operator new" has no
> corresponding operator delete (to be called if an exception is thrown during
> initialization of
On 04/17/2017 07:34 AM, Emil Velikov wrote:
Module: Mesa
Branch: master
Commit: ce562f9e3fab769d64b0e5453ec2b4f8710a31ce
URL:
https://urldefense.proofpoint.com/v2/url?u=http-3A__cgit.freedesktop.org_mesa_mesa_commit_-3Fid-3Dce562f9e3fab769d64b0e5453ec2b4f8710a31ce&d=DwIGaQ&c=uilaK90D4TOVoH58J
On Sun, Apr 16, 2017 at 8:32 PM, Jason Ekstrand wrote:
> On Fri, Apr 14, 2017 at 5:35 PM, Anuj Phogat wrote:
>>
>> From: Jason Ekstrand
>>
>> Signed-off-by: Anuj Phogat
>> ---
>> src/intel/Makefile.sources |3 +-
>> src/intel/genxml/gen10.xml | 3557
>> +
None of the PCI id headers have licensing information. Let's add
the standard Mesa license.
---
include/pci_ids/i810_pci_ids.h | 22 ++
include/pci_ids/i915_pci_ids.h | 22 ++
include/pci_ids/i965_pci_ids.h | 22 ++
incl
https://bugs.freedesktop.org/show_bug.cgi?id=100693
Matt Turner changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
https://bugs.freedesktop.org/show_bug.cgi?id=100693
--- Comment #4 from sav...@ukr.net ---
Probably I should have explained earlier. ICC tries to be GCC on *unix and MSVC
on Windows. E.g. on Windows it has almost the same compiler keys, use MSVC
Linker and Librarian, Windows SDK headers, etc. Thus
https://bugs.freedesktop.org/show_bug.cgi?id=99116
--- Comment #9 from Boyan Ding ---
(In reply to jr from comment #8)
> The patch fixes the problem on NVA5 for both games mentioned above and also
> similar symptoms in Septerra Core and Gothic (both also using wine). Whether
> the patch is correc
Hello,
Currently etnaviv chooses supertiled layout always for new resources that can
be rendered to, when this is available:
bool want_supertiled = screen->specs.can_supertile &&
!DBG_ENABLED(ETNA_DBG_NO_SUPERTILE);
However, etnaviv does not support render *from* supertiled textures (GC3000
https://bugs.freedesktop.org/show_bug.cgi?id=99116
--- Comment #8 from jr ---
The patch fixes the problem on NVA5 for both games mentioned above and also
similar symptoms in Septerra Core and Gothic (both also using wine). Whether
the patch is correct I have no clue.
--
You are receiving this m
I don't see anything in here that actually implements parallel shader
compilation. Does radeon already spawn back-end threads to compile shaders
or are we just lying about it? Even if it does, the front-end tends to
take significant quantities of time so it'd be nice to parallelize that.
On Mon,
The whole point of this extension is to allow applications to query
compilation status without stalling, waiting for the compile. That
means that glCompileShader/glLinkProgram should return immediately
while the real work proceeds in the background. I don't think you've
done that here.
As an aside
https://bugs.freedesktop.org/show_bug.cgi?id=99246
Emil Velikov changed:
What|Removed |Added
Resolution|--- |FIXED
Status|REOPENED
The first release candidate for Mesa 17.1.0 is now available.
The plan is to have one release candidate every Friday, until the final
release on 5th May 2017.
The expectation is that the 17.0 branch will remain alive with bi-weekly
releases until the 17.1.1 release.
Here are the people which he
Mesa 17.0.4 is now available.
In this release we have:
The radeonsi driver has PCI IDs for new Polaris10 devices. While r600 has
improved error handling in OOM conditions.
There is a GBM flush fix for VMWGFX and other drivers that queue DMA operations
on the mapping context. A performance regres
Signed-off-by: Edward O'Callaghan
---
src/mesa/main/extensions_table.h | 1 +
src/mesa/main/mtypes.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/src/mesa/main/extensions_table.h b/src/mesa/main/extensions_table.h
index d11cb0f..58ac77a 100644
--- a/src/mesa/main/extensions_tab
Signed-off-by: Edward O'Callaghan
---
docs/features.txt | 2 +-
src/mesa/state_tracker/st_extensions.c | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/docs/features.txt b/docs/features.txt
index 5f63632..4021fbc 100644
--- a/docs/features.txt
+++ b/docs/f
Signed-off-by: Edward O'Callaghan
---
src/mesa/main/get.c| 4
src/mesa/main/mtypes.h | 6 ++
src/mesa/main/shaderapi.c | 20
src/mesa/main/shaderapi.h | 3 +++
src/mesa/main/shared.c |
Hi folks,
This is my early draft on the threaded shader compile "suggestion"
thread. The requirements according the spec are rather weak as
it is up to the implementation, which frankly can even just ignore
the requested thread count. However, afaik in the case of radeonsi
it is already threaded.
On Thu, Apr 13, 2017 at 11:23 AM, Rob Clark wrote:
> This is equivalent to what mesa/st does in glsl_to_tgsi. For most hw
> there isn't a particularly good reason to treat these differently.
>
> Signed-off-by: Rob Clark
> ---
> This is part of a larger patchset I'm working on to add SSBO and com
On 16 March 2017 at 12:22, Emil Velikov wrote:
> On 16 March 2017 at 09:24, Tapani Pälli wrote:
>> Fixes: efd63e2 ("mesa: Connect the generated GL command marshalling code to
>> the build.")
>> Signed-off-by: Tapani Pälli
>> ---
>> src/mesa/Android.gen.mk | 4 +++-
>> 1 file changed, 3 inserti
On 17 April 2017 at 05:01, Edward O'Callaghan
wrote:
> On 04/03/2017 06:37 PM, Nicolai Hähnle wrote:
>> On 01.04.2017 12:48, Mauro Rossi wrote:
>>> Fixes the following build error:
>>>
>>> external/mesa/src/amd/addrlib/gfx9/gfx9addrlib.cpp:36:10: fatal error:
>>> 'gfx9_gb_reg.h' file not found
>>>
Actually Clang complains with this patch, it reports a compilation error
because 'usage' is an integer. I dropped the change.
On 04/14/2017 06:32 PM, Samuel Pitoiset wrote:
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/radeon/r600_cs.h | 2 +-
1 file changed, 1 insertion(+), 1 dele
https://bugs.freedesktop.org/show_bug.cgi?id=100693
--- Comment #3 from Hi-Angel ---
> Yes, but for some reason it does not reproduced for MSVC Debug builds, which
> use the same toolchain and headers.
> Whether it's possible to figure out, that this is an ICC bug? Then it would be
> possible to
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