Reviewed-by: Samuel Iglesias Gonsálvez
:-D
On Fri, 2017-01-13 at 22:53 -0800, Kenneth Graunke wrote:
> Everything is in place and the test results look solid.
>
> Signed-off-by: Kenneth Graunke
> ---
> src/mesa/drivers/dri/i965/intel_extensions.c | 2 +-
> src/mesa/drivers/dri/i965/intel_scre
On Fri, 2017-01-13 at 12:15 -0200, Alejandro Piñeiro wrote:
> When the attachment type is NONE (att->Type),
> FRAMEBUFFER_ATTACHMENT_OBJECT_TYPE should be NONE too.
>
> Note that technically, the current behaviour follows the spec. From
> OpenGL 4.5 spec, Section 9.2.3 "Framebuffer Object Queries"
On Fri, 2017-01-13 at 08:29 -0800, Jason Ekstrand wrote:
On Fri, Jan 13, 2017 at 1:33 AM, Samuel Iglesias Gonsálvez
wrote:
Fixes crash in dEQP-VK.ubo.random.all_shared_buffer.48 due to a
fragment shader code bigger than 128 kB.
This patch increases the allocation size limit to 256 kB.
That li
On Sun, 15 Jan 2017 22:06:01 +0100
Axel Davy wrote:
As far as I remember this doesn't affact wine, as it resets the offset
in case no depth buffer is attached.
The same could be done in nine, but would add some overhead and
it isn't required on other gallium drivers.
Regards,
Patrick
> Shouldn't
Yes! Simplifies current situation quite a bit and makes Vulkan Android
build possible, I'll submit that if/when this one lands.
There's one thing that caused problems with Android, I've marked it
below .. with that removed;
Acked-by: Tapani Pälli
On 01/13/2017 06:51 PM, Emil Velikov wrote:
On 01/13/2017 08:55 PM, Thomas Helland wrote:
2017-01-13 18:41 GMT+01:00 Vladislav Egorov :
13.01.2017 15:31, Tapani Pälli пишет:
On 01/12/2017 09:23 PM, Thomas Helland wrote:
Walking the whole hash table, inserting entries by hashing them first
is just a really really bad idea. We can s
From: Marek Olšák
The next patch will add SPI_BUSY monitoring.
---
src/gallium/drivers/radeon/r600_gpu_load.c| 64 ---
src/gallium/drivers/radeon/r600_pipe_common.h | 15 +--
src/gallium/drivers/radeon/r600_query.c | 6 +--
3 files changed, 53 insertions(+)
From: Marek Olšák
---
src/gallium/drivers/radeonsi/si_shader.c| 4 ++--
src/gallium/drivers/radeonsi/si_shader.h| 4 ++--
src/gallium/drivers/radeonsi/si_state.c | 6 +++---
src/gallium/drivers/radeonsi/si_state.h | 2 +-
src/gallium/drivers/radeonsi/si_state_shad
From: Marek Olšák
---
src/gallium/drivers/radeonsi/si_shader.c | 52 +++-
src/gallium/drivers/radeonsi/si_shader.h | 12 ++--
src/gallium/drivers/radeonsi/si_state.c | 44 ++-
3 files changed, 90 insertions(+), 18 deletions(-)
diff --git
From: Marek Olšák
It should be close to the GPU load, but it can be much lower if something
is stalling shader execution (e.g. CP DMA).
---
src/gallium/drivers/radeon/r600_gpu_load.c| 16
src/gallium/drivers/radeon/r600_pipe_common.h | 4
src/gallium/drivers/radeon/r60
From: Marek Olšák
so that the graphs are independent from FPS.
---
src/gallium/drivers/radeon/r600_perfcounter.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/radeon/r600_perfcounter.c
b/src/gallium/drivers/radeon/r600_perfcounter.c
index 0c55fc2..4671b
From: Marek Olšák
---
src/gallium/drivers/radeonsi/si_shader.c | 14 --
src/gallium/drivers/radeonsi/si_shader.h | 2 ++
src/gallium/drivers/radeonsi/si_state.c | 11 ++-
3 files changed, 20 insertions(+), 7 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_shader.
From: Marek Olšák
---
src/gallium/auxiliary/hud/hud_context.c | 10 ++
src/gallium/auxiliary/hud/hud_driver_query.c | 18 +-
src/gallium/auxiliary/hud/hud_private.h | 2 ++
3 files changed, 29 insertions(+), 1 deletion(-)
diff --git a/src/gallium/auxiliary/hud
From: Marek Olšák
---
src/gallium/auxiliary/hud/hud_context.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/auxiliary/hud/hud_context.c
b/src/gallium/auxiliary/hud/hud_context.c
index 7fa62a9..9f067f3 100644
--- a/src/gallium/auxiliary/hud/hud_context.c
+++ b/s
On Monday, January 9, 2017 11:58:45 AM PST Marek Olšák wrote:
> On Mon, Jan 9, 2017 at 7:25 AM, Michel Dänzer wrote:
> > On 09/01/17 03:13 PM, Michel Dänzer wrote:
> >> On 07/01/17 11:46 PM, Marek Olšák wrote:
> >>> From: Marek Olšák
> >>>
> >>> ~/.drirc is created by the driconf tool (GPL licens
On Sunday, January 15, 2017 12:19:36 PM PST Jordan Justen wrote:
> Maybe you should drop 'TCS' from the subject? I think TCS is the
> reason for the change, but it doesn't only affect TCS barrier
> messages, right?
Well, scalar TCS and CS are already in align1 mode, so even though
this is common c
https://bugs.freedesktop.org/show_bug.cgi?id=99116
--- Comment #6 from Fabian Maurer ---
Created attachment 128976
--> https://bugs.freedesktop.org/attachment.cgi?id=128976&action=edit
Apitrace from the editor for a game called N-Ball
Probably a second instance of this issue, this time with a
https://bugs.freedesktop.org/show_bug.cgi?id=98428
Laurent carlier changed:
What|Removed |Added
CC||lordhea...@gmail.com
--
You are recei
Wait a sec. Nevermind. It's something else. Trace replays fine in Mesa
13.0.3. Ignore this patch.
On Sun, Jan 15, 2017 at 4:08 PM, Ilia Mirkin wrote:
> Well, the trace in question rendered just fine on NVIDIA blob... I'm
> kind of assuming that I just missed something in the spec, or all
> other
Well, the trace in question rendered just fine on NVIDIA blob... I'm
kind of assuming that I just missed something in the spec, or all
other HW works this way, or ... .
On Sun, Jan 15, 2017 at 4:06 PM, Axel Davy wrote:
> Shouldn't this be fixed in wine, rather than in the driver ?
>
>
> Yours,
>
Shouldn't this be fixed in wine, rather than in the driver ?
Yours,
Axel
On 15/01/2017 21:57, Ilia Mirkin wrote:
While I can find no support for this in the GL spec, this is apparently
what D3D9 wants. Also appears to fix a very long-standing bug in Tomb
Raider: Underworld and Deus Ex: Human
While I can find no support for this in the GL spec, this is apparently
what D3D9 wants. Also appears to fix a very long-standing bug in Tomb
Raider: Underworld and Deus Ex: Human Revolution (probably based on the
same engines).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91247
Referenc
While I can find no support for this in the GL spec, this is apparently
what D3D9 wants. Also appears to fix a very long-standing bug in Tomb
Raider: Underworld and Deus Ex: Human Revolution (probably based on the
same engines).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91247
Referenc
Maybe you should drop 'TCS' from the subject? I think TCS is the
reason for the change, but it doesn't only affect TCS barrier
messages, right?
On 2017-01-15 01:45:45, Kenneth Graunke wrote:
> In commit 7428e6f86ab5 we switched the barrier SEND message's
> destination type to UW to avoid problems
This is simply keyed off the vertex shader, as that's guaranteed to be
present in any pipeline.
Signed-off-by: Ilia Mirkin
---
Note - untested on nv50. I started with very similar code for nvc0 though,
which "worked" until I realized that the UNK1690 reg totally changed on Kepler.
.../drivers
Signed-off-by: Ilia Mirkin
---
src/gallium/state_trackers/nine/nine_shader.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/gallium/state_trackers/nine/nine_shader.c
b/src/gallium/state_trackers/nine/nine_shader.c
index 0a75c07..cb25253 100644
--- a/src/gallium/state_trackers/nine/nine_
This will be useful for proper D3D9 emulation, where this behavior is
expected by some shaders.
Signed-off-by: Ilia Mirkin
---
src/gallium/auxiliary/tgsi/tgsi_strings.c | 3 ++-
src/gallium/docs/source/tgsi.rst | 14 --
src/gallium/include/pipe/p_shader_tokens.h | 1 +
3
This had been updated in one place but not the other.
Signed-off-by: Ilia Mirkin
---
Not sure about that first one - should it do count++ irrespectively, and then
count++ again for <= GM200? Or can all that checking stuff just go away?
src/gallium/drivers/nouveau/nvc0/nvc0_query.c | 4 ++--
1
On 01/14/2017 02:35 AM, Ilia Mirkin wrote:
The NVEA 3D class is numerically larger than the NVF0 3D class. The TK1
chip uses the SM35 ISA and likely has the same hw counters. Allow these
to be used like on all the other supported chips.
This actually needs more testing. Perf counters are pret
https://bugs.freedesktop.org/show_bug.cgi?id=98428
--- Comment #17 from Darek ---
Segfault after
'0003-mesa-glapi-Clean-up-dlopening-glapi-as-we-are-buildi.patch'
---
$ weston
GL_EXT_copy_image GL_EXT_draw_elements_base_vertex
GL_EXT_polygon_offset_clamp GL_EXT_text
In commit 7428e6f86ab5 we switched the barrier SEND message's
destination type to UW to avoid problems in SIMD16 compute shaders.
Tessellation control shaders also use barriers, and in vec4 mode, we
were emitting them in align16 mode. The simulator warns that only UD,
D, F, and DF are valid desti
On Thursday, January 12, 2017 1:41:10 PM PST Eero Tamminen wrote:
> Hi,
>
> On 11.01.2017 20:07, Lionel Landwerlin wrote:
> > On 11/01/17 17:02, Eero Tamminen wrote:
> >> On 09.01.2017 07:26, Kenneth Graunke wrote:
> >>> Signed-off-by: Kenneth Graunke
> >>> ---
> >>> src/intel/vulkan/anv_device.
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