On 04/12/16 01:09 AM, srol...@vmware.com wrote:
> From: Roland Scheidegger
>
> Trivial, this just resurrects the code which was there once upon a time
> (the code can't lower instructions generated in the lowering pass there,
> and even if it could it would probably be suboptimal).
> This fixes p
This is a step towards using NIR optimisations over GLSL IR
optimisations. Delaying adding built-in uniforms until after
we convert to NIR gives it a chance to optimise them away.
V2: move the new code back to brw_link_shader()
---
src/mesa/drivers/dri/i965/brw_link.cpp | 42 +++--
On Mon, 2016-12-05 at 21:13 -0800, Kenneth Graunke wrote:
> This was a hack which worked around the VS and TCS disagreeing on
> their
> shared interface due to the lack of varying packing. In particular,
> it
> was needed by Piglit's tcs-input-read-array-interface test.
>
> However, that was just
On 06/12/16 02:39 AM, Tim Rowley wrote:
> Use llvm provided API based on cpuid rather than our own
> manually mantained list of mattr enabling/disabling.
This change broke the llvmpipe unit test lp_test_format for me:
Testing PIPE_FORMAT_R32_FLOAT (float) ...
FAILED
Packed: 00 00 00 00
Unpack
We would really like it to be false as that's what you get on hardware that
doesn't have RegisterPoleMode (Sky Lake for example). While we're at it,
we change it to a boolean. This fixes dEQP-VK.synchronization.smoke.events
on Broxton.
Cc: "13.0"
---
src/intel/genxml/gen9.xml | 2 +-
1 file ch
This is a step towards using NIR optimisations over GLSL IR
optimisations. Delaying adding built-in uniforms until after
we convert to NIR gives it a chance to optimise them away.
---
src/mesa/drivers/dri/i965/brw_link.cpp | 23 ---
src/mesa/drivers/dri/i965/brw_program.c | 19
A while ago, I made i965 start compiling shaders independently. The VUE
map layouts were based entirely on each shader's input/output bitfields.
Assuming the interfaces match, this works out well - both sides will
compute the same layout, and outputs are correctly routed to inputs.
At the time, I
This was a hack which worked around the VS and TCS disagreeing on their
shared interface due to the lack of varying packing. In particular, it
was needed by Piglit's tcs-input-read-array-interface test.
However, that was just one case where things could go awry, so the
previous commit forcibly ma
On Mon, Dec 05, 2016 at 05:56:40PM +, Emil Velikov wrote:
> On 1 December 2016 at 04:18, Jonathan Gray wrote:
> > DRI devices on OpenBSD are not in their own directory. They reside in
> > /dev with a large number of statically generated /dev nodes.
> >
> > Avoid stat'ing all of /dev on OpenBS
On Thursday, December 1, 2016 8:53:16 AM PST Iago Toral Quiroga wrote:
> This was written specifically for RECT samplers. Make it more generic so
> we can call this from the gradient lowerings too.
> ---
> src/compiler/nir/nir_lower_tex.c | 15 ++-
> 1 file changed, 10 insertions(+), 5
On Thursday, December 1, 2016 8:53:19 AM PST Iago Toral Quiroga wrote:
> This is ported from the Intel lowering pass that we use with GLSL IR.
> This takes care of lowering texture gradients on shadow samplers other
> than cube maps. Intel hardware requires this for gen < 8.
> ---
> src/compiler/n
This patch is to potentially remove ourself from the maintaince
burden of the ilo driver that appears to now be essentially
unmaintained?
I am not sure of our policy here or if there are too many
users so this patch is really only to gauge a response of
how folks feel?
Kind Regards,
Edward O'Cal
On 12/05/2016 10:31 AM, Matt Turner wrote:
> On Wed, Nov 30, 2016 at 1:11 PM, Matt Turner wrote:
>> On 11/28, Ian Romanick wrote:
>>>
>>> From: Ian Romanick
>>>
>>> I believe that I have addressed all of the review feedback from the
>>> previous iteration. Many of the patches have been reviewed,
On Mon, 2016-12-05 at 11:59 -0800, Jason Ekstrand wrote:
> From: Timothy Arceri
>
Just in case this lands before NIR loop unrolling I've just sent a
slightly updated patch [1] in the latest series.
[1] https://patchwork.freedesktop.org/patch/125758/
> This moves the nir_lower_indirect_derefs()
This will be useful for fixing phi srcs when cloning a loop body
during loop unrolling.
---
src/compiler/nir/nir_clone.c | 36 +---
1 file changed, 21 insertions(+), 15 deletions(-)
diff --git a/src/compiler/nir/nir_clone.c b/src/compiler/nir/nir_clone.c
index 4f7b
V2:
- enable on all gens
---
src/mesa/drivers/dri/i965/brw_compiler.c | 5 -
src/mesa/drivers/dri/i965/brw_nir.c | 22 +-
2 files changed, 21 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_compiler.c
b/src/mesa/drivers/dri/i965/brw_compiler
V2:
- updated to create a generic list clone helper nir_cf_list_clone()
- continue to assert on clone when fallback flag not set as suggested
by Jason.
---
src/compiler/nir/nir_clone.c| 58 +++--
src/compiler/nir/nir_control_flow.h | 3 ++
2 files changed
---
src/compiler/nir/nir_opt_remove_phis.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/compiler/nir/nir_opt_remove_phis.c
b/src/compiler/nir/nir_opt_remove_phis.c
index acaa6e1..d4344b0 100644
--- a/src/compiler/nir/nir_opt_remove_phis.c
+++ b/src/compiler/nir/nir_o
From: Thomas Helland
V2: Do a "depth first search" to convert to LCSSA
V3: Small comment fixup
V4: Rebase, adapt to removal of function overloads
V5: Rebase, adapt to relocation of nir to compiler/nir
Still need to adapt to potential if-uses
Work around nir_validate issue
V6 (Timothy)
Later we will pass compiler to nir_optimise to be used by the loop unroll
pass.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 10 --
src/mesa/drivers/dri/i965/brw_nir.c | 7 ---
src/mesa/drivers/dri/i965/brw_nir.h | 4 ++--
src/mesa/drivers/dri/i
V2:
- tidy ups suggested by Connor.
- tidy up cloning logic and handle copy propagation
based of suggestion by Connor.
- use nir_ssa_def_rewrite_uses to fix up lcssa phis
suggested by Connor.
- add support for complex loop unrolling (two terminators)
- handle case were the ssa defs use outside t
Again thanks to Jason and Connor for their feedback, and to
Thomas for getting this work started.
V6: Is mainly just a rebase but fixes a few regressions cause by
ralloc() being fixed recently to not zero out memory. There is also a fix for
the analysis pass for detecting jump instructions when a
This moves the nir_lower_indirect_derefs() call into
brw_preprocess_nir() so thats is called by both OpenGL and Vulkan
and removes that call to the old GLSL IR pass
lower_variable_index_to_cond_assign()
We want to do this pass in nir to be able to move loop unrolling
to nir.
There is a increase o
From: Thomas Helland
This pass detects induction variables and calculates the
trip count of loops to be used for loop unrolling.
I've removed support for float induction values for now, for the
simple reason that they don't appear in my shader-db collection,
and so I don't see it as common enoug
Without this we will regress the max-samplers piglit test on Gen6
and lower when loop unrolling is done in NIR. There is a check
in the GLSL IR linker that errors when it finds indirects and
EmitNoIndirectSampler is set.
As far as I can tell there is no reason for not enabling this for
all gens re
---
src/intel/vulkan/gen8_cmd_buffer.c | 24
1 file changed, 20 insertions(+), 4 deletions(-)
diff --git a/src/intel/vulkan/gen8_cmd_buffer.c
b/src/intel/vulkan/gen8_cmd_buffer.c
index 3e4aa9b..6b56d06 100644
--- a/src/intel/vulkan/gen8_cmd_buffer.c
+++ b/src/intel/vulka
On 12/05/2016 01:39 PM, Kenneth Graunke wrote:
> Allocating zero URB space is a really bad idea. The hardware has to
> give threads a handle to their URB space, and threads have to use that
> to terminate the thread. Having it be an empty region just breaks a
> lot of assumptions. Hence, why we
On Mon, Dec 5, 2016 at 5:48 PM, Matt Turner wrote:
> On Mon, Dec 5, 2016 at 2:20 PM, Connor Abbott wrote:
>> On Mon, Dec 5, 2016 at 5:09 PM, Connor Abbott wrote:
>>> On Mon, Dec 5, 2016 at 3:22 PM, Matt Turner wrote:
On 12/05, Matt Turner wrote:
>
> On 11/28, Ian Romanick wrote:
>>
Leo Liu wrote:
Hi Andy,
Please rebase all your reviewed patches, and add RB, and send them to me
I will commit them for you.
Ok, thanks, I've sent two to you.
Cheers,
Leo
On 12/05/2016 03:14 PM, Andy Furniss wrote:
Hi, I did a v2, can it be applied?
https://patchwork.freedesktop.org/p
Just fyi I have not tested this, however it should fix the
problem highlighted.
Please kindly Review,
Edward O'Callaghan (1):
[PATCH] virgl: Fix a strict-aliasing violation in the encoder
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https:/
As per the C spec, it is illegal to alias pointers to different
types. This results in undefined behaviour after optimization
passes, resulting in very subtle bugs that happen only on a
full moon..
Use a memcpy() as a well defined coercion between the double
to uint64_t interpretations of the memo
On Thu, Jul 21, 2016 at 2:52 AM, Iago Toral wrote:
> On Wed, 2016-07-20 at 15:28 -0700, Jason Ekstrand wrote:
> > Signed-off-by: Jason Ekstrand
> > ---
> > src/compiler/Makefile.sources | 1 +
> > src/compiler/nir/nir.h | 2 +
> > src/compile
On 10/11, Iago Toral Quiroga wrote:
It's been some time since
... anyone has reviewed your patches. Sorry. :(
I'm going to review from your rebased i965-fp64-gen7-scalar-vec4-rc2
branch. There have probably been some reorderings or other changes due
to rebasing since the patches were sent, so
> On Dec 5, 2016, at 11:52 AM, Emil Velikov wrote:
>
> From: Emil Velikov
>
> No point in having an identical code in two places.
>
> Not to mention that the Apple one incorrectly uses GLXDrawable as pbuf
> type. This change is both API and ABI safe since the header uses the
> correct GLXPbuf
On Mon, Dec 5, 2016 at 2:20 PM, Connor Abbott wrote:
> On Mon, Dec 5, 2016 at 5:09 PM, Connor Abbott wrote:
>> On Mon, Dec 5, 2016 at 3:22 PM, Matt Turner wrote:
>>> On 12/05, Matt Turner wrote:
On 11/28, Ian Romanick wrote:
>
> From: Ian Romanick
>Patches 42 through 5
On Mon, Dec 5, 2016 at 1:39 PM, Kenneth Graunke wrote:
> Allocating zero URB space is a really bad idea. The hardware has to
> give threads a handle to their URB space, and threads have to use that
> to terminate the thread. Having it be an empty region just breaks a
> lot of assumptions. Hence
On 05/12/16 19:52, Emil Velikov wrote:
From: Emil Velikov
Analogoust to the previous commit were we did so for autotools
Cc: Jose Fonseca
Signed-off-by: Emil Velikov
---
Jose, I'm not 100% sure if that holds true the compiler(s) that you
gents use. Can you please double-check ?
Thanks
Emil
On Mon, Dec 5, 2016 at 5:09 PM, Connor Abbott wrote:
> On Mon, Dec 5, 2016 at 3:22 PM, Matt Turner wrote:
>> On 12/05, Matt Turner wrote:
>>>
>>> On 11/28, Ian Romanick wrote:
From: Ian Romanick
Patches 42 through 50 enable the extension on BDW+.
>>>
>>>
>>> 42-48 are
>>>
>>> R
On Mon, Dec 5, 2016 at 3:22 PM, Matt Turner wrote:
> On 12/05, Matt Turner wrote:
>>
>> On 11/28, Ian Romanick wrote:
>>>
>>> From: Ian Romanick
>>>Patches 42 through 50 enable the extension on BDW+.
>>
>>
>> 42-48 are
>>
>> Reviewed-by: Matt Turner
>>
>> I don't understand the 64-bit CMP is
Ack
On Mon, Dec 5, 2016 at 1:47 PM, Nanley Chery wrote:
> ---
>
> Hi everyone,
>
> I'm about to start working on this task.
>
> src/intel/vulkan/TODO | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/src/intel/vulkan/TODO b/src/intel/vulkan/TODO
> index abfe4b6..915f423 100644
> --- a/sr
---
Hi everyone,
I'm about to start working on this task.
src/intel/vulkan/TODO | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/intel/vulkan/TODO b/src/intel/vulkan/TODO
index abfe4b6..915f423 100644
--- a/src/intel/vulkan/TODO
+++ b/src/intel/vulkan/TODO
@@ -16,6 +16,7 @@ Code sharing
Allocating zero URB space is a really bad idea. The hardware has to
give threads a handle to their URB space, and threads have to use that
to terminate the thread. Having it be an empty region just breaks a
lot of assumptions. Hence, why we asserted that it isn't possible.
Unfortunately, it /is
Emil Velikov writes:
> From: Emil Velikov
>
> In the (not too) distant future we'd want to remove this option and
> effectively drop the other codepath(s) we have in our dispatch.
>
> Linux distributions have been using --enable-glx-tls for a number of
> years. Some/most BSD platforms still don'
Matt Turner writes:
> On Wed, Nov 30, 2016 at 1:11 PM, Matt Turner wrote:
>> On 11/28, Ian Romanick wrote:
>>>
>>> From: Ian Romanick
>>>
>>> I believe that I have addressed all of the review feedback from the
>>> previous iteration. Many of the patches have been reviewed, and they
>>> should
Hi Andy,
Please rebase all your reviewed patches, and add RB, and send them to me
I will commit them for you.
Cheers,
Leo
On 12/05/2016 03:14 PM, Andy Furniss wrote:
Hi, I did a v2, can it be applied?
https://patchwork.freedesktop.org/patch/118006/
Christian König wrote:
Am 25.10.2016
On 12/05/2016 12:24 PM, Matt Turner wrote:
> The PRMs for HSW and newer say that other than the opcode and DebugCtrl
> bits of the instruction word, the rest must be zero.
>
> By zeroing the instruction word manually, we avoid using any of the
> state inherited through brw_codegen.
>
> Bug: https
On Dec 5, 2016 12:14 PM, "Connor Abbott" wrote:
I'm a little worried about this since it seems like the
load/store_scratch intrinsics are basically doing the same thing as
registers were originally intended to do. Either we should use the
existing register lowering, and make it conditional on the
The PRMs for HSW and newer say that other than the opcode and DebugCtrl
bits of the instruction word, the rest must be zero.
By zeroing the instruction word manually, we avoid using any of the
state inherited through brw_codegen.
Bug: https://bugs.freedesktop.org/show_bug.cgi?id=96959
---
src/me
On 12/05, Matt Turner wrote:
On 11/28, Ian Romanick wrote:
From: Ian Romanick
Patches 42 through 50 enable the extension on BDW+.
42-48 are
Reviewed-by: Matt Turner
I don't understand the 64-bit CMP issue, so I'm booting a SKL to see how
fp64 works.
Ah, I think I see. Because 16x dou
Hi, I did a v2, can it be applied?
https://patchwork.freedesktop.org/patch/118006/
Christian König wrote:
Am 25.10.2016 um 00:39 schrieb Andy Furniss:
For gstreamer
Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=91281
Signed-off-by: Andy Furniss
---
src/gallium/drivers/radeon/radeon_v
I'm a little worried about this since it seems like the
load/store_scratch intrinsics are basically doing the same thing as
registers were originally intended to do. Either we should use the
existing register lowering, and make it conditional on the size like
you've done here, or we should just gut
Can you apply this please.
Christian König wrote:
Am 25.10.2016 um 00:46 schrieb Andy Furniss:
Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=91281
Signed-off-by: Andy Furniss
Reviewed-by: Christian König .
---
src/gallium/state_trackers/omx/vid_enc.c | 2 +-
1 file changed, 1 ins
---
src/mesa/drivers/dri/i965/brw_defines.h| 6 ++
src/mesa/drivers/dri/i965/brw_fs.h | 3 +++
src/mesa/drivers/dri/i965/brw_fs_cse.cpp | 1 +
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 28 ++
src/mesa/drivers/dri/i965/brw_fs_nir.cpp
---
src/mesa/drivers/dri/i965/brw_nir.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_nir.c
b/src/mesa/drivers/dri/i965/brw_nir.c
index 8768cee..f75db4d 100644
--- a/src/mesa/drivers/dri/i965/brw_nir.c
+++ b/src/mesa/drivers/dri/i965/brw_nir.c
@@ -485,6 +485
---
src/compiler/Makefile.sources| 1 +
src/compiler/nir/nir.h | 8 +-
src/compiler/nir/nir_clone.c | 1 +
src/compiler/nir/nir_lower_scratch.c | 258 +++
4 files changed, 267 insertions(+), 1 deletion(-)
create mode 100644 src/c
From: Timothy Arceri
This moves the nir_lower_indirect_derefs() call into
brw_preprocess_nir() so thats is called by both OpenGL and Vulkan
and removes that call to the old GLSL IR pass
lower_variable_index_to_cond_assign()
We want to do this pass in nir to be able to move loop unrolling
to nir.
---
src/mesa/drivers/dri/i965/brw_defines.h| 2 +
src/mesa/drivers/dri/i965/brw_fs.cpp | 2 +
src/mesa/drivers/dri/i965/brw_fs.h | 3 +
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 142 +
src/mesa/drivers/dri/i965/brw_shader.cpp
This uses either the normal scratch read/write messages that we use for
spilling or the DWORD scattered read/write messages for when we have
indirects.
---
src/mesa/drivers/dri/i965/brw_defines.h | 2 +
src/mesa/drivers/dri/i965/brw_fs.cpp | 111 ++
src
---
src/compiler/nir/nir_intrinsics.h | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/src/compiler/nir/nir_intrinsics.h
b/src/compiler/nir/nir_intrinsics.h
index f45bfe2..d269805 100644
--- a/src/compiler/nir/nir_intrinsics.h
+++ b/src/compiler/nir/nir_intrinsics.h
@@ -41
This little series implements lowering of indirectly accessed local
variables larger than some threshold (8 floats?) to scratch space. This
improves the performance of the CSDof synmark test by about 45% because it
uses a large temporary array which we lower to if-ladders and then to piles
of scra
On 12/05/2016 11:52 AM, Emil Velikov wrote:
> From: Emil Velikov
>
> Use the macro, rather than open-coding it.
>
> Signed-off-by: Emil Velikov
> ---
> src/glx/glxcmds.c | 17 -
> 1 file changed, 4 insertions(+), 13 deletions(-)
>
> diff --git a/src/glx/glxcmds.c b/src/glx/glx
From: Emil Velikov
Analogous to previous two commits.
Strictly speaking it's not be applicable for Android since we don't
build GLX and related code.
Regardless keep things consistent with the other build systems.
Cc: Rob Herring
Signed-off-by: Emil Velikov
---
Android.common.mk | 1 +
1 fi
From: Emil Velikov
Use the macro, rather than open-coding it.
Signed-off-by: Emil Velikov
---
src/glx/glxcmds.c | 17 -
1 file changed, 4 insertions(+), 13 deletions(-)
diff --git a/src/glx/glxcmds.c b/src/glx/glxcmds.c
index 7266b58..6c7bbfd 100644
--- a/src/glx/glxcmds.c
+++
From: Emil Velikov
Quick search through git history (of both mesa and xserver) hows no
instances where this was ever set.
Signed-off-by: Emil Velikov
---
src/glx/glxextensions.h | 5 -
1 file changed, 5 deletions(-)
diff --git a/src/glx/glxextensions.h b/src/glx/glxextensions.h
index 743e
From: Emil Velikov
No point in having an identical code in two places.
Not to mention that the Apple one incorrectly uses GLXDrawable as pbuf
type. This change is both API and ABI safe since the header uses the
correct GLXPbufferSGIX and both types are a typedef of the same
primitive XID.
Cc: J
From: Emil Velikov
Analogoust to the previous commit were we did so for autotools
Cc: Jose Fonseca
Signed-off-by: Emil Velikov
---
Jose, I'm not 100% sure if that holds true the compiler(s) that you
gents use. Can you please double-check ?
Thanks
Emil
---
include/c99_compat.h | 1 +
1 file c
From: Emil Velikov
We must make sure that xserver has an equivalent one-line
change to its configure.ac as the glx/glapi headers get copied over.
Then again, xserver does _not_ seem to set HAVE_ALIAS to begin with so
one might want to look into that first.
Cc: Adam Jackson
Signed-off-by: Emil
From: Emil Velikov
Currently we have two macros - HAVE_ALIAS and GLX_ALIAS_UNSUPPORTED.
To make it even better former of which is explicitly cleared in some
cases while not in others.
Clear all that up by using a single macro properly set during configure.
Signed-off-by: Emil Velikov
---
conf
Minor nit: i965 in the subject. :)
On 12/05/2016 10:16 AM, Rafael Antognolli wrote:
> Enable getting the results of a transform feedback overflow query with a
> buffer object.
>
> Signed-off-by: Rafael Antognolli
> ---
> src/mesa/drivers/dri/i965/hsw_queryobj.c | 108
>
On 11/28, Ian Romanick wrote:
From: Ian Romanick
Patches 42 through 50 enable the extension on BDW+.
42-48 are
Reviewed-by: Matt Turner
I don't understand the 64-bit CMP issue, so I'm booting a SKL to see how
fp64 works.
signature.asc
Description: Digital signature
On Mon, Dec 05, 2016 at 11:01:54AM -0800, Ian Romanick wrote:
> Aside from my comments on patch 5, you're missing some changes to
> _mesa_BeginConditionalRender. See
> https://cgit.freedesktop.org/~idr/mesa/commit/?h=ARB_transform_feedback_overflow_query&id=c17cf16caa18e44f9d53e05a7279066f8cc2f33c
On Mon, Dec 05, 2016 at 10:57:16AM -0800, Ian Romanick wrote:
> On 12/05/2016 10:16 AM, Rafael Antognolli wrote:
> > Signed-off-by: Rafael Antognolli
> > ---
> > src/mesa/drivers/dri/i965/intel_extensions.c | 1 +
> > src/mesa/main/extensions_table.h | 1 +
> > src/mesa/main/get.c
From: Emil Velikov
Mesa requires ax_pthread_ok = yes, thus we can fold/rewrite the
conditional to follow the more common "if test" pattern.
No functional change intended.
Signed-off-by: Emil Velikov
---
configure.ac | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/conf
From: Emil Velikov
In the (not too) distant future we'd want to remove this option and
effectively drop the other codepath(s) we have in our dispatch.
Linux distributions have been using --enable-glx-tls for a number of
years. Some/most BSD platforms still don't support this, yet this should
ser
Aside from my comments on patch 5, you're missing some changes to
_mesa_BeginConditionalRender. See
https://cgit.freedesktop.org/~idr/mesa/commit/?h=ARB_transform_feedback_overflow_query&id=c17cf16caa18e44f9d53e05a7279066f8cc2f33c.
On 12/05/2016 10:16 AM, Rafael Antognolli wrote:
> Add some basic
On 12/05/2016 10:16 AM, Rafael Antognolli wrote:
> Signed-off-by: Rafael Antognolli
> ---
> src/mesa/drivers/dri/i965/intel_extensions.c | 1 +
> src/mesa/main/extensions_table.h | 1 +
> src/mesa/main/get.c | 1 +
> 3 files changed, 3 insertions(+)
>
> diff
On 12/02/2016 05:04 PM, Matt Turner wrote:
> On Fri, Dec 2, 2016 at 12:22 PM, Emil Velikov
> wrote:
>> On 2 December 2016 at 19:49, Matt Turner wrote:
>>> A user reporting an unrelated bug (98964) said that he has to set
>>> MESA_GL_VERSION_OVERRIDE=1.4 when running Chromium otherwise it's too
>
Am 05.12.2016 um 18:39 schrieb Tim Rowley:
> Use llvm provided API based on cpuid rather than our own
> manually mantained list of mattr enabling/disabling.
> ---
> src/gallium/auxiliary/gallivm/lp_bld_misc.cpp | 15 +++
> 1 file changed, 15 insertions(+)
>
> diff --git a/src/gallium/
Am 05.12.2016 um 16:49 schrieb Philipp Zabel:
> Add a hook to tell drivers that an imported resource may have changed
> and they need to update their internal derived resources.
>
> Signed-off-by: Philipp Zabel
> ---
> Changes since v1:
> - Clarified intended of pipe_screen::resource_changed
> -
On Wed, Nov 30, 2016 at 1:11 PM, Matt Turner wrote:
> On 11/28, Ian Romanick wrote:
>>
>> From: Ian Romanick
>>
>> I believe that I have addressed all of the review feedback from the
>> previous iteration. Many of the patches have been reviewed, and they
>> should be ready to go.
>>
>> Patches m
Add some basic types and storage for the queries of this extension.
Signed-off-by: Rafael Antognolli
---
src/mesa/main/mtypes.h | 5 +
src/mesa/main/queryobj.c| 21 +
src/mesa/state_tracker/st_cb_queryobj.c | 6 ++
3 files changed, 3
Enable getting the results of a transform feedback overflow query with a
buffer object.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/hsw_queryobj.c | 108 +++
1 file changed, 108 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/hsw_queryobj.c
b
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/intel_extensions.c | 1 +
src/mesa/main/extensions_table.h | 1 +
src/mesa/main/get.c | 1 +
3 files changed, 3 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/
When querying for transform feedback overflow on one or all of the
streams, store information about number of generated and written
primitives. Then check whether generated == written.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/brw_queryobj.c | 2 ++
src/mesa/drivers/dri/i
Predication needs cmd parser only on gen7. For newer platforms, it
should be available without it.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/intel_extensions.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/driver
Enable the use of a transform feedback overflow query with
glBeginConditionalRender. The render commands will only execute if the
query is true (i.e. if there was an overflow).
Use ARB_conditional_render_inverted to change this behavior.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri
This patch series is an initial version that implements support for
ARB_transform_feedback_overflow_query on i965. It does that by storing
the initial values of generated and written primitives on glBeginQuery,
and final values on glEndQuery, and then comparing those values.
I still need to write
Reviewed-by: Bruce Cherniak
> On Dec 5, 2016, at 11:39 AM, Rowley, Timothy O
> wrote:
>
> Uses llvmpipe's string formating.
> ---
> src/gallium/drivers/swr/swr_screen.cpp | 12 +++-
> 1 file changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/src/gallium/drivers/swr/swr_screen.cp
On Mon, Dec 05, 2016 at 04:11:21PM +, Emil Velikov wrote:
> From: Emil Velikov
>
> Document what has been the unofficial way to self-reject stable patches.
>
> Namely: drop the mesa-stable tag and push the commit.
>
> Cc: Nanley Chery
> Signed-off-by: Emil Velikov
> ---
> Nanley, I fear t
Reviewed-by: Bruce Cherniak
> On Dec 5, 2016, at 11:40 AM, Tim Rowley wrote:
>
> ---
> src/gallium/drivers/swr/swr_screen.cpp | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/src/gallium/drivers/swr/swr_screen.cpp
> b/src/gallium/drivers/swr/swr_screen.cpp
> index 539acf1..b5c2cd3 100
---
src/gallium/drivers/swr/swr_screen.cpp | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/gallium/drivers/swr/swr_screen.cpp
b/src/gallium/drivers/swr/swr_screen.cpp
index 539acf1..b5c2cd3 100644
--- a/src/gallium/drivers/swr/swr_screen.cpp
+++ b/src/gallium/drivers/swr/swr_screen.cpp
@@
Use llvm provided API based on cpuid rather than our own
manually mantained list of mattr enabling/disabling.
---
src/gallium/auxiliary/gallivm/lp_bld_misc.cpp | 15 +++
1 file changed, 15 insertions(+)
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp
b/src/gallium/auxiliar
Uses llvmpipe's string formating.
---
src/gallium/drivers/swr/swr_screen.cpp | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/swr/swr_screen.cpp
b/src/gallium/drivers/swr/swr_screen.cpp
index 75a9d02..539acf1 100644
--- a/src/gallium/drivers/swr
On Monday, December 5, 2016 1:40:06 PM PST srol...@vmware.com wrote:
> From: Roland Scheidegger
>
> As per GL 4.5 rules, which fixed a spec mistake in GL_ARB_stencil_texturing.
> The extension spec wasn't updated, but just allow it with older GL versions
> as well, hoping there aren't any crazy t
Mesa 12.0.5 is now available.
Note: this is the final anticipated release in the 12.0 series. Users are
encouraged to migrate to the 13.0 series in order to obtain future fixes.
In this release we have:
The SWR driver builds correctly with LLVM 3.7 up-to 3.9. The i965 and radeon
(r600, radeonsi)
On Mon, Dec 5, 2016 at 11:11 AM, Robert Bragg wrote:
>
>
> On Sun, Nov 27, 2016 at 7:23 PM, Ilia Mirkin wrote:
>>
>> The strategy is to just keep n anv_query_pool_slot entries per query
>> instead of one. The available bit is only valid in the last one.
>>
>> Signed-off-by: Ilia Mirkin
>> ---
>>
On Sun, Nov 27, 2016 at 7:23 PM, Ilia Mirkin wrote:
> The strategy is to just keep n anv_query_pool_slot entries per query
> instead of one. The available bit is only valid in the last one.
>
> Signed-off-by: Ilia Mirkin
> ---
>
> I think this is in a pretty good state now. I've tested both the
From: Emil Velikov
Document what has been the unofficial way to self-reject stable patches.
Namely: drop the mesa-stable tag and push the commit.
Cc: Nanley Chery
Signed-off-by: Emil Velikov
---
Nanley, I fear that adding this note to the criteria section will get
lost.
Please let me know if
Hi,
On 10 June 2014 at 15:46, Rob Clark wrote:
> On Mon, Jun 9, 2014 at 5:53 AM, Pekka Paalanen wrote:
>> On Thu, 16 Aug 2012 17:28:19 -0500 Rob Clark wrote:
>>> From: Rob Clark
>>
>> it looks like this patch never made it into Mesa. Also the
>> implementation apparently didn't make it into Me
Implement the resource_changed pipe callback to invalidate internal
resources derived from imported buffers. This is needed to update the
texture for re-imported renderables.
Signed-off-by: Philipp Zabel
---
src/gallium/drivers/etnaviv/etnaviv_resource.c | 13 +
1 file changed, 13 in
1 - 100 of 135 matches
Mail list logo
