Re: [Mesa-dev] [PATCH 3/3] i965/fs: emit DIM instruction to load 64-bit immediates in HSW

On Wed, Jul 13, 2016 at 10:52 PM, Samuel Iglesias Gonsálvez wrote: > > > On 14/07/16 03:46, Matt Turner wrote: >> On Wed, Jul 13, 2016 at 5:06 PM, Matt Turner wrote: >>> On Tue, Jul 12, 2016 at 11:42 PM, Samuel Iglesias Gonsálvez >>> wrote: Signed-off-by: Samuel Iglesias Gonsálvez ---

Re: [Mesa-dev] [PATCH 3/3] i965/fs: emit DIM instruction to load 64-bit immediates in HSW

On 14/07/16 03:46, Matt Turner wrote: > On Wed, Jul 13, 2016 at 5:06 PM, Matt Turner wrote: >> On Tue, Jul 12, 2016 at 11:42 PM, Samuel Iglesias Gonsálvez >> wrote: >>> Signed-off-by: Samuel Iglesias Gonsálvez >>> --- >>> src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 12 >>> 1 file

Re: [Mesa-dev] [PATCH 1/3] i965: enable the emission of the DIM instruction

On 14/07/16 02:04, Matt Turner wrote: > On Tue, Jul 12, 2016 at 11:42 PM, Samuel Iglesias Gonsálvez > wrote: >> Signed-off-by: Samuel Iglesias Gonsálvez >> --- >> src/mesa/drivers/dri/i965/brw_defines.h | 2 +- >> src/mesa/drivers/dri/i965/brw_eu.c | 2 +- >> src/mesa/dr

Re: [Mesa-dev] [PATCH] isl/state: Divide the aux qpitch by 2

Subject says: "isl/state: Divide the aux qpitch by 2". Should be divide by 4 or shift by 2. Otherwise: Reviewed-by: Topi Pohjolainen On Wed, Jul 13, 2016 at 04:45:09PM -0700, Jason Ekstrand wrote: > The field is in multiples of 4 like regular QPitch. > --- > src/intel/isl/isl_surface_state.c

Re: [Mesa-dev] [PATCH mesa v2] vl: fix memory leak

Reviewed-by: Nayan Deshmukh On Thu, Jul 14, 2016 at 3:20 AM, Eric Engestrom wrote: > CovID: 1363008 > Signed-off-by: Eric Engestrom > --- > > v2: avoid using malloc() altogether (Christian König) > > --- > src/gallium/auxiliary/vl/vl_bicubic_filter.c | 8 +--- > 1 file changed, 1 inserti

[Mesa-dev] [PATCH v2] egl/dri2: dri2_make_current: Set EGL error if bindContext fails

From: Nicolas Boichat Without this, if a configuration is, say, available only on GLES2/3, but not on GLES1, and is rejected by the dri module's bindContext call, eglMakeCurrent fails with error "EGL_SUCCESS". In this patch, we set error to EGL_BAD_MATCH, which is what CTS/dEQP dEQP-EGL.function

Re: [Mesa-dev] V3 On disk shader cache for i965 (Now with real world results!)

On Wed, 2016-07-13 at 23:51 +0300, Grazvydas Ignotas wrote: > On Wed, Jul 13, 2016 at 2:56 AM, Timothy Arceri > wrote: > > On Sat, 2016-07-09 at 20:21 +0300, Grazvydas Ignotas wrote: > > > > > > I think I still have some more: > > > - running 32bit program after 64bit version of the same thing (o

[Mesa-dev] [PATCH 2/3] i915/sync: Implement DRI2_Fence extension

Here is the porting of corresponding patch for i965, i.e. commit c636284 i965/sync: Implement DRI2_Fence extension Here follows part of original commit message by Chad Versace: "This enables EGL_KHR_fence_sync and EGL_KHR_wait_sync." Cc: "12.0" --- src/mesa/drivers/dri/i915/intel_screen.c |

[Mesa-dev] [PATCH 3/3] i915: store reference to the context within struct intel_fence

Porting of the corresponding experimental patch for i965, i.e. commit 67adb45 in external/mesa project branch x86/marshmallow-x86 in Android-x86 repo. Here follows the original commit message by Emil Velikov: "As the spec allows for {server,client}_wait_sync to be called without currently bound c

[Mesa-dev] [PATCH 1/3] i915/sync: Replace prefix 'intel_sync' -> 'intel_gl_sync'

This is the porting of corresponding patch for i965, i.e. commit 2516d83 i965/sync: Replace prefix 'intel_sync' -> 'intel_gl_sync' The only difference compared to i965 one is that intel_check_sync() was renamed to intel_gl_check_sync() here, as it is more appropriate. Here follows original commit

[Mesa-dev] i915: Enable EGL_KHR_{fence,wait}_sync

Sending patches to implement DRI2_Fence extension for i915, to enable EGL_KHR_fence_sync and EGL_KHR_wait_sync. It is the step-by-step porting to i915 of i965/sync, plus patch to support {server,client}_wait_sync without bound context. [PATCH 1/3] i915/sync: Replace prefix 'intel_sync' -> 'intel_

Re: [Mesa-dev] [PATCH] egl/dri2: dri2_make_current: Set EGL error if bindContext fails

Hi, On Wed, Jul 13, 2016 at 11:21 PM, Emil Velikov wrote: > On 7 June 2016 at 11:14, Nicolas Boichat wrote: >> Without this, if a configuration is, say, available only on GLES2/3, but >> not on GLES1, eglMakeCurrent fails with error "EGL_SUCCESS". >> >> In this patch, we set error to EGL_BAD_MAT

Re: [Mesa-dev] [PATCH] gallium/dri: Add shared glapi to LIBADD on Android

Hi Emil, On Thu, Jul 14, 2016 at 1:28 AM, Emil Velikov wrote: > On 13 July 2016 at 04:29, Nicolas Boichat wrote: >> From: Tomasz Figa >> >> An earlier patch fixed the problem for classic drivers, however Gallium >> was still left broken. This patch applies the same workaround to >> Gallium, whe

Re: [Mesa-dev] [PATCH 08/12] st/va: add functions for VAAPI encode

As discussed, we will improve this in a separate patch later. Regards, Boyuan From: Christian König Sent: July 1, 2016 9:03:13 AM To: Zhang, Boyuan; mesa-dev@lists.freedesktop.org Subject: Re: [PATCH 08/12] st/va: add functions for VAAPI encode Am 30.06.2016 u

Re: [Mesa-dev] [PATCH 06/12] st/va: colorspace conversion when image is yv12 and surface is nv12

Hi Christian, Style issue is fixed. Also, I checked the utility function, it seems that the existing yv12 to nv12 function can't be used for "copying from image to surface" case, so I added a new function in the utility function to do this job. Please see the new submitted patch set. For I

Re: [Mesa-dev] [PATCH] i965: fix compiler warnings for 32bit build

Reviewed-by: Matt Turner ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH] i965: fix compiler warnings for 32bit build

--- src/mesa/drivers/dri/i965/brw_state_upload.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c index 98c62d5..3eb9259 100644 --- a/src/mesa/drivers/dri/i965/brw_state_upload.c +++ b/s

Re: [Mesa-dev] [PATCH 3/3] i965/fs: emit DIM instruction to load 64-bit immediates in HSW

On Wed, Jul 13, 2016 at 5:06 PM, Matt Turner wrote: > On Tue, Jul 12, 2016 at 11:42 PM, Samuel Iglesias Gonsálvez > wrote: >> Signed-off-by: Samuel Iglesias Gonsálvez >> --- >> src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 12 >> 1 file changed, 12 insertions(+) >> >> diff --git a/src

Re: [Mesa-dev] [PATCH 01/12] vl: add parameters for VAAPI encode

Hi Emil, Thanks for the suggestion. I added brief message to each of the patch to explain what the patch does. Please see the new patch set I just submitted. Hi Christian, The un-used ref_pic related definitions are removed from this patch. For the concern of is_idr flag , I checked the b

Re: [Mesa-dev] [PATCH] i965/disasm: fix compiler warnings for 32bit build

Thanks Tim. Reviewed-by: Matt Turner ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 2/2] anv/device: Fix max buffer range limits

Thanks for fixing this! Both are Reviewed-by: Jason Ekstrand Cc: "12.0" On Wed, Jul 13, 2016 at 5:32 PM, Nanley Chery wrote: > Set limits that are consistent with ISL's assertions in > isl_genX(buffer_fill_state_s)() and Anvil's format-DescriptorType > mapping in anv_isl_format_for_descripto

[Mesa-dev] [PATCH 1/2] isl: Fix assert on raw buffer surface state size

See inline PRM reference. Signed-off-by: Nanley Chery --- src/intel/isl/isl_surface_state.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c index fc7e1ba..58e9af5 100644 --- a/src/intel/isl/isl_sur

[Mesa-dev] [PATCH 2/2] anv/device: Fix max buffer range limits

Set limits that are consistent with ISL's assertions in isl_genX(buffer_fill_state_s)() and Anvil's format-DescriptorType mapping in anv_isl_format_for_descriptor_type(). Fixes the following new crucible tests: * stress.limits.buffer-update.range.uniform * stress.limits.buffer-update.range.storage

[Mesa-dev] [PATCH] i965/disasm: fix compiler warnings for 32bit build

--- src/mesa/drivers/dri/i965/brw_disasm.c | 50 +- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c b/src/mesa/drivers/dri/i965/brw_disasm.c index 068c120..d74d5d5 100644 --- a/src/mesa/drivers/dri/i965/brw_dis

[Mesa-dev] [PATCH v4 21/34] i965/state: Use ISL for emitting image surfaces

--- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 32 1 file changed, 21 insertions(+), 11 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 65a1f3c..5873ea5 100644 --- a/src/mesa/driv

[Mesa-dev] [PATCH v4 31/34] i965/state: Account for the element size in emit_buffer_surface_state

Reviewed-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 11 ++- src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 9 + src/mesa/drivers/dri/i965/gen8_surface_state.c| 9 + 3 files changed, 16 insertions(+), 13 deletions(-) diff --git

[Mesa-dev] [PATCH v4 28/34] i965/gen6: Use the generic ISL-based path for renderbuffer surfaces

Reviewed-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/gen6_surface_state.c | 100 + 1 file changed, 1 insertion(+), 99 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen6_surface_state.c b/src/mesa/drivers/dri/i965/gen6_surface_state.c index d892c93..84b8ef4 1

[Mesa-dev] [PATCH v4 34/34] i965/context: Remove some unnecessary vfuncs

Reviewed-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.h | 17 - src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 3 +-- src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 1 - src/mesa/drivers/dri/i965/gen8_surface_state.c| 1 - 4 files chang

[Mesa-dev] [PATCH v4 27/34] i965/gen7: Use the generic ISL-based path for renderbuffer surfaces

Reviewed-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_state.h | 7 - src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 194 +- 2 files changed, 1 insertion(+), 200 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dr

[Mesa-dev] [PATCH v4 18/34] i965/blorp: Use the generic ISL path for texture surfaces on gen6

Reviewed-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/gen6_blorp.c | 76 +- 1 file changed, 2 insertions(+), 74 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.c b/src/mesa/drivers/dri/i965/gen6_blorp.c index 1af898d..70dc9f6 100644 --- a/src

[Mesa-dev] [PATCH v4 25/34] i965/gen8: Use the generic ISL-based path for renderbuffer surfaces

Reviewed-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_state.h | 16 -- src/mesa/drivers/dri/i965/gen8_surface_state.c | 249 + 2 files changed, 2 insertions(+), 263 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri

[Mesa-dev] [PATCH v4 23/34] i965/state: Add generic surface update functions based on ISL

Reviewed-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_state.h| 9 ++ src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 184 +++ 2 files changed, 193 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_stat

[Mesa-dev] [PATCH v4 32/34] i965: Use ISL for emitting buffer surface states

Reviewed-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_binding_tables.c| 2 +- src/mesa/drivers/dri/i965/brw_context.h | 8 -- src/mesa/drivers/dri/i965/brw_state.h | 9 +++ src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 93 +++ src/m

[Mesa-dev] [PATCH v4 30/34] isl/formats: Mark RAW as having a block size of 1 byte

--- src/intel/isl/isl_format_layout.csv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/isl/isl_format_layout.csv b/src/intel/isl/isl_format_layout.csv index f0f31c7..c1c98e8 100644 --- a/src/intel/isl/isl_format_layout.csv +++ b/src/intel/isl/isl_format_layout.csv @

[Mesa-dev] [PATCH v4 33/34] i965: Get rid of gen6_surface_state.c

The only useful thing left was gen6_init_vtable_surface_functions which we can easily put in brw_wm_surface_state.c. Reviewed-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/Makefile.sources | 1 - src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 7 src/mesa/drivers/dri/i965/ge

[Mesa-dev] [PATCH v4 19/34] i965/state: Add a helper for emitting a surface state using isl

Reviewed-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_state.h| 8 +++ src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 79 2 files changed, 87 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state

[Mesa-dev] [PATCH v4 24/34] i965/gen8: Use the generic ISL-based path for texture surfaces

Reviewed-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/gen8_surface_state.c | 214 + 1 file changed, 1 insertion(+), 213 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c index bd9e2a1..ed26271

[Mesa-dev] [PATCH v4 26/34] i965/gen7: Use the generic ISL-based path for texture surfaces

Reviewed-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 168 +- 1 file changed, 1 insertion(+), 167 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c index 932e62e..bd

[Mesa-dev] [PATCH v4 29/34] i965/gen4-6: Use the generic ISL-based path for texture surfaces

Reviewed-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 94 +--- 1 file changed, 1 insertion(+), 93 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 084bd8c..01c98

[Mesa-dev] [PATCH v4 10/34] i965/miptree: Add a helper for getting an isl_surf from a miptree

Reviewed-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 175 +- src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 6 + 2 files changed, 179 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drive

[Mesa-dev] [PATCH v4 20/34] i965/blorp: Use a generic ISL path for texture surfaces on gen8

Reviewed-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/gen8_blorp.c | 47 +++--- 1 file changed, 38 insertions(+), 9 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen8_blorp.c b/src/mesa/drivers/dri/i965/gen8_blorp.c index 498c9f6..870b67f 100644 --- a/src

[Mesa-dev] [PATCH v4 13/34] i965/blorp: Add a generic ISL-based surface state emit path

Reviewed-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.c | 157 ++ src/mesa/drivers/dri/i965/brw_blorp.h | 6 ++ 2 files changed, 163 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c index 0

[Mesa-dev] [PATCH v4 17/34] i965/blorp: Use the generic ISL path for renderbuffer surfaces on gen6

Reviewed-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/gen6_blorp.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.c b/src/mesa/drivers/dri/i965/gen6_blorp.c index c38952e..1af898d 100644 --- a/src/mesa/drivers/dri/i965/gen6_bl

[Mesa-dev] [PATCH v4 12/34] i965/miptree: Add a helper for getting the aux isl_surf from a miptree

Reviewed-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 120 ++ src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 5 ++ 2 files changed, 125 insertions(+) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/int

[Mesa-dev] [PATCH v4 09/34] i965: Add an isl_device to the brw_context

--- src/mesa/drivers/dri/i965/brw_context.c | 2 ++ src/mesa/drivers/dri/i965/brw_context.h | 4 2 files changed, 6 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index 3f0c2e3..cb74200 100644 --- a/src/mesa/drivers/dri/i965/brw_

[Mesa-dev] [PATCH v4 03/34] genxml: Add enough XML for gens 4, 4.5, and 5 to get SURFACE_STATE

Acked-by: Chad Versace --- src/intel/genxml/Android.mk | 15 +++ src/intel/genxml/Makefile.am | 3 +++ src/intel/genxml/Makefile.sources | 3 +++ src/intel/genxml/gen4.xml | 52 src/intel/genxml/gen45.xml| 56 ++

[Mesa-dev] [PATCH v4 16/34] i965/blorp: Use the generic ISL path for texture surfaces on gen7

Reviewed-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/gen7_blorp.c | 96 ++ 1 file changed, 3 insertions(+), 93 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.c b/src/mesa/drivers/dri/i965/gen7_blorp.c index 600684e..07b622d 100644 --- a/src

[Mesa-dev] [PATCH v4 15/34] i965/blorp: Use the generic ISL path for renderbuffer surfaces on gen7

Reviewed-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/gen7_blorp.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.c b/src/mesa/drivers/dri/i965/gen7_blorp.c index 72ab082..600684e 100644 --- a/src/mesa/drivers/dri/i965/gen7_

[Mesa-dev] [PATCH v4 14/34] i965/blorp: Use the generic ISL path for renderbuffer surfaces on gen8-9

Reviewed-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/gen8_blorp.c | 99 ++ 1 file changed, 4 insertions(+), 95 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen8_blorp.c b/src/mesa/drivers/dri/i965/gen8_blorp.c index f68aba5..498c9f6 100644 --- a/src

[Mesa-dev] [PATCH v4 11/34] i965/miptree: Add a helper for getting the ISL clear color from a miptree

Reviewed-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 24 src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 4 2 files changed, 28 insertions(+) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_

[Mesa-dev] [PATCH v4 22/34] i965/surface_state: Rename brw_update to gen4_update

We're about to add generic versions which work across gens and those should have the brw name. Reviewed-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 22 +++--- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH v4 02/34] isl/state: Divide the aux qpitch by 2

The field is in multiples of 4 like regular QPitch. --- src/intel/isl/isl_surface_state.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c index fc7e1ba..ed964bd 100644 --- a/src/intel/isl/isl_surface_state.c

[Mesa-dev] [PATCH v4 07/34] isl: Add support for filling out surface states all the way back to gen4

Reviewed-by: Chad Versace --- src/intel/isl/Android.mk | 60 +++ src/intel/isl/Makefile.am | 12 src/intel/isl/Makefile.sources| 13 +++-- src/intel/isl/isl.c | 22 ++ src/intel/isl/isl_priv.h

[Mesa-dev] [PATCH v4 06/34] isl: Add an ISL_DEV_IS_G4X macro

Reviewed-by: Chad Versace --- src/intel/isl/isl.h | 4 1 file changed, 4 insertions(+) diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h index b5884be..3064bd8 100644 --- a/src/intel/isl/isl.h +++ b/src/intel/isl/isl.h @@ -65,6 +65,10 @@ struct brw_image_param; (assert(ISL_DEV_GEN(

[Mesa-dev] [PATCH v4 04/34] genxml: Make X/Y Offset field of SURFACE_STATE a uint

THe offset type has special implications that it's intended to be some form of aligned memory address. These assumptions allow it to handle the case where there is some alignment requirement on the offset and the bottom bits are used for other things. However, the offsets in the surface state fie

[Mesa-dev] [PATCH v4 05/34] genxml: Add macros and #includes for gens 4-6

Reviewed-by: Chad Versace --- src/intel/genxml/genX_pack.h | 10 +- src/intel/genxml/gen_macros.h | 15 ++- 2 files changed, 23 insertions(+), 2 deletions(-) diff --git a/src/intel/genxml/genX_pack.h b/src/intel/genxml/genX_pack.h index 7967c29..0c25c4e 100644 --- a/src/inte

[Mesa-dev] [PATCH v4 08/34] isl/state: Add support for OffsetX/Y in surface state

Reviewed-by: Chad Versace --- src/intel/isl/isl.h | 3 +++ src/intel/isl/isl_surface_state.c | 28 2 files changed, 31 insertions(+) diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h index 3064bd8..4a9d90e 100644 --- a/src/intel/isl/isl.h +++ b/sr

[Mesa-dev] [PATCH v4 00/34] i965: Use ISL for emitting surface state

This is a resend of the latest version of this patch series mostly for Chad's benifit. Hopefully we can finally get this reviewed and landed yet this week. The first two patches are because some untested bits of the isl patches I pushed today didn't work as intended. They're pretty trivial but n

[Mesa-dev] [PATCH v4 01/34] isl: Fix the bs assertion in isl_tiling_get_info

--- src/intel/isl/isl.c | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c index 48ff8ce..363c5d5 100644 --- a/src/intel/isl/isl.c +++ b/src/intel/isl/isl.c @@ -113,21 +113,23 @@ isl_tiling_get_info(const struct isl_device *dev,

Re: [Mesa-dev] [PATCH 3/3] i965/fs: emit DIM instruction to load 64-bit immediates in HSW

On Tue, Jul 12, 2016 at 11:42 PM, Samuel Iglesias Gonsálvez wrote: > Signed-off-by: Samuel Iglesias Gonsálvez > --- > src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 12 > 1 file changed, 12 insertions(+) > > diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp > b/src/mesa/drivers/dri

Re: [Mesa-dev] [PATCH 2/3] i965/eu: set DF imm value to the source of DIM

On Tue, Jul 12, 2016 at 11:42 PM, Samuel Iglesias Gonsálvez wrote: > According to HSW's PRM, vol02b, the DIM instruction has the following > restriction: > > "Restriction : src0 must be immediate. src0 must specify the :f (F, Float) > type encoding but is an immediate 64-bit DF (Double Float) valu

Re: [Mesa-dev] [PATCH 1/3] i965: enable the emission of the DIM instruction

On Tue, Jul 12, 2016 at 11:42 PM, Samuel Iglesias Gonsálvez wrote: > Signed-off-by: Samuel Iglesias Gonsálvez > --- > src/mesa/drivers/dri/i965/brw_defines.h | 2 +- > src/mesa/drivers/dri/i965/brw_eu.c | 2 +- > src/mesa/drivers/dri/i965/brw_eu.h | 1 + > sr

[Mesa-dev] [Bug 96835] "gallium: Force blend color to 16-byte alignment" crash with "-march=native -O3" causes some 32bit games to crash

https://bugs.freedesktop.org/show_bug.cgi?id=96835 --- Comment #11 from i...@yahoo.com --- I would actually recommend solving the problem in its root. Disable auto vectorization. FFmpeg recently tried removing "-fno-tree-vectorize" for gcc >=4.9 . After a few weeks they reverted the change. It c

Re: [Mesa-dev] [PATCH 1/3 v3] anv/descriptor_set: Fix binding partly undefined descriptor sets

LGTM On Wed, Jul 13, 2016 at 4:36 PM, Nanley Chery wrote: > Section 13.2.3. of the Vulkan spec requires that implementations be able to > bind sparsely-defined Descriptor Sets without any errors or exceptions. > > When binding a descriptor set that contains a dynamic buffer > binding/descriptor,

[Mesa-dev] [PATCH] isl/state: Divide the aux qpitch by 2

The field is in multiples of 4 like regular QPitch. --- src/intel/isl/isl_surface_state.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c index d40f2c1..1c656c9 100644 --- a/src/intel/isl/isl_surface_state.c

[Mesa-dev] [PATCH 1/3 v3] anv/descriptor_set: Fix binding partly undefined descriptor sets

Section 13.2.3. of the Vulkan spec requires that implementations be able to bind sparsely-defined Descriptor Sets without any errors or exceptions. When binding a descriptor set that contains a dynamic buffer binding/descriptor, the driver attempts to dereference the descriptor's buffer_view field

[Mesa-dev] [PATCH 1/3 v2] anv/descriptor_set: Fix binding partly undefined descriptor sets

Section 13.2.3. of the Vulkan spec requires that implementations be able to bind sparsely-defined Descriptor Sets without any errors or exceptions. When binding a descriptor set that contains a dynamic buffer binding/descriptor, the driver attempts to dereference the descriptor's buffer_view field

[Mesa-dev] [PATCH] isl: Fix the bs assertion in isl_tiling_get_info

--- src/intel/isl/isl.c | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c index 2003e2a..9e01b8d 100644 --- a/src/intel/isl/isl.c +++ b/src/intel/isl/isl.c @@ -113,21 +113,23 @@ isl_tiling_get_info(const struct isl_device *dev,

[Mesa-dev] [PATCH 03/11] radeon/omx: assign previous values to new structure

Assign previously hardcoded values for OMX to newly defined structure. As a result, OMX behaviour will not change at all. Signed-off-by: Boyuan Zhang --- src/gallium/state_trackers/omx/vid_enc.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/src/gallium/state_trackers/omx/vid_e

[Mesa-dev] [PATCH 07/11] st/va: add conversion for yv12 to nv12in putimage

For putimage call, if image format is yv12 (or IYUV with U V field swap) and surface format is nv12, then we need to convert yv12 to nv12 and then copy the converted data from image to surface. We can't use the existing logic where surface is destroyed and re-created with yv12 format. Signed-of

Re: [Mesa-dev] [PATCH 1/3] anv/descriptor_set: Fix binding partly undefined descriptor sets

On Wed, Jul 13, 2016 at 03:56:42PM -0700, Jason Ekstrand wrote: > On Wed, Jul 13, 2016 at 3:34 PM, Nanley Chery wrote: > > > Section 13.2.3. of the Vulkan spec requires that implementations be able to > > bind sparsely-defined Descriptor Sets without any errors or exceptions. > > > > When binding

Re: [Mesa-dev] [PATCH 1/3] anv/descriptor_set: Fix binding partly undefined descriptor sets

On Wed, Jul 13, 2016 at 3:34 PM, Nanley Chery wrote: > Section 13.2.3. of the Vulkan spec requires that implementations be able to > bind sparsely-defined Descriptor Sets without any errors or exceptions. > > When binding a descriptor set that contains a dynamic buffer > binding/descriptor, > the

[Mesa-dev] [PATCH 02/11] vl: add entry point

Add entry point for encoding which previously hardcoded for decoding purpose only Signed-off-by: Boyuan Zhang --- src/gallium/include/pipe/p_video_state.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/gallium/include/pipe/p_video_state.h b/src/gallium/include/pipe/p_video_state.h ind

[Mesa-dev] [PATCH 04/11] radeon/vce: handle newly added parameters

Replace the previous hardcoded value with newly defined parameters Signed-off-by: Boyuan Zhang --- src/gallium/drivers/radeon/radeon_vce_52.c | 33 ++ 1 file changed, 20 insertions(+), 13 deletions(-) diff --git a/src/gallium/drivers/radeon/radeon_vce_52.c b/src/gal

[Mesa-dev] [PATCH 01/11] vl: add parameters for VAAPI encode

Allow to specify more parameters in the encoding interface which previously just hardcoded in the encoder Signed-off-by: Boyuan Zhang --- src/gallium/include/pipe/p_video_state.h | 33 1 file changed, 33 insertions(+) diff --git a/src/gallium/include/pipe/p_vid

[Mesa-dev] [PATCH 06/11] st/va: add copy function for yv12 image to nv12 surface

Add function to copy from yv12 image to nv12 surface for VAAPI putimage call. Existing function only work for copying from yv12 surface to nv12 image. Signed-off-by: Boyuan Zhang --- src/gallium/auxiliary/util/u_video.h | 22 ++ 1 file changed, 22 insertions(+) diff --git a

[Mesa-dev] [PATCH 05/11] st/va: add encode entrypoint

VAAPI passes PIPE_VIDEO_ENTRYPOINT_ENCODE as entry point for encoding case. We will save this encode entry point instead of always hardcoded to PIPE_VIDEO_ENTRYPOINT_BITSTREAM for decoding case previously. Signed-off-by: Boyuan Zhang --- src/gallium/state_trackers/va/config.c | 61

[Mesa-dev] [PATCH 10/11] st/va: add preset values for VAAPI encode

Add some hardcoded values hardware needs mainly for rate control purpose. Signed-off-by: Boyuan Zhang --- src/gallium/state_trackers/va/picture.c | 36 + 1 file changed, 36 insertions(+) diff --git a/src/gallium/state_trackers/va/picture.c b/src/gallium/state_tr

[Mesa-dev] [PATCH 08/11] st/va: get rate control method from configattrib

Rate control method is passed from app to driver through config attrib list. Signed-off-by: Boyuan Zhang --- src/gallium/state_trackers/va/config.c | 11 +++ src/gallium/state_trackers/va/context.c| 3 ++- src/gallium/state_trackers/va/va_private.h | 1 + 3 files changed, 14 in

[Mesa-dev] [PATCH 11/11] st/va: enable h264 VAAPI encode

Enable H.264 VAAPI encoding through config. Signed-off-by: Boyuan Zhang --- src/gallium/state_trackers/va/config.c | 32 ++-- 1 file changed, 22 insertions(+), 10 deletions(-) diff --git a/src/gallium/state_trackers/va/config.c b/src/gallium/state_trackers/va/config

[Mesa-dev] [PATCH 09/11] st/va: add functions for VAAPI encode

Add necessary functions/changes for VAAPI encoding to buffer and picture, without affecting decode behaviour. Signed-off-by: Boyuan Zhang --- src/gallium/state_trackers/va/buffer.c | 6 ++ src/gallium/state_trackers/va/picture.c| 161 - src/gallium/state_tr

[Mesa-dev] [PATCH 3/3] anv/cmd_buffer: Simplify range member assignment

A ternary is clearer because the range member is assigned one of two values dependant on one condition. Signed-off-by: Nanley Chery --- src/intel/vulkan/anv_cmd_buffer.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/src/intel/vulkan/anv_cmd_buffer.c b/src/intel/vulka

[Mesa-dev] [PATCH 0/3] Fix binding sparsely-defined descriptor sets and misc cleanups

The first patch of this series fixes a bug in the driver. The remaining two make the related code easier to understand. Nanley Chery (3): anv/descriptor_set: Fix binding partly undefined descriptor sets anv/cmd_buffer: Remove unused variable anv/cmd_buffer: Simplify range member assignment

[Mesa-dev] [PATCH 1/3] anv/descriptor_set: Fix binding partly undefined descriptor sets

Section 13.2.3. of the Vulkan spec requires that implementations be able to bind sparsely-defined Descriptor Sets without any errors or exceptions. When binding a descriptor set that contains a dynamic buffer binding/descriptor, the driver attempts to dereference the descriptor's buffer_view field

[Mesa-dev] [PATCH 2/3] anv/cmd_buffer: Remove unused variable

This became unused due to commit 612e35b2c65c99773b73e53d0e6fd112b1a7431f . Signed-off-by: Nanley Chery --- src/intel/vulkan/anv_cmd_buffer.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/intel/vulkan/anv_cmd_buffer.c b/src/intel/vulkan/anv_cmd_buffer.c index 20d3af1

Re: [Mesa-dev] [PATCH] st/mesa: fix reference counting bug in st_vdpau

I have tested the leak is fixed by this patch. And have a look again, the leak actually happens in the case of st_vdpau_output_surface_dma_buf. Sorry for the noise. The patch is Tested-and-Reviewed by: Leo Liu Regards, Leo On 07/13/2016 10:08 AM, Leo Liu wrote: On 07/13/2016 08:56 AM, C

[Mesa-dev] [PATCH 1/3] st/mesa: check for immutable texture in st_TestProxyTexImage()

If it's immutable, we don't have to guess about the number of mipmap levels. --- src/mesa/state_tracker/st_cb_texture.c | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/src/mesa/state_tracker/st_cb_texture.c b/src/mesa/state_tracker/st_cb_texture.c index 1474d97..b91a2

[Mesa-dev] [PATCH 2/3] mesa: use _mesa_clear_texture_image() in clear_texture_fields()

This avoids a failed assert(img->_BaseFormat != -1) in init_teximage_fields_ms() because the internalFormat argument is GL_NONE. This was hit when using glTexStorage() to do a proxy texture test. Fixes a failure with the updated Piglit tex3d-maxsize test. Cc: --- src/mesa/main/texstorage.c | 4

[Mesa-dev] [PATCH 3/3] mesa: fix issues with glTexStorage() and proxy textures

When we call ctx->Driver.TestProxyTexImage() we want to have the texture object's Immutable and NumLevels fields initialized so that the function doesn't have to guess about the number of mipmap levels. But since the proxy textures are shared by the old glTexImage() and new glTexStorage(), we can'

[Mesa-dev] [PATCH 2/2] glsl/types: Use _mesa_hash_data for hashing function types

This is way better than the stupid string approach especially since you could overflow the string. Again, I thought I had something better at one point but it obviously got lost. Signed-off-by: Jason Ekstrand Cc: "12.0" --- src/compiler/glsl_types.cpp | 16 ++-- 1 file changed, 2 i

[Mesa-dev] [PATCH 1/2] glsl/types: Fix function type comparison function

It was returning true if the function types have different lengths rather than false. This was new with the SPIR-V to NIR pass and I thought I'd fixed it a while ago but it may have gotten lost in rebasing somewhere. Signed-off-by: Jason Ekstrand Cc: "12.0" --- src/compiler/glsl_types.cpp | 2

Re: [Mesa-dev] [PATCH 2/5] radeonsi: set dereferenceable attribute on descriptor arrays

> On Jul 13, 2016, at 12:36, Marek Olšák wrote: > > On Wed, Jul 13, 2016 at 9:25 PM, Tom Stellard > wrote: >> On Wed, Jul 13, 2016 at 03:20:55PM -0400, Tom Stellard wrote: >>> On Tue, Jul 12, 2016 at 10:52:35PM +0200, Marek Olšák wrote: From: Marek Olšák >>

Re: [Mesa-dev] V3 On disk shader cache for i965 (Now with real world results!)

On Wed, Jul 13, 2016 at 2:56 AM, Timothy Arceri wrote: > On Sat, 2016-07-09 at 20:21 +0300, Grazvydas Ignotas wrote: >> >> I think I still have some more: >> - running 32bit program after 64bit version of the same thing (or >> vice >> versa) leads to segfaults and assert hits. Probably easiest to

Re: [Mesa-dev] [PATCH] gallium/u_queue: add optional cleanup callback

On Wed, Jul 13, 2016 at 6:28 PM, Rob Clark wrote: > Adds a second optional cleanup callback, called after the fence is > signaled. This is needed if, for example, the queue has the last > reference to the object that embeds the util_queue_fence. In this > case we cannot drop the ref in the main

Re: [Mesa-dev] [PATCH] main: memcpy larger chunks in _mesa_propagate_uniforms_to_driver_storage

On Wednesday, July 13, 2016 1:53:26 PM PDT Nils Wallménius wrote: > When possible, do the memcpy on larger blocks. This reduces cycles > spent in _mesa_propagate_uniforms_to_driver_storage from > 1.51 % to 0.62% according to perf during the Unigine Heaven benchmark. > It did not affect the framerat

Re: [Mesa-dev] [PATCH] glsl: look for frag data bindings with [0] tacked onto the end for arrays

Thanks for confirming, Corentin. Ian, do you have any opinions on this? Seems like a fairly innocuous thing to be doing... On Fri, Jul 8, 2016 at 3:39 PM, Corentin Wallez wrote: > Not sure how reviews work in Mesa, but this patch LGTM. I also tested that > it fixes the relevant tests failures it

Re: [Mesa-dev] [PATCH 2/5] radeonsi: set dereferenceable attribute on descriptor arrays

On Wed, Jul 13, 2016 at 9:25 PM, Tom Stellard wrote: > On Wed, Jul 13, 2016 at 03:20:55PM -0400, Tom Stellard wrote: >> On Tue, Jul 12, 2016 at 10:52:35PM +0200, Marek Olšák wrote: >> > From: Marek Olšák >> > >> > This allows moving the loads arbitrarily in the Sinking pass. >> > >> > 26002 shade

Re: [Mesa-dev] [PATCH 2/5] radeonsi: set dereferenceable attribute on descriptor arrays

On Wed, Jul 13, 2016 at 03:20:55PM -0400, Tom Stellard wrote: > On Tue, Jul 12, 2016 at 10:52:35PM +0200, Marek Olšák wrote: > > From: Marek Olšák > > > > This allows moving the loads arbitrarily in the Sinking pass. > > > > 26002 shaders in 14643 tests > > Totals: > > SGPRS: 2080160 -> 2080160

Re: [Mesa-dev] [PATCH 3/5] radeonsi: replace !tbaa with !invariant.load

On Tue, Jul 12, 2016 at 10:52:36PM +0200, Marek Olšák wrote: > From: Marek Olšák > Reviewed-by: Tom Stellard > no change in generated code thanks to dereferenceable(n) > --- > src/gallium/drivers/radeonsi/si_shader.c | 17 + > 1 file changed, 5 insertions(+), 12 deletions(-) >

Re: [Mesa-dev] [PATCH 2/5] radeonsi: set dereferenceable attribute on descriptor arrays

On Tue, Jul 12, 2016 at 10:52:35PM +0200, Marek Olšák wrote: > From: Marek Olšák > > This allows moving the loads arbitrarily in the Sinking pass. > > 26002 shaders in 14643 tests > Totals: > SGPRS: 2080160 -> 2080160 (0.00 %) > VGPRS: 798875 -> 797826 (-0.13 %) > Spilled SGPRs: 108485 -> 79165

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