On Thu, 2016-06-30 at 08:15 +0200, Iago Toral wrote:
> On Wed, 2016-06-29 at 23:12 +1000, Timothy Arceri wrote:
> > On Wed, 2016-06-29 at 14:42 +0200, Iago Toral wrote:
> > > On Wed, 2016-06-29 at 14:40 +0200, Iago Toral wrote:
> > > > On Tue, 2016-06-28 at 16:30 +0200, Iago Toral wrote:
> > > > >
Reviewed-by: Iago Toral Quiroga
On Thu, 2016-06-30 at 14:49 +1000, Timothy Arceri wrote:
> ---
>
> This applys on top of https://patchwork.freedesktop.org/series/9217/
> with hasn't landed just yet.
>
> src/compiler/glsl/glsl_parser_extras.cpp | 57 +++
> src/compiler/glsl/glsl_to_nir
Are you using VA-API on X11? libva gets the driver name from Xserver,
it is nouveau for you. so libva tries to load nouveau_drv_video.so.
You can create a symlink for nouveau pointing to a available driver or
just ignore the message because you have gallium_drv_video.so now.
Thanks
Haihao
>
On Wed, 2016-06-29 at 23:12 +1000, Timothy Arceri wrote:
> On Wed, 2016-06-29 at 14:42 +0200, Iago Toral wrote:
> > On Wed, 2016-06-29 at 14:40 +0200, Iago Toral wrote:
> > > On Tue, 2016-06-28 at 16:30 +0200, Iago Toral wrote:
> > > > On Tue, 2016-06-28 at 11:52 +1000, Timothy Arceri wrote:
> > >
On Wed, Jun 29, 2016 at 05:37:28PM -0700, Jason Ekstrand wrote:
> ---
> src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 10 +-
> 1 file changed, 5 insertions(+), 5 deletions(-)
Could you add some rational here? In the next patch you still use
MAX2(mt->num_samples, 1) and it looks that it a
On Wed, Jun 29, 2016 at 10:57:43PM -0700, Jason Ekstrand wrote:
>On Jun 29, 2016 10:28 PM, "Pohjolainen, Topi"
><[1]topi.pohjolai...@intel.com> wrote:
>>
>> On Wed, Jun 29, 2016 at 05:37:23PM -0700, Jason Ekstrand wrote:
>> > ---
>> > src/mesa/drivers/dri/i965/brw_blorp.c
On Wed, Jun 29, 2016 at 05:37:27PM -0700, Jason Ekstrand wrote:
> Now that we're carrying around the isl_surf, we can just modify it
> directly instead of passing an extra bit around.
> ---
> src/mesa/drivers/dri/i965/brw_blorp.c| 14 ++
> src/mesa/drivers/dri/i965/brw_blorp.h
On Jun 29, 2016 10:28 PM, "Pohjolainen, Topi"
wrote:
>
> On Wed, Jun 29, 2016 at 05:37:23PM -0700, Jason Ekstrand wrote:
> > ---
> > src/mesa/drivers/dri/i965/brw_blorp.c| 6 +-
> > src/mesa/drivers/dri/i965/brw_context.c | 2 ++
> > src/mesa/drivers/dri/i965/brw_contex
On Wed, Jun 29, 2016 at 05:37:25PM -0700, Jason Ekstrand wrote:
> ---
> src/mesa/drivers/dri/i965/brw_blorp.c | 25 ++---
> src/mesa/drivers/dri/i965/brw_blorp.h | 5 +
> 2 files changed, 19 insertions(+), 11 deletions(-)
Patches five and six are:
Reviewed-by: Topi Pohjo
On Wed, Jun 29, 2016 at 05:37:21PM -0700, Jason Ekstrand wrote:
> It's only used to stomp the tiling to Y and it's only used by blorp so
> there's no reason why blorp can't do it itself.
Reviewed-by: Topi Pohjolainen
> ---
> src/mesa/drivers/dri/i965/brw_blorp.c | 6 --
> src/mesa/d
On Wed, Jun 29, 2016 at 05:37:23PM -0700, Jason Ekstrand wrote:
> ---
> src/mesa/drivers/dri/i965/brw_blorp.c| 6 +-
> src/mesa/drivers/dri/i965/brw_context.c | 2 ++
> src/mesa/drivers/dri/i965/brw_context.h | 4
> src/mesa/drivers/dri/i965/brw_wm_surface
Hi Alejandro,
Alejandro Piñeiro writes:
> Fixes:
> GL44-CTS.texture_barrier_ARB.same-texel-rw-multipass
>
> On Haswell, Broadwell and Skylake (note that in order to execute that
> test, it is needed to override GL and GLSL versions).
>
> On gen6 this test was already working without this change.
On Wed, Jun 29, 2016 at 03:11:25PM -0700, Jason Ekstrand wrote:
>On Tue, Jun 28, 2016 at 10:27 PM, Pohjolainen, Topi
><[1]topi.pohjolai...@intel.com> wrote:
>
> On Tue, Jun 28, 2016 at 09:22:49AM +0300, Pohjolainen, Topi wrote:
> > On Thu, Jun 23, 2016 at 02:00:30PM -0700, Jason
---
This applys on top of https://patchwork.freedesktop.org/series/9217/
with hasn't landed just yet.
src/compiler/glsl/glsl_parser_extras.cpp | 57 +++
src/compiler/glsl/glsl_to_nir.cpp | 10 +-
src/compiler/glsl/link_varyings.cpp| 2 +-
src/compiler/glsl/linker.cpp
Fix this build error with GCC 4.4.
CC state_tracker/st_nir_lower_builtin.lo
In file included from state_tracker/st_nir_lower_builtin.c:61:
state_tracker/st_nir.h:34: error: redefinition of typedef ‘nir_shader’
../../src/compiler/nir/nir.h:1830: note: previous declaration of ‘nir_shader’
was
On Jun 29, 2016 7:16 PM, "Vinson Lee" wrote:
>
> Fix this build error with GCC 4.4.
>
> CC state_tracker/st_nir_lower_builtin.lo
> In file included from state_tracker/st_nir_lower_builtin.c:61:
> state_tracker/st_nir.h:34: error: redefinition of typedef ‘nir_shader’
> ../../src/compiler/nir/
Fix this build error with GCC 4.4.
CC state_tracker/st_nir_lower_builtin.lo
In file included from state_tracker/st_nir_lower_builtin.c:61:
state_tracker/st_nir.h:34: error: redefinition of typedef ‘nir_shader’
../../src/compiler/nir/nir.h:1830: note: previous declaration of ‘nir_shader’
was
On 06/27/2016 08:28 AM, Andres Gomez wrote:
> The linker deals with atomic counters in terms of uniforms. This is OK
> but when we want to know the number of used atomic counters since a 2
> elements atomic counters array will use 2 counters but only 1 uniform.
>
> Renamed the data structures used
On Mon, 2016-06-27 at 18:28 +0300, Andres Gomez wrote:
> The linker deals with atomic counters in terms of uniforms. This is
> OK
> but when we want to know the number of used atomic counters since a 2
> elements atomic counters array will use 2 counters but only 1
> uniform.
You don't really ment
Previously, we tried to take advantage of the already computed physical
level0 extent in samples. However, this was wrong because you can't minify
a value that's expressed in samples; only pixels. Instead, we just pull
directly from the number of pixels provided by the user. Fortunately,
calc_ph
The helper does a full transformation on the surface to turn it into a new
2-D single-layer single-level surface representing the original layer and
level in memory.
---
src/mesa/drivers/dri/i965/brw_blorp.c | 84 ++-
1 file changed, 43 insertions(+), 41 deletions(-
---
src/intel/isl/isl_surface_state.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/src/intel/isl/isl_surface_state.c
b/src/intel/isl/isl_surface_state.c
index 1d354f3..1b269a3 100644
--- a/src/intel/isl/isl_surface_state.c
+++ b/src/intel/isl/isl_surface_state.c
@@ -423,6 +423,
Now that the generic blorp path uses base level/layer, there's no need to
make gen8 special.
---
src/mesa/drivers/dri/i965/brw_state.h| 8 -
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 2 +-
src/mesa/drivers/dri/i965/gen8_blorp.c | 46 +++-
3
AUX USAGE
---
src/mesa/drivers/dri/i965/brw_blorp.h| 2 ++
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 16 +---
2 files changed, 11 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h
b/src/mesa/drivers/dri/i965/brw_blorp.h
index a85d368..89a7
The only reason why we need layer or level is that we need the z-offset for
3-D surfaces. Let's just have the one field for that.
---
src/mesa/drivers/dri/i965/brw_blorp.c | 3 ---
src/mesa/drivers/dri/i965/brw_blorp.h | 16
2 files changed, 19 deletions(-)
diff --git a/src/mes
At the moment, the minify operation does nothing because
params.depth.view.base_level is always zero. However, as soon as we start
using actual base miplevels and array slices, we are going to need the
minification. Also, we only need to align the surface dimensions in the
case where we are opera
Since the dawn of time, blorp has used offsets directly to get at different
mip levels and array slices of surfaces. This isn't really necessary since
we can just use the base level/layer provided in the surface state. While
it may have simplified blorp's original design, we haven't been using th
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 25 -
1 file changed, 24 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 4d23b70..318dfe5 100644
--- a/src/mesa/drivers/dri/i9
---
src/intel/isl/isl_surface_state.c | 124 +++---
1 file changed, 74 insertions(+), 50 deletions(-)
diff --git a/src/intel/isl/isl_surface_state.c
b/src/intel/isl/isl_surface_state.c
index 1b269a3..0a2d877 100644
--- a/src/intel/isl/isl_surface_state.c
+++ b/src
---
src/intel/isl/isl_surface_state.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/src/intel/isl/isl_surface_state.c
b/src/intel/isl/isl_surface_state.c
index 0a2d877..e7f9101 100644
--- a/src/intel/isl/isl_surface_state.c
+++ b/src/intel/isl/isl_surface_state.c
@@ -263,6 +2
---
src/mesa/drivers/dri/i965/brw_blorp.c| 8 +++-
src/mesa/drivers/dri/i965/brw_blorp.h| 2 --
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 30 ++--
src/mesa/drivers/dri/i965/gen6_blorp.c | 10 +-
src/mesa/drivers/dri/i965/gen7_blorp.c
---
src/intel/isl/isl.h | 4
1 file changed, 4 insertions(+)
diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index 0a3af02..c360586 100644
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -79,6 +79,10 @@ struct brw_image_param;
#define ISL_DEV_IS_HASWELL(__dev) ((__dev)->info->
---
src/mesa/drivers/dri/i965/brw_blorp.c | 18 +-
1 file changed, 1 insertion(+), 17 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 188f708..cd8d066 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/d
Eventually, this will be the actual view that gets passed into isl to
create the surface state. For now, we just use it for the format and the
swizzle.
---
src/mesa/drivers/dri/i965/brw_blorp.c | 38 +++
src/mesa/drivers/dri/i965/brw_blorp.h | 16 ++
Instead, we manually mutate the surface size as needed.
---
src/mesa/drivers/dri/i965/brw_blorp.c| 21 ++---
src/mesa/drivers/dri/i965/brw_blorp.h| 12
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 19 +++
src/mesa/drivers/dri/i965/gen6
---
src/intel/isl/isl.c | 24
src/intel/isl/isl.h | 46 ++
2 files changed, 58 insertions(+), 12 deletions(-)
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 2792240..404cfc1 100644
--- a/src/intel/isl/isl.c
+++ b/s
Multisample array surfaces on IVB don't support the minimum array element
surface attribute so it needs to come through the sampler message. We may
as well just pass it through everything.
---
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 77 +---
1 file changed, 35 inser
The data comes in via ISL in a format that's almost directly usable by the
hardware so we can avoid some of the conversion headache.
---
src/mesa/drivers/dri/i965/gen6_blorp.c | 34 --
src/mesa/drivers/dri/i965/gen7_blorp.c | 38 +++---
2 fil
For the moment, we still call the old miptree function; we just assert that
the two are equal.
---
src/mesa/drivers/dri/i965/brw_blorp.c | 96 +--
1 file changed, 93 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
b/src/mesa/driver
The sampling hardware can handle them ok. It just looks at the tiling to
determine whether it's the new gen9 1-D layout or the old one. The render
hardware isn't so smart.
---
src/mesa/drivers/dri/i965/brw_blorp.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/src/mesa/drivers/dri/i96
We put all of the code for fake IMS together. This requires moving a bit
of the program key setup code further down so that it gets the right values
out of the final surface.
---
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 71 +---
1 file changed, 34 insertions(+), 37 d
It's only used to stomp the tiling to Y and it's only used by blorp so
there's no reason why blorp can't do it itself.
---
src/mesa/drivers/dri/i965/brw_blorp.c | 6 --
src/mesa/drivers/dri/i965/brw_misc_state.c| 6 +++---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 5 +
sr
The layer field is in terms of physical layers which isn't quite what the
sampler will want for 2-D MS array textures.
---
src/mesa/drivers/dri/i965/brw_blorp.c| 9 +
src/mesa/drivers/dri/i965/brw_blorp.h| 3 +++
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 10 +
---
src/mesa/drivers/dri/i965/brw_blorp.c| 6 +-
src/mesa/drivers/dri/i965/brw_context.c | 2 ++
src/mesa/drivers/dri/i965/brw_context.h | 4
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 12 ++--
4 files changed, 9 insertions(+), 15 deletions
---
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index 1e15bd5..257db06 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.
We have a handy little function is ISL that does exactly the same thing.
---
src/mesa/drivers/dri/i965/brw_blorp.c | 34 +-
src/mesa/drivers/dri/i965/brw_blorp.h | 5 -
2 files changed, 5 insertions(+), 34 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/br
It's been in elements for a while but, for whatever reason, the parameter
names in the header file never got updated.
---
src/intel/isl/isl.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index 8c1f0c3..ca07393 100644
--- a/sr
Now that we're carrying around the isl_surf, we can just modify it
directly instead of passing an extra bit around.
---
src/mesa/drivers/dri/i965/brw_blorp.c| 14 ++
src/mesa/drivers/dri/i965/brw_blorp.h| 15 ---
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 40 +++
We also remove brw_blorp_surface_info::msaa_layout.
---
src/mesa/drivers/dri/i965/brw_blorp.c| 18 -
src/mesa/drivers/dri/i965/brw_blorp.h| 14 +---
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 111 +--
3 files changed, 39 insertions(+), 104 deletion
---
src/mesa/drivers/dri/i965/brw_blorp.c| 24
src/mesa/drivers/dri/i965/brw_blorp.h| 15 ++-
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 8
3 files changed, 18 insertions(+), 29 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/
---
src/mesa/drivers/dri/i965/brw_blorp.c | 1 -
src/mesa/drivers/dri/i965/brw_blorp.h | 9 -
2 files changed, 10 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 34a16dc..d6581d0 100644
--- a/src/mesa/drivers/dri/i965/brw_blor
---
src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
index 2515a04..a4237e5 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_
The function takes a logical array layer but was assuming it was a physical
array layer. While we'er here, we also make it not assert-fail on gen9 3-D
surfaces.
---
src/intel/isl/isl.c | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/src/intel/isl/isl.c b/src/inte
This is one more series on the way to making blorp generic enough to be
shared between the two drivers.
The way blorp works right now is that it takes a pair of miptrees and
records a set of tweaks to those miptrees in a side data structure. At the
last moment, when it goes to emit RENDER_SURFACE
The alignment we use doesn't matter (see the comment) but it should at
least be an alignment we can represent with the enums.
---
src/intel/isl/isl_surface_state.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/isl/isl_surface_state.c
b/src/intel/isl/isl_surface_sta
---
src/mesa/drivers/dri/i965/brw_blorp.c | 25 ++---
src/mesa/drivers/dri/i965/brw_blorp.h | 5 +
2 files changed, 19 insertions(+), 11 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 8e36080..c934913 100644
On Wed, 2016-06-29 at 17:23 +0300, Andres Gomez wrote:
> On Thu, 2016-06-30 at 00:09 +1000, Timothy Arceri wrote:
> >
> > On 29 June 2016 11:29:17 pm AEST, Andres Gomez
> > wrote:
> > > This reverts commit 644e015f0b9236e955d679cac4bcc7a1523fc475.
> > >
> > > PrimitiveMode from the program doesn
Reviewed-by: Topi Pohjolainen
v3: Stomp more surface state fields
---
src/mesa/drivers/dri/i965/brw_blorp.c | 163 ++
src/mesa/drivers/dri/i965/brw_blorp.h | 6 ++
2 files changed, 169 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
b/src/mesa
Am 29.06.2016 um 01:52 schrieb Brian Paul:
> From: Neha Bhende
>
> We want to be able to copy between different 32-bit, 3-channel surface
> formats for GL_ARB_copy_image but since we don't have a 3-channel float
> format, we can't support 32-bit, 3-channel integer formats.
>
> The state tracker
Reviewed-by: Topi Pohjolainen
v3: Various fixes, mostly involving alignment, found when porting blorp
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 170 +-
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 6 +
2 files changed, 174 insertions(+), 2 deletions(-)
dif
Reviewed-by: Chad Versace
v3: Add units to the parameters and a pile of asserts
---
src/intel/isl/isl.h | 3 +++
src/intel/isl/isl_surface_state.c | 28
2 files changed, 31 insertions(+)
diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index 3bf
Am 29.06.2016 um 01:52 schrieb Brian Paul:
> Since only the src box can have negative dims for flipping, just
> comparing the src/dst box sizes is enough to detect flips.
> ---
> src/gallium/auxiliary/util/u_surface.c | 20
> 1 file changed, 8 insertions(+), 12 deletions(-)
>
Am 29.06.2016 um 04:32 schrieb Chuck Atkins:
> This aligns the 4-element color float array to 16 byte boundaries. This
> should allow compiler vectorizers to generate better optimizations.
> Also fixes broken vectorization generated by Intel compiler.
>
> v2: Fixed indentation and added a lengthy
>From: Brian Paul
>Sent: Tuesday, June 28, 2016 4:52 PM
>To: mesa-dev@lists.freedesktop.org
>Cc: Charmaine Lee; Neha Bhende; Jose Fonseca; Roland Scheidegger
>Subject: [PATCH 11/16] svga: use copy_region_vgpu10() for region copies when
>possible
>
>---
> src/gallium/drivers/svga/svga_pipe_blit.
On 06/19/2016 10:06 PM, Dave Airlie wrote:
> From: Dave Airlie
>
> This just adds the new operations and add 64-bit integer
> support to all the existing cases where it is needed.
>
> v2: fix some issues found in testing.
>
> Signed-off-by: Dave Airlie
> ---
> src/compiler/glsl/ir_constant_ex
Patches 1, 2, 3, 4 (with the changes you said you made), 6, 7, 8, 11,
12, and 14 through 19 are
Reviewed-by: Ian Romanick
I sent comments on 5 and 10.
9 was already R-b.
I'm still thinking about 13, but it's probably correct.
I'm a little surprised that nothing was needed for UBOs or SSBOs.
On Wed, Jun 29, 2016 at 3:12 PM, Chad Versace
wrote:
> On Thu 23 Jun 2016, Jason Ekstrand wrote:
> > ---
> > src/intel/isl/isl.h | 26 ++
> > 1 file changed, 26 insertions(+)
> >
> > diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
> > index 4aedb11..5011d15 100644
v2: Switch on the usage when filling out formats
Reviewed-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 119 ++
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 5 ++
2 files changed, 124 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/in
On Thu 23 Jun 2016, Jason Ekstrand wrote:
> ---
> src/intel/isl/isl.h | 7 +++
> src/intel/isl/isl_surface_state.c | 39
> ---
> 2 files changed, 43 insertions(+), 3 deletions(-)
>
> diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
> i
On Wed 29 Jun 2016, Jason Ekstrand wrote:
> On Wed, Jun 29, 2016 at 3:03 PM, Chad Versace
> wrote:
>
> > On Thu 23 Jun 2016, Jason Ekstrand wrote:
> > > ---
> > > src/intel/isl/isl.h | 21 +
> > > src/intel/isl/isl_format_layout.csv | 14 ++
> > >
On 06/19/2016 10:06 PM, Dave Airlie wrote:
> From: Dave Airlie
>
> This hooks up the API to the internals for 64-bit integer uniforms.
>
> Signed-off-by: Dave Airlie
> ---
> src/mesa/main/uniform_query.cpp | 60 +-
> src/mesa/main/uniforms.c| 170
> +++
On 06/20/2016 02:02 PM, Dave Airlie wrote:
> On 21 June 2016 at 04:29, Ian Romanick wrote:
>> I sent feedback for this patch the first time. :)
>>
>> https://lists.freedesktop.org/archives/mesa-dev/2016-June/119945.html
>
> This reply for some reason isn't in my inbox at all. Not sure what ate it
From: Ian Romanick
Signed-off-by: Ian Romanick
Cc: Dave Airlie
---
src/compiler/glsl_types.cpp | 7 +++
src/compiler/glsl_types.h | 3 +++
2 files changed, 10 insertions(+)
diff --git a/src/compiler/glsl_types.cpp b/src/compiler/glsl_types.cpp
index 6e107a7..1539f5a 100644
--- a/src/com
On Wed, Jun 29, 2016 at 3:03 PM, Chad Versace
wrote:
> On Thu 23 Jun 2016, Jason Ekstrand wrote:
> > ---
> > src/intel/isl/isl.h | 21 +
> > src/intel/isl/isl_format_layout.csv | 14 ++
> > 2 files changed, 35 insertions(+)
> >
> > diff --git a/src
On Thu 23 Jun 2016, Jason Ekstrand wrote:
> ---
> src/intel/isl/isl.h | 26 ++
> 1 file changed, 26 insertions(+)
>
> diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
> index 4aedb11..5011d15 100644
> --- a/src/intel/isl/isl.h
> +++ b/src/intel/isl/isl.h
> @@ -506,6
On Tue, Jun 28, 2016 at 10:27 PM, Pohjolainen, Topi <
topi.pohjolai...@intel.com> wrote:
> On Tue, Jun 28, 2016 at 09:22:49AM +0300, Pohjolainen, Topi wrote:
> > On Thu, Jun 23, 2016 at 02:00:30PM -0700, Jason Ekstrand wrote:
> > > ---
> > > src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 11
On Thu 23 Jun 2016, Jason Ekstrand wrote:
> ---
> src/intel/isl/isl.h | 21 +
> src/intel/isl/isl_format_layout.csv | 14 ++
> 2 files changed, 35 insertions(+)
>
> diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
> index f2128d8..4aedb11 1006
On Wed, Jun 29, 2016 at 3:11 PM, Timothy Arceri
wrote:
> On Wed, 2016-06-29 at 03:47 +0300, Grazvydas Ignotas wrote:
>> On Tue, Jun 28, 2016 at 10:53 AM, Timothy Arceri
>> wrote:
>> > On Mon, 2016-06-27 at 00:46 +1000, Timothy Arceri wrote:
>> > > On Sun, 2016-06-26 at 16:15 +0300, Grazvydas Igno
On 06/29/2016 06:13 AM, Ilia Mirkin wrote:
Basically we just have to scale up the coordinates and then add the
relevant sample offset. The code to handle this was already largely
present from Christoph's earlier attempts to pipe images through back in
the dark ages, this just hooks it all up.
On 06/29/2016 02:04 AM, Colin McDonald wrote:
> I'm not familiar with the code, other than diving in to fix these
> indirect multi-texture problems, so you will know much more about it
> than me.
>
> But, my understanding is that __glXInitVertexArrayState needs info
> from the server, obtained by
This patch is
Reviewed-by: Ian Romanick
On 06/29/2016 01:38 PM, Matt Turner wrote:
> This partially reverts commit d41f5396f3cb619729021390c273f838d92f11fb.
>
> That untested commit broke the tex-skipped-unit piglit test and the
> arbvparray Mesa demo when run with indirect GLX.
>
> state->arr
This patch is
Reviewed-by: Ian Romanick
On 06/29/2016 01:33 PM, Matt Turner wrote:
> ---
> src/mesa/main/dlist.c | 10 --
> 1 file changed, 4 insertions(+), 6 deletions(-)
>
> diff --git a/src/mesa/main/dlist.c b/src/mesa/main/dlist.c
> index 3845d2e..9d9e319 100644
> --- a/src/mesa/ma
From: Ian Romanick
---
src/mesa/drivers/dri/i965/brw_link.cpp | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp
b/src/mesa/drivers/dri/i965/brw_link.cpp
index 9cdbe30..2be8cbd 100644
--- a/src/mesa/drivers/dri/i965/brw_link.cpp
+++
From: Ian Romanick
Signed-off-by: Ian Romanick
---
src/mesa/drivers/dri/i965/brw_link.cpp | 20 ++--
src/mesa/drivers/dri/i965/intel_extensions.c | 1 +
2 files changed, 15 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp
b/src/mesa/driv
From: Ian Romanick
Signed-off-by: Ian Romanick
---
src/compiler/glsl/ir_optimization.h | 1 +
src/compiler/glsl/lower_instructions.cpp | 53
2 files changed, 54 insertions(+)
diff --git a/src/compiler/glsl/ir_optimization.h
b/src/compiler/glsl/ir_optimiz
From: Ian Romanick
Signed-off-by: Ian Romanick
---
src/mesa/state_tracker/st_extensions.c | 1 +
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 16 +++-
2 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/src/mesa/state_tracker/st_extensions.c
b/src/mesa/state_tracker
From: Ian Romanick
Signed-off-by: Ian Romanick
---
src/compiler/glsl/ir_optimization.h | 1 +
src/compiler/glsl/lower_instructions.cpp | 80
2 files changed, 81 insertions(+)
diff --git a/src/compiler/glsl/ir_optimization.h
b/src/compiler/glsl/ir_optimiz
From: Ian Romanick
Signed-off-by: Ian Romanick
---
src/mesa/drivers/dri/i965/brw_link.cpp | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp
b/src/mesa/drivers/dri/i965/brw_link.cpp
index 76c580b..3c331a5 100644
--- a/src/mesa/drivers/
From: Ian Romanick
BFM is (((1u << a) - 1) << b). Recognize a couple patterns that look
like this, and replace them with BFM.
NOTE: Using lower_bitfield_insert is definitely not the right way to
flag this optimization... so, I'm looking for some advice as to what the
right way is.
Signed-off-b
From: Ian Romanick
Signed-off-by: Ian Romanick
---
src/compiler/glsl/ast_to_hir.cpp | 3 ++-
src/compiler/glsl_types.cpp | 13 -
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/src/compiler/glsl/ast_to_hir.cpp b/src/compiler/glsl/ast_to_hir.cpp
index 0cfce68..a
From: Ian Romanick
This uses one less instruction.
Signed-off-by: Ian Romanick
---
src/mesa/drivers/dri/i965/brw_fs.h | 4
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 3 +++
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 26 +++-
src/mesa/dri
From: Ian Romanick
This isn't the lowering pass you want. Most GPUs that can support GLSL
1.30 have a multiply unit that can do something more interesting than
32x32->32. Many have 32x16->48. Any GPU that does, should do the
lowering in the backend. This is just the thing that will always wor
From: Ian Romanick
I noticed this when I tried to do frexp(float(some_unsigned)) in the
ir_unop_find_lsb lowering pass. The code generated for frexp() uses
fabs, and this resulted in an extra instruction. Ultimately I ended up
not using frexp.
Signed-off-by: Ian Romanick
---
src/compiler/nir
From: Ian Romanick
Previously SHADER_OPCODE_MULH could only exist on Gen7+, so the
assertion assumed the Gen7+ accumulator rules. A future patch will
allow this instruction on at least Gen6, so update the assertion.
Signed-off-by: Ian Romanick
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 6
From: Ian Romanick
Signed-off-by: Ian Romanick
---
src/compiler/glsl/ir_optimization.h | 1 +
src/compiler/glsl/lower_instructions.cpp | 91
2 files changed, 92 insertions(+)
diff --git a/src/compiler/glsl/ir_optimization.h
b/src/compiler/glsl/ir_optimiz
This patch series adds support for a (useful) subset of
GL_ARB_gpu_shader5 to every GPU in Mesa that supports GLSL 1.30 or
later. Many of these functions are needed to implement a lowering pass
for 64-bit integers on non-GL4 GPUs. It didn't make a lot of sense to
me to have an extension (public o
From: Ian Romanick
---
docs/specs/MESA_shader_integer_functions.txt | 519 +++
1 file changed, 519 insertions(+)
create mode 100644 docs/specs/MESA_shader_integer_functions.txt
diff --git a/docs/specs/MESA_shader_integer_functions.txt
b/docs/specs/MESA_shader_integer_f
From: Ian Romanick
Signed-off-by: Ian Romanick
---
src/compiler/glsl/ir_optimization.h | 1 +
src/compiler/glsl/lower_instructions.cpp | 73
2 files changed, 74 insertions(+)
diff --git a/src/compiler/glsl/ir_optimization.h
b/src/compiler/glsl/ir_optimiz
From: Ian Romanick
Signed-off-by: Ian Romanick
---
src/compiler/glsl/ir_function.cpp | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/src/compiler/glsl/ir_function.cpp
b/src/compiler/glsl/ir_function.cpp
index 0b4cb4b..c0b62af 100644
--- a/src/compiler/glsl/ir_f
From: Ian Romanick
This extension does not depend on the Gen. It only depends on the
availability of GLSL 1.30.
Signed-off-by: Ian Romanick
---
src/mesa/drivers/dri/i965/intel_extensions.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/intel_ex
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