Francisco Jerez writes:
> Serge Martin writes:
>
>> This fix getting the size of a struct arg. vec3 types still work ok.
>> Only buit-in args need to have power of two alignment, getTypeAllocSize
>> reports the correct size.
>> ---
>> src/gallium/state_trackers/clover/llvm/invocation.cpp | 3 ++
On Thu, Jun 23, 2016 at 02:00:30PM -0700, Jason Ekstrand wrote:
> ---
> src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 11 ++-
> src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 9 +
> src/mesa/drivers/dri/i965/gen8_surface_state.c| 9 +
> 3 files changed, 16
On Thu, Jun 23, 2016 at 02:00:22PM -0700, Jason Ekstrand wrote:
> ---
> src/mesa/drivers/dri/i965/brw_state.h| 9 ++
> src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 184
> +++
> 2 files changed, 193 insertions(+)
Patches 23-29 are:
Reviewed-by: Topi Pohjol
Jan Vesely writes:
> On Wed, 2016-06-22 at 20:52 -0400, Jan Vesely wrote:
>> Signed-off-by: Jan Vesely
>
> sorry for an early ping, but at least the first patch is needed to
> unbreak clover with recent llvm (otherwise all kernel launches fail
> with unknown kernel name)
>
I'm about to send out
On Thu, Jun 23, 2016 at 02:00:21PM -0700, Jason Ekstrand wrote:
> We're about to add generic versions which work across gens and those should
> have the brw name.
> ---
> src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 22 +++---
> 1 file changed, 11 insertions(+), 11 deletions(
On Mon, Jun 27, 2016 at 6:08 PM, Samuel Pitoiset
wrote:
>
>
> On 06/28/2016 12:06 AM, Ilia Mirkin wrote:
>>
>> On Mon, Jun 27, 2016 at 6:05 PM, Ilia Mirkin wrote:
>>>
>>> On Mon, Jun 27, 2016 at 6:04 PM, Samuel Pitoiset
>>> wrote:
On 06/28/2016 12:02 AM, Ilia Mirkin wrote:
>>
On 27.06.2016 19:52, Jose Fonseca wrote:
>
> BTW, I've been using http://editorconfig.org/ on several projects. It's
> widely supported by many editors including Emacs.
>
> There's even Python based tools to check editorconfig (
> https://github.com/editorconfig/editorconfig/wiki/FAQ#my-files-are-
On Mon, Jun 27, 2016 at 6:30 PM, Gurchetan Singh
wrote:
> Hi Ilia,
>
> The changes for get.c where prompted by the es3fIntegerStateQueryTests (see
> modules/gles3/functional/es3fIntegerStateQueryTests.cpp in the dEQP tree).
> Specifically, these few lines:
>
>>> const GLint validInitialValues[] =
Reviewed-by: Ilia Mirkin
Moderately sure this should work...
On Mon, Jun 27, 2016 at 6:59 PM, Samuel Pitoiset
wrote:
> Rely on the existence of a second destination when emitting a setcond
> flag is dangerous, because this doesn't mean that the flag has been
> correctly set. Instead rely on fla
On Mon, Jun 27, 2016 at 6:45 PM, Vinson Lee wrote:
> Fix this build error with GCC 4.4.
>
> CC state_tracker/st_nir_lower_builtin.lo
> In file included from state_tracker/st_nir_lower_builtin.c:61:
> state_tracker/st_nir.h:34: error: redefinition of typedef ‘nir_shader’
> ../../src/compiler/
On Tue, 2016-06-28 at 11:52 +1000, Timothy Arceri wrote:
> This will allow us to later split gl_shader into two structs.
> ---
> src/compiler/glsl/link_functions.cpp | 47 +-
> --
> 1 file changed, 22 insertions(+), 25 deletions(-)
>
> diff --git a/src/compiler/gls
---
src/compiler/glsl/builtin_functions.cpp | 2 +-
src/compiler/glsl/standalone_scaffolding.cpp | 4 +---
src/compiler/glsl/standalone_scaffolding.h | 2 +-
src/mesa/drivers/common/meta.c | 2 +-
src/mesa/main/ff_fragment_shader.cpp | 2 +-
src/mesa/main/shaderapi.c
This will allow us to later split gl_shader into two structs.
---
src/compiler/glsl/link_functions.cpp | 47 +---
1 file changed, 22 insertions(+), 25 deletions(-)
diff --git a/src/compiler/glsl/link_functions.cpp
b/src/compiler/glsl/link_functions.cpp
index 4e102
There are two distinctly different uses of this struct. The first
is to store GL shader objects. The second is to store information
about a shader stage thats been linked.
The two uses actually share few fields and there is clearly confusion
about their use. For example the linked shaders map one
There is only ever one shader so simplify the input params.
---
src/compiler/glsl/link_uniform_blocks.cpp | 7 ++-
src/compiler/glsl/linker.cpp | 5 ++---
src/compiler/glsl/linker.h| 3 +--
3 files changed, 5 insertions(+), 10 deletions(-)
diff --git a/src/compile
This will allow us to split gl_shader into two different structs, one for
shader objects and one for linked shaders.
---
src/compiler/glsl/builtin_functions.cpp | 4 ++--
src/compiler/glsl/builtin_variables.cpp | 2 +-
src/compiler/glsl/ir.h | 2 +-
src/compiler/glsl/linker.cpp
There are two distinctly different uses of this struct. The first
is to store GL shader objects. The second is to store information
about a shader stage thats been linked.
The only place the new structs overlap is the shader layout fields and
I intend to split that out into a third struct once thi
The drivers function only needs to be used when creating a struct for
linked shaders.
---
src/mesa/main/shaderapi.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/src/mesa/main/shaderapi.c b/src/mesa/main/shaderapi.c
index 07250cd..142e750 100644
--- a/src/mesa/main/shaderap
Rather than passing in gl_shader we now pass in the IR. This will
allow us to later split gl_shader into two structs. One for use
as a linked per stage shader struct and one for use as a GL shader
object.
---
src/compiler/glsl/linker.cpp | 413 ++-
1 file ch
Fix this build error with GCC 4.4.
CC state_tracker/st_nir_lower_builtin.lo
In file included from state_tracker/st_nir_lower_builtin.c:61:
state_tracker/st_nir.h:34: error: redefinition of typedef ‘nir_shader’
../../src/compiler/nir/nir.h:1830: note: previous declaration of ‘nir_shader’
was
Hi Julien and Christian,
I got a patch attached to fix the "fillout" problem, and please review.
But we still need to fix transcoding issue with interlaced as true. Our
transcode support tunneling, basic the decode buffer will be used directly for
encode.
Thanks,
Leo
___
This patch is
Reviewed-by: Ian Romanick
On 06/23/2016 11:15 AM, Matt Turner wrote:
> From: Colin McDonald
>
> There is no draw arrays protocol support for multi-texture coordinate
> arrays, so it is implemented by sending batches of immediate mode
> commands from emit_element_none in indirect_
On 06/23/2016 11:15 AM, Matt Turner wrote:
> From: Colin McDonald
>
> For each indirect context the indirect vertex array state must be initialised
> by __glXInitVertexArrayState in indirect_vertex_array.c. As noted in the
> routine header it requires that the glx context has been setup prior to
On 06/23/2016 11:15 AM, Matt Turner wrote:
> This partially reverts commit d41f5396f3cb619729021390c273f838d92f11fb.
>
> That untested commit broke the tex-skipped-unit piglit test and the
> arbvparray Mesa demo when run with indirect GLX.
>
> state->array_state is used during initialization, so
On 06/23/2016 11:15 AM, Matt Turner wrote:
> From: Colin McDonald
>
> At the same time, replace opcode numbers with names in
> __indirect_glVertexAttribPointer.
>
> Reviewed-by: Matt Turner
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=61907
> ---
> src/glx/indirect_vertex_array.c |
It looks like there's another premature return around line 10087.
On 06/27/2016 04:31 PM, Matt Turner wrote:
> ---
> src/mesa/main/dlist.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/src/mesa/main/dlist.c b/src/mesa/main/dlist.c
> index 3845d2e..1cf814b 100644
> --
This is unusual. Usually IDs listed on early stages of platform
definition are kept there as reserved for later use.
However these IDs here are not listed anymore in any of steppings
and devices IDs tables for Kabylake on configurations overview
section of BSpec.
So it is better removing them bef
The spec has been updated adding new PCI IDs.
v2: Avoid using "H" instead of HALO to keep names uniform - DK.
Cc: Dhinakaran Pandiyan
Signed-off-by: Rodrigo Vivi
---
intel/intel_chipset.h | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/intel/intel_chipset.h
Reviewed-by: Jason Ekstrand
On Mon, Jun 27, 2016 at 4:35 PM, Nanley Chery wrote:
> Signed-off-by: Nanley Chery
> ---
> src/intel/isl/isl.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
> index ef86228..64aced8 100644
> --- a
In the next patch, ISL will unconditionally perform verification of a
surface's tiling and usage. Since it will require that w-tiled images
be stencil buffers, create a stencil surface to copy from a
w-tiled/stencil surface.
Signed-off-by: Nanley Chery
---
src/intel/vulkan/anv_meta_blit2d.c | 17
Signed-off-by: Nanley Chery
---
src/intel/vulkan/anv_image.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
index 77d9931..b3f5f5c 100644
--- a/src/intel/vulkan/anv_image.c
+++ b/src/intel/vulkan/anv_image
This reverts commit 091f1da902c71ac8d3d27b325a118e2f683f1ae5.
Although a user may specify a specfic tiling bit, ISL should still
prevent incompatible tiling/surface combinations.
Signed-off-by: Nanley Chery
---
Prior to patch https://patchwork.freedesktop.org/patch/95338/ ,
this change made cru
Signed-off-by: Nanley Chery
---
src/intel/isl/isl.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index ef86228..64aced8 100644
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -989,7 +989,7 @@ isl_has_matching_typed_storage_im
---
src/mesa/main/dlist.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mesa/main/dlist.c b/src/mesa/main/dlist.c
index 3845d2e..1cf814b 100644
--- a/src/mesa/main/dlist.c
+++ b/src/mesa/main/dlist.c
@@ -10366,7 +10366,7 @@ print_list(struct gl_context *ctx, GLuint list
Rely on the existence of a second destination when emitting a setcond
flag is dangerous, because this doesn't mean that the flag has been
correctly set. Instead rely on flagsDef like what emitX() does
for flagsSrc.
Signed-off-by: Samuel Pitoiset
Cc:
---
src/gallium/drivers/nouveau/codegen/nv50_
Remove 'reg' option that does not actually exist, elaborate more about
'sync' and add the missing options.
Signed-off-by: Grazvydas Ignotas
---
no commit access, if this is ok please somebody push
docs/envvars.html | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git
Hi Ilia,
The changes for get.c where prompted by the es3fIntegerStateQueryTests (see
modules/gles3/functional/es3fIntegerStateQueryTests.cpp in the dEQP tree).
Specifically, these few lines:
>> const GLint validInitialValues[] = {GL_BACK, GL_NONE};
>> m_verifier->verifyIntegerAnyOf(m_testCtx, GL_
On Mon, Jun 27, 2016 at 3:27 PM, Brian Paul wrote:
> On 06/27/2016 03:42 PM, Matt Turner wrote:
>>
>> ---
>> src/compiler/glsl/ir_constant_expression.cpp| 11 +++
>> src/compiler/glsl/link_uniform_initializers.cpp | 3 +--
>> 2 files changed, 4 insertions(+), 10 deletions(-)
>>
>>
On 06/27/2016 03:42 PM, Matt Turner wrote:
---
src/compiler/glsl/ir_constant_expression.cpp| 11 +++
src/compiler/glsl/link_uniform_initializers.cpp | 3 +--
2 files changed, 4 insertions(+), 10 deletions(-)
diff --git a/src/compiler/glsl/ir_constant_expression.cpp
b/src/compil
Reviewed-by: Ilia Mirkin
On Mon, Jun 27, 2016 at 6:13 PM, Samuel Pitoiset
wrote:
> Signed-off-by: Samuel Pitoiset
> Cc:
> ---
> src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emi
Signed-off-by: Samuel Pitoiset
Cc:
---
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
index 25a9a52..334c078
On 06/28/2016 12:06 AM, Ilia Mirkin wrote:
On Mon, Jun 27, 2016 at 6:05 PM, Ilia Mirkin wrote:
On Mon, Jun 27, 2016 at 6:04 PM, Samuel Pitoiset
wrote:
On 06/28/2016 12:02 AM, Ilia Mirkin wrote:
This loses you saturation. Does the target account for this?
No saturate flag for FADD32I.
On Mon, Jun 27, 2016 at 6:05 PM, Ilia Mirkin wrote:
> On Mon, Jun 27, 2016 at 6:04 PM, Samuel Pitoiset
> wrote:
>>
>>
>> On 06/28/2016 12:02 AM, Ilia Mirkin wrote:
>>>
>>> This loses you saturation. Does the target account for this?
>>
>>
>> No saturate flag for FADD32I.
>
> That's not what I ask
On Mon, Jun 27, 2016 at 6:04 PM, Samuel Pitoiset
wrote:
>
>
> On 06/28/2016 12:02 AM, Ilia Mirkin wrote:
>>
>> This loses you saturation. Does the target account for this?
>
>
> No saturate flag for FADD32I.
That's not what I asked.
___
mesa-dev mailing
Reviewed-by: Ilia Mirkin
On Mon, Jun 27, 2016 at 5:55 PM, Samuel Pitoiset
wrote:
> LOP only allows to emit 19-bits immediates.
>
> Signed-off-by: Samuel Pitoiset
> Cc:
> ---
> src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
On 06/28/2016 12:02 AM, Ilia Mirkin wrote:
This loses you saturation. Does the target account for this?
No saturate flag for FADD32I.
On Mon, Jun 27, 2016 at 5:55 PM, Samuel Pitoiset
wrote:
FADD only allows to emit 19-bits immediates.
Signed-off-by: Samuel Pitoiset
Cc:
---
src/galliu
On 06/28/2016 12:01 AM, Ilia Mirkin wrote:
Hm, dangerous:
CodeEmitterGM107::emitCC(int pos)
{
emitField(pos, 1, insn->defExists(1));
}
That should *probably* be insn->flagsDef >= 0. IIRC I fixed up
gf100/gk110 before. But that might have been nv50-specific, I forget
(which has somewhat dif
This loses you saturation. Does the target account for this?
On Mon, Jun 27, 2016 at 5:55 PM, Samuel Pitoiset
wrote:
> FADD only allows to emit 19-bits immediates.
>
> Signed-off-by: Samuel Pitoiset
> Cc:
> ---
> src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 2 +-
> 1 file chang
Hm, dangerous:
CodeEmitterGM107::emitCC(int pos)
{
emitField(pos, 1, insn->defExists(1));
}
That should *probably* be insn->flagsDef >= 0. IIRC I fixed up
gf100/gk110 before. But that might have been nv50-specific, I forget
(which has somewhat different flags).
On Mon, Jun 27, 2016 at 5:55 PM
LOP only allows to emit 19-bits immediates.
Signed-off-by: Samuel Pitoiset
Cc:
---
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
b/src/gallium/drivers/nou
FADD only allows to emit 19-bits immediates.
Signed-off-by: Samuel Pitoiset
Cc:
---
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
b/src/gallium/drivers/no
Signed-off-by: Samuel Pitoiset
Cc:
---
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
index 80761e2..c7bd4e1
On Mon, Jun 27, 2016 at 11:30 AM, Nanley Chery wrote:
> This causes tests that attempt to create linear depth buffers on
> Gen7+ (unsupported), to be skipped.
>
> Signed-off-by: Nanley Chery
> ---
> src/tests/func/miptree/miptree.c | 39 ++-
> 1 file changed,
---
src/mesa/main/texcompress_fxt1.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/main/texcompress_fxt1.c b/src/mesa/main/texcompress_fxt1.c
index ae339e1..c5646fb 100644
--- a/src/mesa/main/texcompress_fxt1.c
+++ b/src/mesa/main/texcompress_fxt1.c
@@ -177,8 +17
---
src/mesa/swrast/s_masking.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/swrast/s_masking.c b/src/mesa/swrast/s_masking.c
index c95587b..c10bf1a 100644
--- a/src/mesa/swrast/s_masking.c
+++ b/src/mesa/swrast/s_masking.c
@@ -56,8 +56,8 @@ _swrast_mask_rgba_sp
I do appreciate the cleverness, but unfortunately it prevents a lot more
cleverness in the form of additional compiler optimizations brought on
by -fstrict-aliasing.
No difference in OglBatch7 (n=20).
Co-authored-by: Davin McCall
---
src/compiler/glsl/ast.h| 4 +-
---
src/mesa/main/uniform_query.cpp | 45 -
1 file changed, 31 insertions(+), 14 deletions(-)
diff --git a/src/mesa/main/uniform_query.cpp b/src/mesa/main/uniform_query.cpp
index 127f097..3e460b0 100644
--- a/src/mesa/main/uniform_query.cpp
+++ b/src/mesa/m
---
src/compiler/glsl/ir_constant_expression.cpp| 11 +++
src/compiler/glsl/link_uniform_initializers.cpp | 3 +--
2 files changed, 4 insertions(+), 10 deletions(-)
diff --git a/src/compiler/glsl/ir_constant_expression.cpp
b/src/compiler/glsl/ir_constant_expression.cpp
index e79d5ef
Compilers are perfectly capable of generating efficient code for calls
like these to memcpy().
---
src/glx/packrender.h | 34 --
src/glx/packsingle.h | 15 +--
2 files changed, 25 insertions(+), 24 deletions(-)
diff --git a/src/glx/packrender.h b/src/gl
Based on work by Davin McCall from last summer.
The biggest change is to exec_list. Previously, the head and tail sentinels
overlapped, saving the size of a pointer. Unfortunately this is not allowed by
the aliasing rules.
I have fixed all warnings GCC reports in my normal build. I have no attem
Improves performance of OglBatch7 by 4.06851% +/- 1.17925% (n=169) on
Haswell, and cuts ~18k of .text:
text data bss dec hex filename
5824627 28781629384 6141827 5db783 before/i965_dri.so
5806354 28781629384 6123554 5d7022 after/i965_dri.so
---
configure
On Wed, 2016-06-22 at 20:52 -0400, Jan Vesely wrote:
> Signed-off-by: Jan Vesely
sorry for an early ping, but at least the first patch is needed to
unbreak clover with recent llvm (otherwise all kernel launches fail
with unknown kernel name)
thanks,
Jan
> ---
> .../state_trackers/clover/llvm/i
Hi Leo,
Sorry for the inconvenience, could you let me know how to reproduce the
problem ?
I have been playing with some gst pipelines and they all work but I can
only test with nouveau driver.
Cheers
Julien
On 27 June 2016 at 21:35, Leo Liu wrote:
> This patch break omx decode to file, it got
From: Dave Airlie
This just does the same as the previous commit in the
other direction.
---
src/gallium/auxiliary/tgsi/tgsi_exec.c | 97 ++
1 file changed, 28 insertions(+), 69 deletions(-)
diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.c
b/src/gallium/auxil
From: Dave Airlie
These 3 functions could be collapsed into a single one,
passing in some control values.
---
src/gallium/auxiliary/tgsi/tgsi_exec.c | 87 +++---
1 file changed, 27 insertions(+), 60 deletions(-)
diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.c
b/
On Mon, Jun 27, 2016 at 4:17 PM, Gurchetan Singh
wrote:
> There a few places in the code where clearing and reading are done on
> incorrect
> buffers for GLES contexts. See comments for details. This fixes 75 GLES3
> dEQP tests on the surfaceless platform with no regressions.
>
> v2: Corrected
https://bugs.freedesktop.org/show_bug.cgi?id=96698
Bug ID: 96698
Summary: [swrast] piglit glsl-array-bounds-05 regression
Product: Mesa
Version: git
Hardware: x86-64 (AMD64)
OS: Linux (All)
Status: NEW
Key
This patch break omx decode to file, it got seg fault. Will take look
further.
Regards,
Leo
On 06/27/2016 04:16 AM, Julien Isorce wrote:
Signed-off-by: Julien Isorce
---
src/gallium/state_trackers/omx/vid_dec.c | 51
1 file changed, 26 insertions(+), 25 de
On 06/27/2016 04:16 AM, Julien Isorce wrote:
Interlaced can be true for nouveau driver.
Signed-off-by: Julien Isorce
---
src/gallium/state_trackers/omx/vid_dec.c | 26 --
1 file changed, 24 insertions(+), 2 deletions(-)
diff --git a/src/gallium/state_trackers/omx/v
There a few places in the code where clearing and reading are done on incorrect
buffers for GLES contexts. See comments for details. This fixes 75 GLES3
dEQP tests on the surfaceless platform with no regressions.
v2: Corrected unclear comment
---
src/mesa/main/buffers.c | 14 --
sr
On 27/06/16 15:45, Brian Paul wrote:
> On 06/27/2016 02:10 AM, Alejandro Piñeiro wrote:
>> silent, flush, incomplete_tex and incomplete_fbo flags were not
>> documented (see src/mesa/main.debug.c for more info).
>>
>> FP is not checked anymore.
>> ---
>>
>> Didn't know about the flush option for ME
On 27/06/16 18:12, Ilia Mirkin wrote:
> On Mon, Jun 27, 2016 at 6:36 AM, Alejandro Piñeiro
> wrote:
>>
>> On 27/06/16 12:33, Alejandro Piñeiro wrote:
>>> On 27/06/16 03:08, Grazvydas Ignotas wrote:
On Sat, Jun 25, 2016 at 4:54 PM, Alejandro Piñeiro
wrote:
> In theory they don't ov
On Thu, Jun 23, 2016 at 02:00:18PM -0700, Jason Ekstrand wrote:
> ---
> src/mesa/drivers/dri/i965/brw_state.h| 8 +++
> src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 83
>
> 2 files changed, 91 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/br
On Mon, Jun 27, 2016 at 3:06 PM, Kenneth Graunke wrote:
> On Monday, June 27, 2016 11:43:28 AM PDT Matt Turner wrote:
>> On Mon, Jun 27, 2016 at 4:44 AM, Rob Clark wrote:
>> > On Mon, Jun 27, 2016 at 7:13 AM, Alan Swanson
>> > wrote:
>> >> On 2016-06-25 13:37, Rob Clark wrote:
>> >>>
>> >>> Som
On Mon, Jun 27, 2016 at 3:01 PM, Marek Olšák wrote:
> From: Marek Olšák
>
> This was missing.
>
> Cc: 12.0
Reviewed-by: Alex Deucher
> ---
> src/gallium/drivers/radeonsi/si_state.c | 5 +
> src/gallium/drivers/radeonsi/sid.h | 6 ++
> 2 files changed, 11 insertions(+)
>
> diff -
On Monday, June 27, 2016 11:43:28 AM PDT Matt Turner wrote:
> On Mon, Jun 27, 2016 at 4:44 AM, Rob Clark wrote:
> > On Mon, Jun 27, 2016 at 7:13 AM, Alan Swanson
> > wrote:
> >> On 2016-06-25 13:37, Rob Clark wrote:
> >>>
> >>> Some games are sloppy.. perhaps because it is defined behavior for D
On Mon, Jun 27, 2016 at 2:43 PM, Matt Turner wrote:
> On Mon, Jun 27, 2016 at 4:44 AM, Rob Clark wrote:
>> On Mon, Jun 27, 2016 at 7:13 AM, Alan Swanson
>> wrote:
>>> On 2016-06-25 13:37, Rob Clark wrote:
Some games are sloppy.. perhaps because it is defined behavior for DX or
pe
From: Marek Olšák
This was missing.
Cc: 12.0
---
src/gallium/drivers/radeonsi/si_state.c | 5 +
src/gallium/drivers/radeonsi/sid.h | 6 ++
2 files changed, 11 insertions(+)
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index 2e2c5
On Mon, Jun 27, 2016 at 4:44 AM, Rob Clark wrote:
> On Mon, Jun 27, 2016 at 7:13 AM, Alan Swanson
> wrote:
>> On 2016-06-25 13:37, Rob Clark wrote:
>>>
>>> Some games are sloppy.. perhaps because it is defined behavior for DX or
>>> perhaps because nv blob driver defaults things to zero.
>>>
>>>
On Thu, Jun 23, 2016 at 02:00:08PM -0700, Jason Ekstrand wrote:
> ---
> src/intel/isl/isl.h | 7 +++
> src/intel/isl/isl_surface_state.c | 39
> ---
> 2 files changed, 43 insertions(+), 3 deletions(-)
Reviewed-by: Topi Pohjolainen
>
> dif
On Mon, Jun 27, 2016 at 10:35 AM, Nicolai Hähnle wrote:
> On 24.06.2016 20:48, Marek Olšák wrote:
>>
>> On Fri, Jun 24, 2016 at 1:09 PM, Nicolai Hähnle
>> wrote:
>>>
>>> On 22.06.2016 20:29, Marek Olšák wrote:
From: Marek Olšák
DCC for displayable surfaces is allocated i
This causes tests that attempt to create linear depth buffers on
Gen7+ (unsupported), to be skipped.
Signed-off-by: Nanley Chery
---
src/tests/func/miptree/miptree.c | 39 ++-
1 file changed, 34 insertions(+), 5 deletions(-)
diff --git a/src/tests/func/miptre
We know what the end looks like without examining .tail: it's NULL. It's
always NULL.
---
src/mesa/drivers/dri/i965/brw_cfg.h | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_cfg.h
b/src/mesa/drivers/dri/i965/brw_cfg.h
index 5b770aa..1c90eab 1
On Thu, Jun 23, 2016 at 02:00:09PM -0700, Jason Ekstrand wrote:
> ---
> src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 171
> +-
> src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 6 +
> 2 files changed, 175 insertions(+), 2 deletions(-)
>
> diff --git a/src/mesa/driver
On Thu, Jun 23, 2016 at 02:00:12PM -0700, Jason Ekstrand wrote:
> ---
> src/mesa/drivers/dri/i965/brw_blorp.c | 148
> ++
> src/mesa/drivers/dri/i965/brw_blorp.h | 6 ++
> 2 files changed, 154 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
On 06/24/2016 09:30 AM, Emil Velikov wrote:
> On 20 June 2016 at 19:14, Ian Romanick wrote:
>> On 06/17/2016 11:15 AM, Emil Velikov wrote:
>>> On 17 June 2016 at 18:20, Ian Romanick wrote:
From: Ian Romanick
Khronos recommends that the GLES 3.1 library also be called libGLESv2.
>>
On Mon, Jun 27, 2016 at 6:36 AM, Alejandro Piñeiro wrote:
>
>
> On 27/06/16 12:33, Alejandro Piñeiro wrote:
>> On 27/06/16 03:08, Grazvydas Ignotas wrote:
>>> On Sat, Jun 25, 2016 at 4:54 PM, Alejandro Piñeiro
>>> wrote:
In theory they don't overdrawn. The test has a square formed by N
On Mon, Jun 27, 2016 at 08:40:41AM -0700, Jason Ekstrand wrote:
>On Mon, Jun 27, 2016 at 8:34 AM, Pohjolainen, Topi
><[1]topi.pohjolai...@intel.com> wrote:
>
>On Thu, Jun 23, 2016 at 02:00:11PM -0700, Jason Ekstrand wrote:
>> ---
>> src/mesa/drivers/dri/i965/intel_mipmap_tree.
On Mon, Jun 27, 2016 at 8:34 AM, Pohjolainen, Topi <
topi.pohjolai...@intel.com> wrote:
> On Thu, Jun 23, 2016 at 02:00:11PM -0700, Jason Ekstrand wrote:
> > ---
> > src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 89
> +++
> > src/mesa/drivers/dri/i965/intel_mipmap_tree.h
On Thu, Jun 23, 2016 at 02:00:11PM -0700, Jason Ekstrand wrote:
> ---
> src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 89
> +++
> src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 5 ++
> 2 files changed, 94 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/intel_
The linker deals with atomic counters in terms of uniforms. This is OK
but when we want to know the number of used atomic counters since a 2
elements atomic counters array will use 2 counters but only 1 uniform.
Renamed the data structures used in the linker for disambiguation.
Fixes GL44-CTS.arr
On Monday, June 27, 2016 2:50:02 PM PDT Iago Toral wrote:
> On Sun, 2016-06-26 at 01:53 -0700, Kenneth Graunke wrote:
> > emit_urb_writes() contains code to emit an EOT write with no actual
> > data when there are no output varyings. This makes sense for the VS
> > and TES stages, where it's calle
This code fragment:
+ /* t = frac(i_vtex*size)
...
+ ureg_MUL(shader, t, i_vtex, ureg_imm1f(shader, size));
Probably doesn't do what you expect it to do when the pixel center is at
0.5 instead of 0.0.
For the matrix and most other filters the difference doesn't matter
because you get the
On 06/24/2016 08:45 AM, Roland Scheidegger wrote:
For what formats is this really needed? I think that usually if you have
a rgb surface, the corresponding rgbx format should be used instead of
rgba (which implicitly has the alpha == 1 property for blending). But
maybe some formats are missing...
Hi Christian,
I haven't taken that into account, but how will it any way affect my
calculation. I have written
the code taking inspiration from the way matrix_filter uses offsets.
Regards,
Nayan.
On Mon, Jun 27, 2016 at 6:55 PM, Christian König
wrote:
> Hi guys,
>
> Nayan have you taken into a
On 06/27/2016 02:10 AM, Alejandro Piñeiro wrote:
silent, flush, incomplete_tex and incomplete_fbo flags were not
documented (see src/mesa/main.debug.c for more info).
FP is not checked anymore.
---
Didn't know about the flush option for MESA_DEBUG until Grazvydas Ignotas
mentioned it on a freed
Hi guys,
Nayan have you taken into account that the pixel center is at 0.5 and
not 0.0?
Regards,
Christian.
Am 26.06.2016 um 22:30 schrieb Andy Furniss:
Nayan Deshmukh wrote:
Hi Andy,
On Sun, Jun 26, 2016 at 12:25 AM, Andy Furniss
wrote:
Nayan Deshmukh wrote:
Hi Andy,
Thanks for te
On Sun, 2016-06-26 at 01:53 -0700, Kenneth Graunke wrote:
> emit_urb_writes() contains code to emit an EOT write with no actual
> data when there are no output varyings. This makes sense for the VS
> and TES stages, where it's called once at the end of the program.
>
> However, in the geometry sh
On Mon, Jun 27, 2016 at 7:13 AM, Alan Swanson wrote:
> On 2016-06-25 13:37, Rob Clark wrote:
>>
>> Some games are sloppy.. perhaps because it is defined behavior for DX or
>> perhaps because nv blob driver defaults things to zero.
>>
>> So add driconf param to force uninitialized variables to defa
On 2016-06-25 13:37, Rob Clark wrote:
Some games are sloppy.. perhaps because it is defined behavior for DX
or
perhaps because nv blob driver defaults things to zero.
So add driconf param to force uninitialized variables to default to
zero.
This issue was observed with rust, from steam store
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