There seemed to be missing one break in nested switchcases.
Signed-off-by: Juha-Pekka Heikkila
---
src/compiler/nir/nir_search.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/compiler/nir/nir_search.c b/src/compiler/nir/nir_search.c
index dc53a90..df80c0f 100644
--- a/src/compiler/nir/
On Friday, April 22, 2016 7:32:43 AM PDT Samuel Iglesias Gonsálvez wrote:
> NIR will lower it in nir_opt_algebraic.
>
> Signed-off-by: Samuel Iglesias Gonsálvez
> ---
> src/mesa/drivers/dri/i965/brw_link.cpp | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_l
On Friday, April 22, 2016 8:53:29 AM PDT Topi Pohjolainen wrote:
> Signed-off-by: Topi Pohjolainen
> ---
> src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 44 ++
+-
> 1 file changed, 36 insertions(+), 8 deletions(-)
Both of these are:
Reviewed-by: Kenneth Graunke
signat
On Saturday, April 16, 2016 4:43:05 PM PDT Topi Pohjolainen wrote:
> Signed-off-by: Topi Pohjolainen
> ---
> src/mesa/drivers/dri/i965/brw_blorp.cpp | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp b/src/mesa/drivers/dri/
i965/brw
On Saturday, April 16, 2016 4:43:04 PM PDT Topi Pohjolainen wrote:
> Signed-off-by: Topi Pohjolainen
> ---
> src/mesa/drivers/dri/i965/brw_blorp.cpp | 3 ++-
> src/mesa/drivers/dri/i965/gen6_blorp.cpp | 5 +
> src/mesa/drivers/dri/i965/gen8_blorp.cpp | 4 +++-
> 3 files changed, 10 insertion
Suggested-by: Kenneth Graunke
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 14 +++---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 5 ++---
2 files changed, 9 insertions(+), 10 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 44 +++-
1 file changed, 36 insertions(+), 8 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index be16941..40b9135 10
NIR will lower it in nir_opt_algebraic.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/mesa/drivers/dri/i965/brw_link.cpp | 1 -
1 file changed, 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp
b/src/mesa/drivers/dri/i965/brw_link.cpp
index bb7e1eb..ee62ada 100644
--- a/src/
I'm about to implement a scalar TCS backend, and I'd rather not
duplicate all of this code there.
One change is that we now write the tessellation levels from all
TCS threads, rather than just the first. This is pretty harmless,
and was easier. The IF/ENDIF needed for that are gone; otherwise
th
I want to add another condition. Moving the indirect_offset.file
check out a level should make this a little easier.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp | 88 --
1 file changed, 46 insertions(+), 42 deletions(-)
diff --git a
Unlike most shader stages, the Hull Shader hardware makes us explicitly
tell it how many threads to dispatch and manually configure the channel
mask. One perk of this is that we have a lot of flexibility - we can
run it in either SIMD4x2 or SIMD8 mode.
Treating it as SIMD8 means that shaders with
Also, move them to brw_shader.cpp so they're in a location for code
used by both the vec4 and fs worlds.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_shader.cpp | 47 ++
src/mesa/drivers/dri/i965/brw_shader.h | 4 +++
src/mesa/drivers/dri/i9
They can be affected by URB writes.
In the upcoming scalar TCS backend, this prevents read-modify-write
cycles from being broken by CSE removing reads.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_shader.cpp | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/mesa/dri
Signed-off-by: Jordan Justen
---
src/mesa/drivers/dri/i965/Makefile.sources | 1 +
src/mesa/drivers/dri/i965/brw_context.c | 4 +-
src/mesa/drivers/dri/i965/brw_context.h | 5 +
src/mesa/drivers/dri/i965/brw_queryobj.c | 35 ++-
src/mesa/drivers/dri/i965/gen6_queryobj.c
Signed-off-by: Jordan Justen
---
src/mesa/drivers/dri/i965/brw_context.h | 4 +++
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 45 +++
src/mesa/drivers/dri/i965/intel_reg.h | 1 +
3 files changed, 50 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/
Signed-off-by: Jordan Justen
---
src/mesa/drivers/dri/i965/brw_context.h | 2 ++
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 15 +++
src/mesa/drivers/dri/i965/intel_reg.h | 1 +
3 files changed, 18 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
Signed-off-by: Jordan Justen
---
src/mesa/drivers/dri/i965/brw_context.h | 2 ++
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 26 ++
2 files changed, 28 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
Signed-off-by: Jordan Justen
---
docs/GL3.txt | 2 +-
docs/relnotes/11.3.0.html | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/docs/GL3.txt b/docs/GL3.txt
index 6214f8d..63ebc67 100644
--- a/docs/GL3.txt
+++ b/docs/GL3.txt
@@ -201,7 +201,7 @@ GL 4.4, GLSL 4.40:
I sent out an update to the piglit 'qbo' test, which this series
passes.
I didn't test the Geometry, Tessellation or Compute queries.
Jordan Justen (9):
i965: Use offset instead of index in brw_store_register_mem64
squash: i965: Move brw_store_register_mem64 to intel_batchbuffer.c
i965: Add
Signed-off-by: Jordan Justen
---
src/mesa/drivers/dri/i965/intel_reg.h | 38 +++
1 file changed, 38 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_reg.h
b/src/mesa/drivers/dri/i965/intel_reg.h
index 365c045..01b4358 100644
--- a/src/mesa/drivers/dri/i
This matches the byte based offset of brw_load_register_mem*.
The function is also move into intel_batchbuffer.c like
brw_load_register_mem*.
Signed-off-by: Jordan Justen
---
src/mesa/drivers/dri/i965/brw_context.h| 2 +-
.../drivers/dri/i965/brw_performance_monitor.c | 5 ++--
---
src/mesa/drivers/dri/i965/brw_context.h | 4 +--
src/mesa/drivers/dri/i965/gen6_queryobj.c | 43 ---
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 37 +++
3 files changed, 39 insertions(+), 45 deletions(-)
diff --git a/src/mesa/drivers/
Signed-off-by: Jordan Justen
---
src/mesa/drivers/dri/i965/brw_context.h | 4
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 32 +++
2 files changed, 36 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_contex
From: Iago Toral Quiroga
At least i965 hardware does not have native support for truncating doubles.
v2:
- Simplified the implementation significantly.
- Fixed the else branch, that was not doing what we wanted.
---
src/compiler/nir/nir.h | 1 +
src/compiler/nir/nir_lower_
On Thu, Apr 21, 2016 at 06:28:15PM +0200, Bas Nieuwenhuizen wrote:
> shader->config is not updated for compute kernels.
>
> Signed-off-by: Bas Nieuwenhuizen
This fixes compute shaders that use scratch. Thanks.
Reviewed-by: Tom Stellard
> ---
> src/gallium/drivers/radeonsi/si_compute.c
On Fri, Apr 22, 2016 at 12:46 AM, Timothy Arceri
wrote:
> On Thu, 2016-03-31 at 09:44 -0400, Ilia Mirkin wrote:
>> Presumably you also want to remove the enable from Consts.Extensions?
>> (mtypes.h)
>
> I left it there because I thought overriding would break without it
> meaning people cant force
On Thu, 2016-03-31 at 09:44 -0400, Ilia Mirkin wrote:
> Presumably you also want to remove the enable from Consts.Extensions?
> (mtypes.h)
I left it there because I thought overriding would break without it
meaning people cant force enable it in compat profile. Not sure if
that's important or not.
On 21.04.2016 13:51, Bas Nieuwenhuizen wrote:
We can use shaders from multiple contexts, and they were not
otherwise locked yet.
Ouch... I guess this is why compute scratch buffers used to be per-program?
I'm still trying to wrap my head around the possible code paths here...
are you sure tha
> On 20 April 2016 at 03:52, Rob Herring wrote:
>> On Tue, Apr 19, 2016 at 8:03 PM, Emil Velikov
>> wrote:
>>> Looking at this patch and Varad's work
>>> there a hunk missing here [1]. Did you not come across the issue in
>>> question ?
>>
>> I don't think it is a real issue. I traced the code f
On 2016-03-31 21:57, Timothy Arceri wrote:
---
src/compiler/glsl/lower_packed_varyings.cpp | 25
+
1 file changed, 25 insertions(+)
diff --git a/src/compiler/glsl/lower_packed_varyings.cpp
b/src/compiler/glsl/lower_packed_varyings.cpp
index ad766bb..6e7a289 100644
---
Acked-by: Edward O'Callaghan
On 2016-03-31 21:57, Timothy Arceri wrote:
These outputs have a separate location domain from per-vertex outputs
and need to be handled separately. For now just skip validation so we
don't invalidate valid shaders.
---
src/compiler/glsl/link_varyings.cpp | 16 +
Acked-by: Edward O'Callaghan
On 2016-03-31 21:58, Timothy Arceri wrote:
---
docs/GL3.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/docs/GL3.txt b/docs/GL3.txt
index f6248da..ede8cf5 100644
--- a/docs/GL3.txt
+++ b/docs/GL3.txt
@@ -193,11 +193,11 @@ GL 4.4, GLSL 4.
Reviewed-by: Edward O'Callaghan
On 2016-03-31 21:57, Timothy Arceri wrote:
---
src/compiler/glsl/ast_type.cpp | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/compiler/glsl/ast_type.cpp
b/src/compiler/glsl/ast_type.cpp
index 30c9eff..de3fdcc 100644
--- a/src/compiler/glsl/ast_type.cpp
Reviewed-by: Nicolai Hähnle
On 21.04.2016 13:51, Bas Nieuwenhuizen wrote:
Signed-off-by: Bas Nieuwenhuizen
---
src/gallium/drivers/radeonsi/si_compute.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/gallium/drivers/radeonsi/si_compute.c
b/src/gallium/drivers/radeonsi/si_compute
On Broadwell, I get the following shader-db statistics:
Tessellation Control Shaders:
total instructions in shared programs: 57327 -> 57012 (-0.55%)
instructions in affected programs: 27334 -> 27019 (-1.15%)
helped: 45
HURT: 0
total cycles in shared programs: 265692 -> 255188 (-3.
On Thu, Apr 21, 2016 at 5:18 PM, Emil Velikov wrote:
> On 21 April 2016 at 22:50, Jason Ekstrand wrote:
>> On Thu, Apr 21, 2016 at 6:16 AM, Emil Velikov
>> wrote:
>>>
>>> From: Emil Velikov
>>>
>>> Rather than parsing through the same files (public headers) twice, tweak
>>> the python script to
https://bugs.freedesktop.org/show_bug.cgi?id=94955
--- Comment #18 from Roland Scheidegger ---
(In reply to Bruce Cherniak from comment #16)
> BTW, for my edification, what indicates it might be a bug in the mip level
> calculation?
That was just a guess as it hit the per-pixel mip computations,
https://bugs.freedesktop.org/show_bug.cgi?id=94955
--- Comment #17 from Roland Scheidegger ---
(In reply to Bruce Cherniak from comment #11)
> Created attachment 123134 [details]
> tex_sample_func
>
> Here's the ir for the jit'd sampler. I forced "use_tex_func" so it didn't
> inline with the FS
https://bugs.freedesktop.org/show_bug.cgi?id=94955
--- Comment #16 from Bruce Cherniak ---
BTW, for my edification, what indicates it might be a bug in the mip level
calculation?
--
You are receiving this mail because:
You are the assignee for the bug.
You are the QA Contact for the bug.___
On Thu, Apr 21, 2016 at 5:04 PM, Emil Velikov
wrote:
> On 21 April 2016 at 23:05, Jason Ekstrand wrote:
> > On Thu, Apr 21, 2016 at 6:16 AM, Emil Velikov
> > wrote:
> >>
> >> From: Emil Velikov
> >>
> >> I.e do not use -lfoo directly.
> >>
> >> Signed-off-by: Emil Velikov
> >> ---
> >> src/i
---
.../drivers/swr/rasterizer/scripts/knob_defs.py| 4 +++-
.../rasterizer/scripts/templates/knobs.template| 25 +-
2 files changed, 27 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/swr/rasterizer/scripts/knob_defs.py
b/src/gallium/drivers/swr/raste
---
.../drivers/swr/rasterizer/core/frontend.cpp | 3 ++-
src/gallium/drivers/swr/rasterizer/core/frontend.h | 2 +-
src/gallium/drivers/swr/rasterizer/core/utils.cpp | 31 +++---
src/gallium/drivers/swr/rasterizer/core/utils.h| 3 ++-
.../drivers/swr/rasterizer/jitte
---
src/gallium/drivers/swr/rasterizer/memory/LoadTile.cpp | 12 +++-
src/gallium/drivers/swr/swr_memory.h | 2 +-
2 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/src/gallium/drivers/swr/rasterizer/memory/LoadTile.cpp
b/src/gallium/drivers/swr/rasterizer/
For example, R10G10B10A2_UNORM.
---
.../drivers/swr/rasterizer/jitter/fetch_jit.cpp| 190 -
1 file changed, 189 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/swr/rasterizer/jitter/fetch_jit.cpp
b/src/gallium/drivers/swr/rasterizer/jitter/fetch_jit.cpp
inde
Add explicit inline and non-inline versions of CompleteDrawContext
to make gcc happy.
---
src/gallium/drivers/swr/rasterizer/core/threads.cpp | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/src/gallium/drivers/swr/rasterizer/core/threads.cpp
b/src/gallium/driv
https://bugs.freedesktop.org/show_bug.cgi?id=94955
--- Comment #15 from Bruce Cherniak ---
Created attachment 123137
--> https://bugs.freedesktop.org/attachment.cgi?id=123137&action=edit
partial gallium trace
Attaching the gallium trace (at least up until the crash). I'm still looking
through
v2: use _mm_cmpunord_ps for vIsNaN
---
.../drivers/swr/rasterizer/common/simdintrin.h | 51 --
src/gallium/drivers/swr/rasterizer/core/frontend.h | 8
src/gallium/drivers/swr/rasterizer/core/state.h| 2 -
3 files changed, 55 insertions(+), 6 deletions(-)
diff --
---
src/gallium/drivers/swr/rasterizer/core/threads.cpp | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/swr/rasterizer/core/threads.cpp
b/src/gallium/drivers/swr/rasterizer/core/threads.cpp
index 4b7a207..21bff4e 100644
--- a/src/gallium/dr
Switch boolean template arguments to typename template arguments of type
std::integral_constant.
This allows the template argument unroller to easily be extended to enums.
---
src/gallium/drivers/swr/rasterizer/core/api.cpp| 41 +--
.../drivers/swr/rasterizer/core/frontend.cpp | 12
v2: simplified vIsNaN based on feedback
Tim Rowley (11):
swr: [rasterizer core] Use CS spill/fill size in core
swr: [rasterizer fetch] Add support for fetching non-uniform component
formats
swr: [rasterizer core] Fix thread binding for 32-bit windows
swr: [rasterizer core] Fix global a
Reduces sorting cost
---
src/gallium/drivers/swr/rasterizer/core/arena.h | 68 +++--
1 file changed, 52 insertions(+), 16 deletions(-)
diff --git a/src/gallium/drivers/swr/rasterizer/core/arena.h
b/src/gallium/drivers/swr/rasterizer/core/arena.h
index d0c0123..b80f6f0 100644
- Plus some minor code refactoring
---
src/gallium/drivers/swr/rasterizer/core/arena.h| 88 --
.../drivers/swr/rasterizer/core/backend.cpp| 5 +-
2 files changed, 51 insertions(+), 42 deletions(-)
diff --git a/src/gallium/drivers/swr/rasterizer/core/arena.h
b/src
---
src/gallium/drivers/swr/rasterizer/core/api.cpp | 4 +++-
src/gallium/drivers/swr/rasterizer/core/api.h | 6 --
src/gallium/drivers/swr/rasterizer/core/backend.cpp | 3 +--
src/gallium/drivers/swr/rasterizer/core/context.h | 1 +
4 files changed, 9 insertions(+), 5 deletions(-)
On 21 April 2016 at 22:50, Jason Ekstrand wrote:
> On Thu, Apr 21, 2016 at 6:16 AM, Emil Velikov
> wrote:
>>
>> From: Emil Velikov
>>
>> Rather than parsing through the same files (public headers) twice, tweak
>> the python script to create both files at the same time.
>
>
> Yes, but it takes al
https://bugs.freedesktop.org/show_bug.cgi?id=94955
--- Comment #14 from Bruce Cherniak ---
Created attachment 123136
--> https://bugs.freedesktop.org/attachment.cgi?id=123136&action=edit
gallivm_debug shaders (inline sampler)
I got distracted trying to get tex func to dump disassembly. :-$
See
On 21 April 2016 at 23:05, Jason Ekstrand wrote:
> On Thu, Apr 21, 2016 at 6:16 AM, Emil Velikov
> wrote:
>>
>> From: Emil Velikov
>>
>> I.e do not use -lfoo directly.
>>
>> Signed-off-by: Emil Velikov
>> ---
>> src/intel/vulkan/Makefile.am | 4 +++-
>> 1 file changed, 3 insertions(+), 1 delet
On 20 April 2016 at 03:52, Rob Herring wrote:
> On Tue, Apr 19, 2016 at 8:03 PM, Emil Velikov
> wrote:
>> Hi Rob,
>>
>> Please bear in mind that there's a fair bit of comments, but before
>> all don't mix refactoring and new code. Please ?
>
> Okay.
>
Thanks.
>> On 15 April 2016 at 17:03, Rob
https://bugs.freedesktop.org/show_bug.cgi?id=94955
--- Comment #13 from Roland Scheidegger ---
Actually it is crashing in sampling, but it's a different sampler. Looks like a
TXF, there _might_ be a problem with mip level calculation as it hits a
seldomly used path...
--
You are receiving this
On Thu, Apr 21, 2016 at 8:11 PM, Nicolai Hähnle wrote:
> On 20.04.2016 10:47, Marek Olšák wrote:
>>
>> From: Marek Olšák
>>
>> this will be used in the next commit
>> ---
>> src/gallium/drivers/radeonsi/si_descriptors.c | 27
>> +--
>> 1 file changed, 17 insertions(+),
On Thu, Apr 21, 2016 at 6:16 AM, Emil Velikov
wrote:
> From: Emil Velikov
>
> I.e do not use -lfoo directly.
>
> Signed-off-by: Emil Velikov
> ---
> src/intel/vulkan/Makefile.am | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/src/intel/vulkan/Makefile.am b/src/intel
I had a few comments here and there. In general
Patches 2-3 should be dropped or replaced with a patch that adds a little
documentation.
1, 4 - 16 are
Acked-by: Jason Ekstrand
I have no real opinion on 17-19 but they look fine as far as I'm concerned
I'm not a fan of patch 20
21-23 are also
On Thu, Apr 21, 2016 at 6:16 AM, Emil Velikov
wrote:
> From: Emil Velikov
>
> Rather than parsing through the same files (public headers) twice, tweak
> the python script to create both files at the same time.
>
Yes, but it takes almost zero time to generate them and it's going to run
in parall
From: Robert Foss
Avoid leaking buffer allocated for task if an
error has occured.
Coverity id: 1213929
Signed-off-by: Robert Foss
---
src/gallium/state_trackers/omx/vid_enc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/gallium/state_trackers/omx/vid_enc.c
b/src/gallium/state_trac
From: Robert Foss
Avoid out of bounds access of the array 'src'.
'src' is passed along:
nir_eval_const_opcode()
evaluate_bitfield_insert()
In evaluate_bitfield_insert() an access to src[3] is made
if bit_size==32 wich it always will be due to the
assert(bit_size == 32) on spirv_to_nir.c
On Thu, Apr 21, 2016 at 6:16 AM, Emil Velikov
wrote:
> From: Emil Velikov
>
> Signed-off-by: Emil Velikov
> ---
> src/intel/vulkan/Makefile.am | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/src/intel/vulkan/Makefile.am b/src/intel/vulkan/Makefile.am
> index edd97f4.
On Thu, Apr 21, 2016 at 6:16 AM, Emil Velikov
wrote:
> From: Emil Velikov
>
> Autoconf already does the exact same thing as the manually written rule.
>
> Signed-off-by: Emil Velikov
> ---
>
> IMHO we can/should nuke --with-vulkan-icddir all together and/or
> change it to /usr/share vs /etc (ac
On Thursday, April 21, 2016 10:00:57 AM PDT Iago Toral wrote:
> On Wed, 2016-04-20 at 18:38 -0700, Kenneth Graunke wrote:
> > In commit cda886a4851ab767fba40e8474d6fa8190347e4f, Neil made us stop
> > advertising RGBX formats on Gen9+, as the hardware apparently no longer
> > has working fast clear
On Thu, Apr 21, 2016 at 6:16 AM, Emil Velikov
wrote:
> From: Emil Velikov
>
> Copy/pasta from the rest of mesa, but namely.
>
Mmmm... pasta... Sounds tasty but probably not what you meant.
> - The module should be shared only.
> - We don't need the explicit ".so", as the vulkan loader will
On Thu, Apr 21, 2016 at 8:56 AM, Emil Velikov
wrote:
> On 21 April 2016 at 15:56, Jason Ekstrand wrote:
> >
> > On Apr 21, 2016 7:52 AM, "Erik Faye-Lund" wrote:
> >>
> >> On Thu, Apr 21, 2016 at 3:16 PM, Emil Velikov >
> >> wrote:
> >> > From: Emil Velikov
> >> >
> >> > Signed-off-by: Emil Ve
On Thu, Apr 21, 2016 at 6:16 AM, Emil Velikov
wrote:
> From: Emil Velikov
>
> Signed-off-by: Emil Velikov
> ---
> src/intel/genxml/Makefile.am | 11 +++
> 1 file changed, 11 insertions(+)
>
> diff --git a/src/intel/genxml/Makefile.am b/src/intel/genxml/Makefile.am
> index 77b2f19..f710
https://bugs.freedesktop.org/show_bug.cgi?id=94955
--- Comment #12 from Roland Scheidegger ---
(In reply to Bruce Cherniak from comment #10)
> Does the gallium llvm sampler fully support float textures? Both llvmpipe
> and OpenSWR generate the same sampler and fail identically.
Yes, that's easil
We can use shaders from multiple contexts, and they were not
otherwise locked yet.
v2: Fix the shader = NULL case.
Signed-off-by: Bas Nieuwenhuizen
---
src/gallium/drivers/radeonsi/si_compute.c | 20
src/gallium/drivers/radeonsi/si_state_shaders.c | 13 +++--
On 21 April 2016 at 20:10, Chuck Atkins wrote:
>>> >> Drop the includes altogether, and forward declare the needed symbols.
>>
>>
>> But then you end up with forward declarations of symbols that may not even
>> exist.
>
>
> I guess you'll already have prototypes that will remain unresolved since i
https://bugs.freedesktop.org/show_bug.cgi?id=94955
--- Comment #11 from Bruce Cherniak ---
Created attachment 123134
--> https://bugs.freedesktop.org/attachment.cgi?id=123134&action=edit
tex_sample_func
Here's the ir for the jit'd sampler. I forced "use_tex_func" so it didn't
inline with the
https://bugs.freedesktop.org/show_bug.cgi?id=94955
--- Comment #10 from Bruce Cherniak ---
Does the gallium llvm sampler fully support float textures? Both llvmpipe and
OpenSWR generate the same sampler and fail identically.
I'll attach the sampler ir, if it's useful. Any hints on debugging sa
>
> >> Drop the includes altogether, and forward declare the needed symbols.
>>
>
> But then you end up with forward declarations of symbols that may not even
> exist.
>
I guess you'll already have prototypes that will remain unresolved since if
you're using GLX then you probably won't be linking
>
> >> Drop the includes altogether, and forward declare the needed symbols.
>
But then you end up with forward declarations of symbols that may not even
exist.
> > Why not use the configure.ac-based approach suggested by Chuck?
>
> Few reasons come to mind:
>
> Not to mention that every user
Signed-off-by: Bas Nieuwenhuizen
---
src/gallium/drivers/radeonsi/si_compute.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/gallium/drivers/radeonsi/si_compute.c
b/src/gallium/drivers/radeonsi/si_compute.c
index a99a985..29dbdd8 100644
--- a/src/gallium/drivers/radeonsi/si_compute.c
We can use shaders from multiple contexts, and they were not
otherwise locked yet.
Signed-off-by: Bas Nieuwenhuizen
---
src/gallium/drivers/radeonsi/si_compute.c | 20
src/gallium/drivers/radeonsi/si_state_shaders.c | 12 ++--
2 files changed, 26 insertions(+),
On 21.04.2016 10:58, Marek Olšák wrote:
From: Marek Olšák
this is a follow-up to the RW buffer cleanup.
Any chance you could squash this with the patch in the earlier series
for better bisect-ability of the history? Either way,
Reviewed-by: Nicolai Hähnle
---
src/gallium/drivers/radeo
For the series:
Reviewed-by: Nicolai Hähnle
On 21.04.2016 05:12, Bas Nieuwenhuizen wrote:
We need to enable a bit in the CONTEXT_CONTROL packet for the
loads to work.
v2: Style issues.
Signed-off-by: Bas Nieuwenhuizen
---
src/gallium/drivers/radeonsi/si_descriptors.c | 7 +++
src/gal
On 20.04.2016 23:02, Michel Dänzer wrote:
On 21.04.2016 02:42, Marek Olšák wrote:
On Thu, Apr 14, 2016 at 9:29 AM, Michel Dänzer wrote:
On 14.04.2016 11:37, Michel Dänzer wrote:
On 12.04.2016 21:33, Marek =?UNKNOWN?B?T2zFocOhaw==?= wrote:
URL:
http://cgit.freedesktop.org/mesa/mesa/com
On Tue 19 Apr 2016, Jason Ekstrand wrote:
> On Tue, Apr 19, 2016 at 8:12 PM, Jason Ekstrand
> wrote:
> FYI (for both of you), I've pushed the latest version of the series with
> your review feedback here:
>
> https://cgit.freedesktop.org/~jekstrand/mesa/log/?h=wip/image-load-store-no-gl-v3
>
>
Reviewed-by: Nicolai Hähnle
On 20.04.2016 14:00, Marek Olšák wrote:
From: Marek Olšák
---
src/gallium/drivers/r600/r600_pipe.c | 3 +
src/gallium/drivers/radeon/Makefile.sources | 1 +
src/gallium/drivers/radeon/r600_pipe_common.c | 2 +
src/gallium/drivers/radeon/r600_p
On Sat 16 Apr 2016, Jason Ekstrand wrote:
> This lets us delete some redundant code and keep all of the
> image_load_store format lowering logic in one place: libisl.
> ---
> src/mesa/drivers/dri/i965/brw_context.h | 2 -
> src/mesa/drivers/dri/i965/brw_surface_formats.c | 109
> -
On 21 April 2016 at 18:44, Mircea Gherzan wrote:
>>> +#ifdef MESA_EGL_NO_X11_HEADERS
>>> +#include
>>> +#else
>>> #include
>>> +#endif
>>> +
>>> #include
>>>
>> Drop the includes altogether, and forward declare the needed symbols.
>
>
> Why not use the configure.ac-based approach suggested b
On Sat 16 Apr 2016, Jason Ekstrand wrote:
> ---
> .../drivers/dri/i965/brw_fs_surface_builder.cpp| 118
> +
> 1 file changed, 52 insertions(+), 66 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_surface_builder.cpp
> b/src/mesa/drivers/dri/i965/brw_fs_surf
Nice cleanup. Patches 1, 3-10 are:
Reviewed-by: Nicolai Hähnle
On 20.04.2016 10:47, Marek Olšák wrote:
From: Marek Olšák
const buffers are no longer used since the clip plane const buffer was
moved to RW buffers
---
src/gallium/drivers/radeonsi/si_shader.c | 4 ++--
src/gallium/drivers/ra
On Sat 16 Apr 2016, Jason Ekstrand wrote:
> ---
> .../drivers/dri/i965/brw_fs_surface_builder.cpp| 55
> ++
> 1 file changed, 55 insertions(+)
Patch 12 is
Reviewed-by: Chad Versace
___
mesa-dev mailing list
mesa-dev@lists.free
On Sat 16 Apr 2016, Jason Ekstrand wrote:
> Previously, we were relying on has_matching_typed_format returning true for
> MESA_FORMAT_NONE which, in turn, relied on _mesa_get_format_bytes returning
> 1 for MESA_FORMAT_NONE. When we switch to ISL, this behaviour will no
> longer be something we can
On 20.04.2016 10:47, Marek Olšák wrote:
From: Marek Olšák
this will be used in the next commit
---
src/gallium/drivers/radeonsi/si_descriptors.c | 27 +--
1 file changed, 17 insertions(+), 10 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c
b/
On 21.04.2016 07:49, Bas Nieuwenhuizen wrote:
On Wed, Apr 20, 2016 at 5:47 PM, Marek Olšák wrote:
From: Marek Olšák
---
src/gallium/drivers/radeonsi/si_descriptors.c | 50 +--
src/gallium/drivers/radeonsi/si_pipe.h| 2 +-
2 files changed, 25 insertions(+
On Thu, Apr 21, 2016 at 8:03 PM, Nicolai Hähnle wrote:
> On 21.04.2016 10:42, Bas Nieuwenhuizen wrote:
>>
>> Does not implement dumping info.
>
>
> Why not?
I primarily wrote this series to make ddebug not crash when used with
compute, so I
haven't really looked at what It should dump.
- Bas
>
Reviewed-by: Nicolai Hähnle
On 21.04.2016 10:42, Bas Nieuwenhuizen wrote:
Signed-off-by: Bas Nieuwenhuizen
---
src/gallium/drivers/ddebug/dd_screen.c | 12
1 file changed, 12 insertions(+)
diff --git a/src/gallium/drivers/ddebug/dd_screen.c
b/src/gallium/drivers/ddebug/dd_scr
On 21.04.2016 10:42, Bas Nieuwenhuizen wrote:
Does not implement dumping info.
Why not?
Signed-off-by: Bas Nieuwenhuizen
---
src/gallium/drivers/ddebug/dd_draw.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/src/gallium/drivers/ddebug/dd_draw.c
b/src
On 21.04.2016 10:42, Bas Nieuwenhuizen wrote:
Note that compute states have a different struct than
the other shader states, so we cannot reuse the macro.
Couldn't you still share bind and delete? This requires dealing with the
possibility of not having TGSI, but that'll be useful for graphics
"LLVN" typo in the subject line. Apart from that,
Reviewed-by: Nicolai Hähnle
On 21.04.2016 08:37, Emil Velikov wrote:
Missed with commit 100796c15c3 "gallium/radeon: drop support for LLVM
3.5"
Cc: Marek Olšák
Cc: Nicolai Hähnle
Signed-off-by: Emil Velikov
---
src/gallium/drivers/radeon/
On 21.04.2016 09:14, Bas Nieuwenhuizen wrote:
On Wed, Apr 20, 2016 at 8:33 AM, wrote:
On 2016-04-20 11:46, Nicolai Hähnle wrote:
On 19.04.2016 17:50, Bas Nieuwenhuizen wrote:
Signed-off-by: Bas Nieuwenhuizen
---
src/gallium/drivers/radeonsi/si_compute.c | 5 -
src/gallium
On 21-Apr-16 4:08 PM, Emil Velikov wrote:
On 20 April 2016 at 16:52, Mircea Gherzan wrote:
This header should not blindly include the GLX and should also
conditionally define functions that use GLX parameters. The
MESA_EGL_NO_X11_HEADERS macro is used to check if we're building without
GLX supp
On Thu, Apr 21, 2016 at 1:15 AM, Iago Toral wrote:
> On Wed, 2016-04-20 at 14:22 -0700, Matt Turner wrote:
>> This reverts commit b449366587b5f3f64c6fb45fe22c39e4bc8a4309.
>>
>> I removed the pass thinking that it was now not useful, but that was not
>> true. I believe I ran shader-db on HSW and s
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