[Mesa-dev] r600g,radeonsi: ARB_query_buffer_object grunt work

These two patches provide just the grunt work for ARB_query_buffer_object support. My incomplete hardware specific callback has been left out of this series. However this does allow a user to fake the PIPE_CAP and not just get a segfault from a unchecked derefenced to a NULL pointer from within 'st

[Mesa-dev] [PATCH 2/2] radeon: Implement the get_query_result_resource() call-in site

Implement the frontend part of the ARB_query_buffer_object gallium callback into the driver query_ops. Signed-off-by: Edward O'Callaghan --- src/gallium/drivers/radeon/r600_query.c | 19 +++ 1 file changed, 19 insertions(+) diff --git a/src/gallium/drivers/radeon/r600_query.c b

[Mesa-dev] [PATCH 1/2] radeon: Provision a query_ops callback, get_query_result_resource()

ARB_query_buffer_object requires us to provide a query_ops callback for statistics about the operation in the OpenGL pipeline. Signed-off-by: Edward O'Callaghan --- src/gallium/drivers/radeon/r600_query.h | 5 + 1 file changed, 5 insertions(+) diff --git a/src/gallium/drivers/radeon/r600_qu

Re: [Mesa-dev] [PATCH 1/2] dri/i965: extend GLES3 sRGB workaround to cover all byte orders

On Wed, Apr 6, 2016 at 10:35 PM, Haixia Shi wrote: > I am afraid that I am not the original author of the > gles3_srgb_workaround, and from the comments it appears to only apply for > argb formats, so I am not sure if extending it to all other formats would > cause behavioral regression. > On Apr

Re: [Mesa-dev] [PATCH v2] glsl: handle unsigned int wraparound in link_shaders()

Pushed thanks! ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH] mesa: enable ARB_explicit_uniform_location for swrast

This is untested but since ARB_explicit_attrib_location is enabled there should be no problem enabling this also. --- src/mesa/main/extensions.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mesa/main/extensions.c b/src/mesa/main/extensions.c index fa50cb6..a889902 100644 --- a/src/mesa/

Re: [Mesa-dev] [PATCH 2/4] nir: Silence unused "options" warning in algebraic passes.

Quoting Dylan Baker (2016-04-08 14:54:38) > Quoting Kenneth Graunke (2016-04-08 11:48:01) > > On Friday, April 8, 2016 11:18:46 AM PDT Dylan Baker wrote: > > > > Quoting Eduardo Lima Mitev (2016-04-08 08:26:22) > > > > On 04/08/2016 01:35 AM, Kenneth Graunke wrote: > > > > > Some passes may not re

Re: [Mesa-dev] [PATCH 1/5] include/GL: add mesa_glinterop.h for OpenGL-OpenCL interop (v3)

On Fri, Apr 1, 2016 at 2:13 PM, Emil Velikov wrote: > On 16 March 2016 at 10:40, Marek Olšák wrote: > >> "offset_after" isn't nasty. :) Yeah, I was inspired by other APIs I >> had seen. The sizes make even more sense when they are function >> parameters, because the caller can just do: >> (sizeof

Re: [Mesa-dev] [PATCH] nir: remove duplicate Makefile.sources

On Fri, Apr 8, 2016 at 4:37 AM, Jose Fonseca wrote: > On 02/04/16 19:35, Rob Clark wrote: >> >> From: Rob Clark >> >> Allegedly this was needed still by scons build.. but in practice it >> doesn't seem to be needed. Removing it and running 'scons' results >> in no build errors. >> >> Signed-off-

[Mesa-dev] [PATCH 7/7] gallium/radeon: remove R600_QUERY_HW_FLAG_TIMER

From: Marek Olšák not used anymore --- src/gallium/drivers/r600/r600_hw_context.c| 2 +- src/gallium/drivers/radeon/r600_perfcounter.c | 1 - src/gallium/drivers/radeon/r600_query.c | 4 +--- src/gallium/drivers/radeon/r600_query.h | 3 +-- 4 files changed, 3 insertions(+), 7 del

[Mesa-dev] [PATCH 6/7] gallium/radeon: merge timer and non-timer query lists

From: Marek Olšák All of them are paused only between IBs. --- src/gallium/drivers/r600/r600_hw_context.c| 3 +- src/gallium/drivers/radeon/r600_pipe_common.c | 18 ++-- src/gallium/drivers/radeon/r600_pipe_common.h | 19 +++- src/gallium/drivers/radeon/r600_query.c | 65 +

[Mesa-dev] [PATCH 1/7] gallium/radeon: move pipeline stat context flags to common code

From: Marek Olšák --- src/gallium/drivers/radeon/r600_pipe_common.h | 5 - src/gallium/drivers/radeonsi/si_pipe.h| 3 --- src/gallium/drivers/radeonsi/si_state.c | 8 src/gallium/drivers/radeonsi/si_state_draw.c | 4 ++-- 4 files changed, 10 insertions(+), 10 deletion

[Mesa-dev] [PATCH] r600g: fix typo in r600 register definitions

From: Marek Olšák --- src/gallium/drivers/r600/r600d.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/r600/r600d.h b/src/gallium/drivers/r600/r600d.h index 3d223ed..ef99573 100644 --- a/src/gallium/drivers/r600/r600d.h +++ b/src/gallium/drivers/r600/r600d

[Mesa-dev] [PATCH 5/7] r600g: don't manually stop queries for blitter

From: Marek Olšák r600_set_active_query_state does it better. --- src/gallium/drivers/r600/r600_blit.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/gallium/drivers/r600/r600_blit.c b/src/gallium/drivers/r600/r600_blit.c index c52d5a9..7ddd4fa 100644 --- a/src/gallium/drivers/r600/r

[Mesa-dev] [PATCH 3/7] r600g: implement set_active_query_state for pausing occlusion queries

From: Marek Olšák Use ZPASS_INCREMENT_DISABLE everywhere. --- src/gallium/drivers/r600/evergreen_state.c | 5 - src/gallium/drivers/r600/evergreend.h| 2 +- src/gallium/drivers/r600/r600_pipe.h | 1 + src/gallium/drivers/r600/r600_state.c| 6 +- src/gallium/

[Mesa-dev] [PATCH 2/7] r600g: simplify r600_set_occlusion_query_state

From: Marek Olšák The caller does the same checking. --- src/gallium/drivers/r600/evergreen_state.c | 2 +- src/gallium/drivers/r600/r600_pipe.h | 1 - src/gallium/drivers/r600/r600_state.c| 2 +- src/gallium/drivers/r600/r600_state_common.c | 5 + 4 files changed, 3 insert

[Mesa-dev] [PATCH 4/7] r600g: add pausing pipeline & streamout queries into set_active_query_state

From: Marek Olšák --- src/gallium/drivers/r600/evergreen_state.c | 12 src/gallium/drivers/r600/r600_hw_context.c | 10 ++ src/gallium/drivers/r600/r600_pipe.h | 2 +- src/gallium/drivers/r600/r600_state.c| 6 ++ src/gallium/drivers/r600/r600_state_

Re: [Mesa-dev] [PATCH 2/2] Remove fs-discard-exit-3

BTW, Talos Principle had a bug that it calculated derivatives after discard, which is undefined on radeonsi if it results in non-uniform control flow. Then, somebody reported the bug to them, and they fixed it. I have to say that rarely do we find a test that quotes the spec and expects the exact

Re: [Mesa-dev] [PATCH 4/4] i965: Port INTEL_PRECISE_TRIG=1 to NIR.

On Fri, Apr 8, 2016 at 9:36 AM, Eduardo Lima Mitev wrote: > On 04/08/2016 01:35 AM, Kenneth Graunke wrote: > >> This makes the extra multiply visible to NIR's algebraic optimizations >> (for constant reassociation) as well as constant folding. This means >> that when the result of sin/cos are mu

Re: [Mesa-dev] [PATCH 1/4] nir: Do basic constant reassociation.

On Fri, Apr 8, 2016 at 8:21 AM, Eduardo Lima Mitev wrote: > On 04/08/2016 01:35 AM, Kenneth Graunke wrote: > >> Many shaders contain expression trees of the form: >> >> const_1 * (value * const_2) >> >> Reorganizing these to >> >> (const_1 * const_2) * value >> >> will allow constant fo

Re: [Mesa-dev] [PATCH 2/2] Remove fs-discard-exit-3

Marek Olšák writes: > From: Marek Olšák > > The test is wrong and the GLSL 1.30 citation in the test states very > clearly that discard can cause non-uniform control flow for any code that > follows. Heh, IIRC I sent this exact same patch over a year ago but I didn't get particularly enthusiast

Re: [Mesa-dev] [PATCH 2/4] nir: Silence unused "options" warning in algebraic passes.

Quoting Kenneth Graunke (2016-04-08 11:48:01) > On Friday, April 8, 2016 11:18:46 AM PDT Dylan Baker wrote: > > > Quoting Eduardo Lima Mitev (2016-04-08 08:26:22) > > > On 04/08/2016 01:35 AM, Kenneth Graunke wrote: > > > > Some passes may not refer to options->..., at which point the compiler > >

[Mesa-dev] [PATCH 2/3] i965/disasm: Decode "channel mask present" bit correctly.

Bit 15 means "interleave" for most messages, but for SIMD8 messages it means "use channel masks". Signed-off-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_disasm.c | 19 +++ 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_disas

[Mesa-dev] [PATCH 1/3] i965/disasm: Simplify the URB opcode printing with ?:.

Signed-off-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_disasm.c | 13 ++--- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c b/src/mesa/drivers/dri/i965/brw_disasm.c index 09eb239..0ae237d 100644 --- a/src/mesa/drivers/dri/i96

[Mesa-dev] [PATCH 3/3] i965/disasm: Decode per-slot offsets.

We just never bothered to decode this. Signed-off-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_disasm.c | 5 + 1 file changed, 5 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c b/src/mesa/drivers/dri/i965/brw_disasm.c index 0848657..88bd7a4 100644 --- a/src/mesa/

Re: [Mesa-dev] [PATCH 05/16] nir: add lowering pass for glBitmap

Rob Clark writes: > From: Rob Clark > > Signed-off-by: Rob Clark > Reviewed-by: Connor Abbott > --- > src/compiler/Makefile.sources | 1 + > src/compiler/nir/nir.h | 7 ++ > src/compiler/nir/nir_lower_bitmap.c | 166 > > 3 files cha

Re: [Mesa-dev] [PATCH 07/16] nir: passthrough-edgeflags support

Rob Clark writes: > From: Rob Clark > > Handled by tgsi_emulate for glsl->tgsi case. > > Signed-off-by: Rob Clark > Reviewed-by: Connor Abbott > --- > src/compiler/Makefile.sources | 1 + > src/compiler/nir/nir.h | 2 + > src/compiler/nir/nir

Re: [Mesa-dev] Merging the Vulkan driver

Jason Ekstrand writes: > All, > > We are getting very close to being able to merge the Vulkan driver into > mesa master. I've got around 30 patches on the mailing list that are still > awaiting review. Once those get merged, the diff between the "vulkan" and > "master" branches is basically zer

Re: [Mesa-dev] [PATCH v2 00/15] i965: Rework uniform handling in the back-end

On Thu, Apr 7, 2016 at 10:01 PM, Matt Turner wrote: > On Tue, Mar 22, 2016 at 3:33 PM, Jason Ekstrand > wrote: > > This is mostly a re-send of a patch series I've had floating around in > one > > form or a while for quite some time. It's basically the same except that > > the original version w

Re: [Mesa-dev] [PATCH 3/3] i965/tiled_memoyp: Get rid of the direction parameter to get_memcpy

On Thu, Apr 7, 2016 at 4:57 PM, Matt Turner wrote: > On Thu, Apr 7, 2016 at 1:56 PM, Jason Ekstrand > wrote: > > Now that we can use the much simpler rgba8_copy function, we don't need > to > > hand different functions out based on direction. > > --- > > Typo in the subject, and PATCH 2/3 needs

Re: [Mesa-dev] [PATCH 2/4] nir: Silence unused "options" warning in algebraic passes.

On Friday, April 8, 2016 11:18:46 AM PDT Dylan Baker wrote: > Quoting Eduardo Lima Mitev (2016-04-08 08:26:22) > > On 04/08/2016 01:35 AM, Kenneth Graunke wrote: > > > Some passes may not refer to options->..., at which point the compiler > > > will warn about an unused variable. Just cast to voi

Re: [Mesa-dev] [PATCH 2/4] nir: Silence unused "options" warning in algebraic passes.

Quoting Eduardo Lima Mitev (2016-04-08 08:26:22) > On 04/08/2016 01:35 AM, Kenneth Graunke wrote: > > Some passes may not refer to options->..., at which point the compiler > > will warn about an unused variable. Just cast to void unconditionally > > to shut it up. > > > > Signed-off-by: Kenneth G

Re: [Mesa-dev] [PATCH 3/3] i965/tiled_memoyp: Get rid of the direction parameter to get_memcpy

On 04/07/2016 01:56 PM, Jason Ekstrand wrote: > Now that we can use the much simpler rgba8_copy function, we don't need to > hand different functions out based on direction. > --- > src/mesa/drivers/dri/i965/intel_pixel_read.c | 3 +-- > src/mesa/drivers/dri/i965/intel_tex_image.c| 3 +-- >

Re: [Mesa-dev] [PATCH] radeon/uvd: alignment fix for decode message buffer

Cc: On 04/08/2016 11:34 AM, Boyuan Zhang wrote: Signed-off-by: Boyuan Zhang Reviewed-by: Christian König --- src/gallium/drivers/radeon/radeon_uvd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeon/radeon_uvd.c b/src/gallium/drivers/radeon/rad

Re: [Mesa-dev] [PATCH 4/4] i965: Port INTEL_PRECISE_TRIG=1 to NIR.

On 04/08/2016 01:35 AM, Kenneth Graunke wrote: This makes the extra multiply visible to NIR's algebraic optimizations (for constant reassociation) as well as constant folding. This means that when the result of sin/cos are multiplied by an constant, we can eliminate the extra multiply altogether

Re: [Mesa-dev] [Nouveau] [PATCH] nouveau: codegen: Take src swizzle into account on loads

On Fri, Apr 8, 2016 at 12:26 PM, Hans de Goede wrote: > Hi, > > > On 08-04-16 18:06, Hans de Goede wrote: >> >> Hi, >> >> On 08-04-16 17:45, Ilia Mirkin wrote: >>> >>> On Fri, Apr 8, 2016 at 11:28 AM, Hans de Goede >>> wrote: When dealing with non vector variables the llvm register allo

Re: [Mesa-dev] [Nouveau] [PATCH] nouveau: codegen: Take src swizzle into account on loads

Hi, On 08-04-16 18:06, Hans de Goede wrote: Hi, On 08-04-16 17:45, Ilia Mirkin wrote: On Fri, Apr 8, 2016 at 11:28 AM, Hans de Goede wrote: When dealing with non vector variables the llvm register allocator will use TEMP[0].x then TEMP[0].y, etc. When loading something from a global buffer

Re: [Mesa-dev] [PATCH mesa v2 1/2] nouveau: codegen: Use FILE_MEMORY_BUFFER for buffers

On 04/08/2016 12:17 PM, Hans de Goede wrote: Hi, On 23-03-16 23:10, Samuel Pitoiset wrote: Are you sure this won't break compute shaders on fermi? Could you please double-check that? I just checked: lspci: 01:00.0 VGA compatible controller: NVIDIA Corporation GF119 [GeForce GT 610] (rev a1

Re: [Mesa-dev] [PATCH] nouveau: codegen: Take src swizzle into account on loads

Hi, On 08-04-16 17:45, Ilia Mirkin wrote: On Fri, Apr 8, 2016 at 11:28 AM, Hans de Goede wrote: When dealing with non vector variables the llvm register allocator will use TEMP[0].x then TEMP[0].y, etc. When loading something from a global buffer it will calculate the address to use, and stor

Re: [Mesa-dev] [PATCH] nouveau: codegen: Take src swizzle into account on loads

On Fri, Apr 8, 2016 at 11:28 AM, Hans de Goede wrote: > When dealing with non vector variables the llvm register allocator > will use TEMP[0].x then TEMP[0].y, etc. > > When loading something from a global buffer it will calculate the > address to use, and store that in say TEMP[0].x, so it ends u

[Mesa-dev] [PATCH] radeon/uvd: alignment fix for decode message buffer

Signed-off-by: Boyuan Zhang Reviewed-by: Christian König --- src/gallium/drivers/radeon/radeon_uvd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeon/radeon_uvd.c b/src/gallium/drivers/radeon/radeon_uvd.c index 233f460..098baf2 100644 --- a/src/gall

Re: [Mesa-dev] [PATCH 2/4] nir: Silence unused "options" warning in algebraic passes.

On 04/08/2016 01:35 AM, Kenneth Graunke wrote: Some passes may not refer to options->..., at which point the compiler will warn about an unused variable. Just cast to void unconditionally to shut it up. Signed-off-by: Kenneth Graunke --- src/compiler/nir/nir_algebraic.py | 1 + 1 file chang

Re: [Mesa-dev] [PATCH] nouveau: codegen: Take src swizzle into account on loads

Hi, On 08-04-16 17:02, Ilia Mirkin wrote: On Fri, Apr 8, 2016 at 5:27 AM, Hans de Goede wrote: Hi, On 07-04-16 15:58, Ilia Mirkin wrote: That's wrong. It used to work with the old RES[] code and if one cannot specify a source swizzle, then how can I do something like LOAD TEMP[0].y, MEM

Re: [Mesa-dev] [PATCH 1/4] nir: Do basic constant reassociation.

On 04/08/2016 01:35 AM, Kenneth Graunke wrote: Many shaders contain expression trees of the form: const_1 * (value * const_2) Reorganizing these to (const_1 * const_2) * value will allow constant folding to combine the constants. Sometimes, these constants are 2 and 0.5, so we can

Re: [Mesa-dev] [PATCH v2 00/15] i965: Rework uniform handling in the back-end

On Apr 7, 2016 11:08 PM, "Jason Ekstrand" wrote: > > > On Apr 7, 2016 10:01 PM, "Matt Turner" wrote: > > > > On Tue, Mar 22, 2016 at 3:33 PM, Jason Ekstrand wrote: > > > This is mostly a re-send of a patch series I've had floating around in one > > > form or a while for quite some time. It's ba

Re: [Mesa-dev] [PATCH] nouveau: codegen: Take src swizzle into account on loads

On Fri, Apr 8, 2016 at 5:27 AM, Hans de Goede wrote: > Hi, > > On 07-04-16 15:58, Ilia Mirkin wrote: >> >> That's wrong. > > > It used to work with the old RES[] code and if one cannot specify > a source swizzle, then how can I do something like > > LOAD TEMP[0].y, MEMORY[0], address > > And get t

Re: [Mesa-dev] [PATCH] nir: remove duplicate Makefile.sources

On Fri, Apr 8, 2016 at 4:37 AM, Jose Fonseca wrote: > On 02/04/16 19:35, Rob Clark wrote: >> >> From: Rob Clark >> >> Allegedly this was needed still by scons build.. but in practice it >> doesn't seem to be needed. Removing it and running 'scons' results >> in no build errors. >> >> Signed-off-

[Mesa-dev] [PATCH v2] glsl: handle unsigned int wraparound in link_shaders()

NOTE: someone with access will need to commit this afer the review process v2: change check_explicit_uniform_locations() to return an unsigned 0 (Timothy Arceri) We were storing the int result of check_explicit_uniform_locations() in num_explicit_uniform_locs as an unsigned int which ca

Re: [Mesa-dev] [PATCH] nouveau: codegen: Take src swizzle into account on loads

Ah, I may have read over your commit too hastily. Will have another look. On Apr 8, 2016 5:27 AM, "Hans de Goede" wrote: > Hi, > > On 07-04-16 15:58, Ilia Mirkin wrote: > >> That's wrong. >> > > It used to work with the old RES[] code and if one cannot specify > a source swizzle, then how can I d

Re: [Mesa-dev] [PATCH] glsl: handle unsigned int wraparound in link_shaders()

Agreed, I didn't see that check_explicit_uniform_locations() was only used in link_shaders(). I will submit a v2 with those changes. On Thu, Apr 7, 2016 at 11:24 PM, Timothy Arceri < timothy.arc...@collabora.com> wrote: > On Thu, 2016-04-07 at 11:22 -0400, Lars Hamre wrote: > > NOTES: > > * Repos

Re: [Mesa-dev] [PATCH] radeonsi: fix mask checking when emitting scissors and viewports

On Fri, Apr 8, 2016 at 12:16 PM, wrote: > On 2016-04-08 19:00, Marek Olšák wrote: >> >> From: Marek Olšák >> >> --- >> src/gallium/drivers/radeonsi/si_state.c | 12 >> 1 file changed, 8 insertions(+), 4 deletions(-) >> >> diff --git a/src/gallium/drivers/radeonsi/si_state.c >> b/sr

Re: [Mesa-dev] [android-x86-devel] Re: gralloc_drm_pipe

2016-04-07 13:30 GMT+08:00 Rob Herring : > On Wed, Apr 6, 2016 at 11:12 AM, Chih-Wei Huang > wrote: > >> I guess the first supported GPU is virgl. Right? > > Yes. Any gallium driver really. The classic mesa drivers will need > their own additions for GBM map/unmap. > >> When could we expect it's

Re: [Mesa-dev] [PATCH] radeonsi: implement and rely on set_active_query_state

Reviewed-by: Edward O'Callaghan On 2016-04-08 18:58, Marek Olšák wrote: From: Marek Olšák --- src/gallium/drivers/radeonsi/si_blit.c | 3 --- src/gallium/drivers/radeonsi/si_pipe.h | 4 src/gallium/drivers/radeonsi/si_state.c | 32 +++- src/g

Re: [Mesa-dev] [PATCH mesa v2 1/2] nouveau: codegen: Use FILE_MEMORY_BUFFER for buffers

Hi, On 23-03-16 23:10, Samuel Pitoiset wrote: Are you sure this won't break compute shaders on fermi? Could you please double-check that? I just checked: lspci: 01:00.0 VGA compatible controller: NVIDIA Corporation GF119 [GeForce GT 610] (rev a1) Before this patch-set: [hans@plank piglit]$

Re: [Mesa-dev] [PATCH] radeonsi: fix mask checking when emitting scissors and viewports

On 2016-04-08 19:00, Marek Olšák wrote: From: Marek Olšák --- src/gallium/drivers/radeonsi/si_state.c | 12 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 8087d23..3894e1d 100644

Re: [Mesa-dev] [PATCH] gallium/radeon: unify checking streamout enable state

Reviewed-by: Edward O'Callaghan On 2016-04-08 19:00, Marek Olšák wrote: From: Marek Olšák --- src/gallium/drivers/r600/r600_state_common.c | 5 ++--- src/gallium/drivers/radeon/r600_pipe_common.h | 6 ++ src/gallium/drivers/radeon/r600_streamout.c | 6 -- src/gallium/drivers/radeo

Re: [Mesa-dev] [PATCH] nouveau: codegen: Take src swizzle into account on loads

Hi, On 07-04-16 15:58, Ilia Mirkin wrote: That's wrong. It used to work with the old RES[] code and if one cannot specify a source swizzle, then how can I do something like LOAD TEMP[0].y, MEMORY[0], address And get the data at absolute global memory address "address" into TEMP[0].y ? This

[Mesa-dev] [PATCH] radeonsi: fix mask checking when emitting scissors and viewports

From: Marek Olšák --- src/gallium/drivers/radeonsi/si_state.c | 12 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 8087d23..3894e1d 100644 --- a/src/gallium/drivers/radeonsi/si_st

[Mesa-dev] [PATCH] gallium/radeon: unify checking streamout enable state

From: Marek Olšák --- src/gallium/drivers/r600/r600_state_common.c | 5 ++--- src/gallium/drivers/radeon/r600_pipe_common.h | 6 ++ src/gallium/drivers/radeon/r600_streamout.c | 6 -- src/gallium/drivers/radeonsi/si_state_draw.c | 3 +-- 4 files changed, 9 insertions(+), 11 deletions

Re: [Mesa-dev] [PATCH 1/3] i965: Extract SSEU configuration info

On Thursday, April 7, 2016 10:53:12 AM PDT Ben Widawsky wrote: > Signed-off-by: Ben Widawsky > --- > src/mesa/drivers/dri/i965/intel_screen.c | 35 ++ +- > 1 file changed, 21 insertions(+), 14 deletions(-) Thanks for taking care of this. Series is: Reviewed-by: Kenne

[Mesa-dev] [PATCH] radeonsi: implement and rely on set_active_query_state

From: Marek Olšák --- src/gallium/drivers/radeonsi/si_blit.c | 3 --- src/gallium/drivers/radeonsi/si_pipe.h | 4 src/gallium/drivers/radeonsi/si_state.c | 32 +++- src/gallium/drivers/radeonsi/si_state_draw.c | 10 + 4 files changed, 45 in

[Mesa-dev] [PATCH 1/2] arb_shader_image_size/builtin: don't report subtests that are never run

From: Marek Olšák this removes a lot of skipped subtests from results --- tests/spec/arb_shader_image_size/builtin.c | 20 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/tests/spec/arb_shader_image_size/builtin.c b/tests/spec/arb_shader_image_size/builtin.c

[Mesa-dev] [PATCH 2/2] Remove fs-discard-exit-3

From: Marek Olšák The test is wrong and the GLSL 1.30 citation in the test states very clearly that discard can cause non-uniform control flow for any code that follows. --- .../execution/fs-discard-exit-3.shader_test| 76 -- 1 file changed, 76 deletions(-) delete mo

Re: [Mesa-dev] [PATCH] nir: remove duplicate Makefile.sources

On 02/04/16 19:35, Rob Clark wrote: From: Rob Clark Allegedly this was needed still by scons build.. but in practice it doesn't seem to be needed. Removing it and running 'scons' results in no build errors. Signed-off-by: Rob Clark --- So, afaict NIR is not even built w/ scons build (I'm jus

Re: [Mesa-dev] [PATCH 3/4] i965: Pass brw_compiler into brw_preprocess_nir() instead of is_scalar.

LGTM, Reviewed-by: Alejandro Piñeiro On 08/04/16 01:35, Kenneth Graunke wrote: > I want to be able to read other fields. > > Signed-off-by: Kenneth Graunke > --- > src/mesa/drivers/dri/i965/brw_nir.c | 6 -- > src/mesa/drivers/dri/i965/brw_nir.h | 3 ++- > 2 files changed, 6 insertions(+),

Re: [Mesa-dev] [PATCH] st/mesa: fix glReadBuffer() assertion failure

On 08/04/16 00:45, Brian Paul wrote: If the first call in a GL app is glReadPixels(GL_FRONT) we'd fail the assert(st->ctx->FragmentProgram._Current) at st_atom_shader.c:114 in update_fp(). This is because we were calling st_validate_state() without first updating Mesa state with _mesa_update_sta