Re: [Mesa-dev] [PATCH] radeonsi: enable denorms for 64-bit and 16-bit floats

> On Feb 8, 2016, at 12:38, Marek Olšák wrote: > >> >> We should tell the compiler we are enabling fp-64 denorms by adding >> +fp64-denormals to the feature string. It would also be better to >> read the float_mode value from the config registers emitted by the >> compiler. > > Yes, I agree,

Re: [Mesa-dev] [PATCH] [v2] i965: Make sure we blit a full compressed block

On Sat, Feb 6, 2016 at 6:11 PM, Ben Widawsky wrote: > This fixes an assertion failure in [at least] one of the Unreal Engine > Linux > demo/games that uses DXT1 compression. Specifically, the "Vehicle Game". > > At some point, the game ends up trying to blit mip level whose size is 2x2, > which i

[Mesa-dev] [Bug 94040] clGetPlatformIDs causes futex race condition

https://bugs.freedesktop.org/show_bug.cgi?id=94040 --- Comment #8 from Francisco Jerez --- (In reply to bob from comment #7) > In the specific case of blender, there are 31 hung up threads with around 9 > each waiting on > > __lll_lock_wait () at ../sysdeps/unix/sysv/linux/x86_64/lowlevellock.S:

[Mesa-dev] [Bug 94040] clGetPlatformIDs causes futex race condition

https://bugs.freedesktop.org/show_bug.cgi?id=94040 --- Comment #7 from b...@bob131.so --- In the specific case of blender, there are 31 hung up threads with around 9 each waiting on __lll_lock_wait () at ../sysdeps/unix/sysv/linux/x86_64/lowlevellock.S:135 pthread_cond_wait@@GLIBC_2.3.2 () at ../

Re: [Mesa-dev] [PATCH] [v2] i965: Make sure we blit a full compressed block

On Sat, Feb 6, 2016 at 6:11 PM, Ben Widawsky wrote: > This fixes an assertion failure in [at least] one of the Unreal Engine Linux > demo/games that uses DXT1 compression. Specifically, the "Vehicle Game". > > At some point, the game ends up trying to blit mip level whose size is 2x2, > which is s

Re: [Mesa-dev] [PATCH 4/7] mesa: remove check_compatible() in make_current

On 02/05/2016 01:11 PM, Miklós Máté wrote: > this was marked for removal since 2007 > ctx::Visual is also removed, since this was its only legit user > --- > .../drivers/dri/radeon/radeon_common_context.c | 2 +- > src/mesa/main/blend.c | 4 +- > src/mesa/main/bl

Re: [Mesa-dev] [PATCH] mesa: rewrite save_CallLists() code

On 02/08/2016 06:25 PM, Ian Romanick wrote: On 02/08/2016 05:06 PM, Brian Paul wrote: When glCallLists() is compiled into a display list, preserve the call as a single glCallLists rather than 'n' glCallList calls. This will matter for an upcoming display list optimization project. I think thi

Re: [Mesa-dev] [PATCH v2] workarounds: Update workaround names and platforms

On Fri, Feb 05, 2016 at 01:59:23PM -0800, Sameer Kibey wrote: > Update the format in which workarounds are documented > in the source code. This allows mesa to be parsed > by the list-workarounds utility in intel-gpu-tools. > > Signed-off-by: Sameer Kibey > --- > changed byt to vlv for consistenc

[Mesa-dev] Request for someone who understands viewports, clip control, etc

https://bugs.freedesktop.org/show_bug.cgi?id=93813 Can someone who *actually* understands what's going on rule on this one way or the other? I've tried to catch people's attention on IRC, but unsuccessfully. If this is a real bug, seems like a very bad one... -ilia _

Re: [Mesa-dev] [PATCH v3] i965/blorp: Fix hiz ops on MSAA surfaces

On 2016-02-06 10:25:59, Ben Widawsky wrote: > On Sat, Feb 06, 2016 at 12:01:50PM +0100, Alejandro Piñeiro wrote: > > From: Chris Forbes > > > > Two things were broken here: > > - The depth/stencil surface dimensions were broken for MSAA. > > - Sample count was programmed incorrectly. > > > > Res

Re: [Mesa-dev] [PATCH] mesa: rewrite save_CallLists() code

On 02/08/2016 05:06 PM, Brian Paul wrote: > When glCallLists() is compiled into a display list, preserve the call > as a single glCallLists rather than 'n' glCallList calls. This will > matter for an upcoming display list optimization project. I think this code is generally better than what was h

Re: [Mesa-dev] [PATCH] mesa: add missing error check in _mesa_CallLists()

On 02/08/2016 05:06 PM, Brian Paul wrote: > Generate GL_INVALID_VALUE if n < 0. Return early if n==0 or lists==NULL. > > v2: fix formatting, also check for lists==NULL. You were correct that I was looking at save_CallLists before. Reviewed-by: Ian Romanick > --- > src/mesa/main/dlist.c | 8 +

Re: [Mesa-dev] [PATCH 6/7] glx: remove incorrect refcounting of DRIdrawable

On 02/05/2016 01:11 PM, Miklós Máté wrote: > dri drawables must never be released when unbound from a context > as long as their corresponding glx objects (window, pixmap, pbuffer) > still exist I'd really like to have Kristian weigh in, since DRI2 was his design, and this is all his code being af

[Mesa-dev] [PATCH] mesa: rewrite save_CallLists() code

When glCallLists() is compiled into a display list, preserve the call as a single glCallLists rather than 'n' glCallList calls. This will matter for an upcoming display list optimization project. --- src/mesa/main/dlist.c | 61 +-- 1 file changed, 3

[Mesa-dev] [PATCH] mesa: add missing error check in _mesa_CallLists()

Generate GL_INVALID_VALUE if n < 0. Return early if n==0 or lists==NULL. v2: fix formatting, also check for lists==NULL. --- src/mesa/main/dlist.c | 8 1 file changed, 8 insertions(+) diff --git a/src/mesa/main/dlist.c b/src/mesa/main/dlist.c index cd8e3b6..65f0929 100644 --- a/src/mes

Re: [Mesa-dev] [PATCH] radeonsi: enable denorms for 64-bit and 16-bit floats

FWIW, D3D requires round-toward-zero for conversion to FP16 colorbuffers. radeonsi does the same: round-toward-zero for colorbuffers and round-to-nearest-even for the GLSL packing functions. This looks like an inconsistency that may cause issues though. Marek On Tue, Feb 9, 2016 at 1:12 AM, Rola

Re: [Mesa-dev] [PATCH 2/5] st/mesa: handle indirect samplers in arrays/structs properly (v4)

>> + >> + assert(var); >> + location = var->data.location; >> + calc_deref_offsets(ir, ir, array_size, base, index, reladdr, >> &location); >> + >> + if (location != 0x) { > > This could just be an assert right? It shouldn't ever be -1 for a > sampler unless something went wrong in

Re: [Mesa-dev] [PATCH 1/2] mesa: compute sampler index in ir_to_mesa rather than using UniformHash

On 6 February 2016 at 22:30, Timothy Arceri wrote: > The aim of this is to work towards removing UniformHash from the program > struct so that we don't need to hold onto it in memory and pass it around > outside the linker. These look good to me, once they rebase on top of my stuff. Reviewed-by:

Re: [Mesa-dev] [PATCH 2/5] st/mesa: handle indirect samplers in arrays/structs properly (v4)

On Mon, 2016-02-08 at 13:45 +1000, Dave Airlie wrote: > From: Dave Airlie > > The state tracker never handled this properly, and it finally > annoyed me for the second time so I decided to fix it properly. > > This is inspired by the NIR sampler lowering code and I only realised > NIR seems to d

Re: [Mesa-dev] [PATCH] mesa: add missing error check in _mesa_CallLists()

On 02/08/2016 05:07 PM, Ian Romanick wrote: On 02/08/2016 02:31 PM, Brian Paul wrote: Generate GL_INVALID_VALUE if n < 0. Return early if n==0. --- src/mesa/main/dlist.c | 9 + 1 file changed, 9 insertions(+) diff --git a/src/mesa/main/dlist.c b/src/mesa/main/dlist.c index cd8e3b6..

Re: [Mesa-dev] [PATCH 4/5] nir: Handle large unsigned values in opt_algebraic.

On Monday, February 8, 2016 4:01:37 PM PST Ian Romanick wrote: > On 02/08/2016 01:59 PM, Kenneth Graunke wrote: > > On Thursday, February 4, 2016 5:48:00 PM PST Matt Turner wrote: > >> The next patch adds an algebraic rule that uses the constant 0xff00ff00. > >> > >> Without this change, the build

Re: [Mesa-dev] [PATCH 3/5] nir: Do opt_algebraic in reverse order.

On Mon, Feb 8, 2016 at 3:57 PM, Ian Romanick wrote: > On 02/04/2016 05:47 PM, Matt Turner wrote: >> Walking the SSA definitions in order means that we consider the smallest >> algebraic optimizations before larger optimizations. So if a smaller >> rule is part of a larger rule, the smaller one wil

Re: [Mesa-dev] [PATCH] radeonsi: enable denorms for 64-bit and 16-bit floats

Am 09.02.2016 um 00:53 schrieb Ian Romanick: > On 02/08/2016 03:37 PM, Roland Scheidegger wrote: >> Am 09.02.2016 um 00:02 schrieb Ian Romanick: >>> On 02/08/2016 12:38 PM, Marek Olšák wrote: On Mon, Feb 8, 2016 at 5:08 PM, Tom Stellard wrote: > On Sat, Feb 06, 2016 at 01:15:42PM +0100, M

Re: [Mesa-dev] [PATCH] mesa: add missing error check in _mesa_CallLists()

On 02/08/2016 02:31 PM, Brian Paul wrote: > Generate GL_INVALID_VALUE if n < 0. Return early if n==0. > --- > src/mesa/main/dlist.c | 9 + > 1 file changed, 9 insertions(+) > > diff --git a/src/mesa/main/dlist.c b/src/mesa/main/dlist.c > index cd8e3b6..24aea35 100644 > --- a/src/mesa/mai

Re: [Mesa-dev] [PATCH 1/5] glsl/ir: add param index to variable.

On Mon, 2016-02-08 at 13:45 +1000, Dave Airlie wrote: > From: Dave Airlie > > We have a requirement to store the index into the mesa parameterlist > for uniforms. Up until now we've overwritten var->data.location with > this info. However this then stops us accessing UniformStorage, > which is ne

Re: [Mesa-dev] [PATCH 4/5] nir: Handle large unsigned values in opt_algebraic.

On 02/08/2016 01:59 PM, Kenneth Graunke wrote: > On Thursday, February 4, 2016 5:48:00 PM PST Matt Turner wrote: >> The next patch adds an algebraic rule that uses the constant 0xff00ff00. >> >> Without this change, the build fails with >> >>return hex(struct.unpack('I', struct.pack('i', self.v

Re: [Mesa-dev] [PATCH 3/5] nir: Do opt_algebraic in reverse order.

On 02/04/2016 05:47 PM, Matt Turner wrote: > Walking the SSA definitions in order means that we consider the smallest > algebraic optimizations before larger optimizations. So if a smaller > rule is part of a larger rule, the smaller one will happen first, > preventing the larger one from happening

Re: [Mesa-dev] [PATCH] radeonsi: enable denorms for 64-bit and 16-bit floats

On 02/08/2016 03:37 PM, Roland Scheidegger wrote: > Am 09.02.2016 um 00:02 schrieb Ian Romanick: >> On 02/08/2016 12:38 PM, Marek Olšák wrote: >>> On Mon, Feb 8, 2016 at 5:08 PM, Tom Stellard wrote: On Sat, Feb 06, 2016 at 01:15:42PM +0100, Marek Olšák wrote: > From: Marek Olšák > >>

Re: [Mesa-dev] [PATCH 5/5] nir: Recognize open-coded bitfield_reverse.

On Mon, Feb 8, 2016 at 3:36 PM, Matt Turner wrote: > On Mon, Feb 8, 2016 at 12:04 PM, Jason Ekstrand > wrote: > > On Thu, Feb 4, 2016 at 5:48 PM, Matt Turner wrote: > >> > >> Helps 11 shaders in UnrealEngine4 demos. > >> > >> I seriously hope they would have given us bitfieldReverse() if we > >

Re: [Mesa-dev] [PATCH 0/2] Simple Klocwork patches

On 02/07/2016 02:07 PM, Matt Turner wrote: > On Sun, Feb 7, 2016 at 1:37 PM, Juha-Pekka Heikkilä > wrote: >> Hi Iago, >> >> I know there are lot of places where there is malloc unchecked still >> -- and then there is ralloc which is a story of its own. Reason why I >> think checking these would be

Re: [Mesa-dev] [Mesa-stable] [PATCH 1/4] mesa/image: Make _mesa_clip_readpixels() work with renderbuffers

BTW, maybe the same thing could be done for _mesa_DrawPixels and _mesa_clip_drawpixels(), though I don't have time to look into it myself right now. -Brian On 02/08/2016 04:40 PM, Brian Paul wrote: Looks good to me too. Reviewed-by: Brian Paul On 02/08/2016 04:36 PM, Ian Romanick wrote: S

Re: [Mesa-dev] [Mesa-stable] [PATCH 1/4] mesa/image: Make _mesa_clip_readpixels() work with renderbuffers

Looks good to me too. Reviewed-by: Brian Paul On 02/08/2016 04:36 PM, Ian Romanick wrote: Series is Reviewed-by: Ian Romanick Might wait 24 hours or so to see if anyone responsible for a non-Intel driver has commentary... since this is shared code. On 02/08/2016 02:38 PM, Nanley Chery wrot

Re: [Mesa-dev] [PATCH 5/5] nir: Recognize open-coded bitfield_reverse.

On Mon, Feb 8, 2016 at 12:04 PM, Jason Ekstrand wrote: > On Thu, Feb 4, 2016 at 5:48 PM, Matt Turner wrote: >> >> Helps 11 shaders in UnrealEngine4 demos. >> >> I seriously hope they would have given us bitfieldReverse() if we >> exposed GL 4.0 (but we do expose ARB_gpu_shader5, so why not use th

Re: [Mesa-dev] [PATCH] radeonsi: enable denorms for 64-bit and 16-bit floats

Am 09.02.2016 um 00:02 schrieb Ian Romanick: > On 02/08/2016 12:38 PM, Marek Olšák wrote: >> On Mon, Feb 8, 2016 at 5:08 PM, Tom Stellard wrote: >>> On Sat, Feb 06, 2016 at 01:15:42PM +0100, Marek Olšák wrote: From: Marek Olšák This fixes FP16 conversion instructions for VI, which

Re: [Mesa-dev] [PATCH 1/4] mesa/image: Make _mesa_clip_readpixels() work with renderbuffers

Series is Reviewed-by: Ian Romanick Might wait 24 hours or so to see if anyone responsible for a non-Intel driver has commentary... since this is shared code. On 02/08/2016 02:38 PM, Nanley Chery wrote: > From: Nanley Chery > > v2: Use gl_renderbuffer::{Width,Height} (Jason) > > Cc: "11.0 11

[Mesa-dev] [Bug 94050] test_vec4_register_coalesce regression

https://bugs.freedesktop.org/show_bug.cgi?id=94050 Matt Turner changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Mesa-dev] [Bug 94050] test_vec4_register_coalesce regression

https://bugs.freedesktop.org/show_bug.cgi?id=94050 Matt Turner changed: What|Removed |Added Assignee|mesa-dev@lists.freedesktop. |matts...@gmail.com |org

Re: [Mesa-dev] [PATCH v2 5/8] i965/fs: Plumb separate surfaces and samplers through from NIR

On Saturday, February 6, 2016 10:19:49 AM PST Jason Ekstrand wrote: > --- > src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp | 2 +- > src/mesa/drivers/dri/i965/brw_fs.cpp| 29 > - > src/mesa/drivers/dri/i965/brw_fs.h | 3 +++ > src/mesa/drivers/d

Re: [Mesa-dev] [PATCH v2 2/8] nir: Separate texture from sampler in nir_tex_instr

On Saturday, February 6, 2016 10:19:46 AM PST Jason Ekstrand wrote: > This commit adds the capability to NIR to support separate textures and > samplers. As it currently stands, glsl_to_nir only sets the texture deref > and leaves the sampler deref alone as it did before and nir_lower_samplers > a

Re: [Mesa-dev] [PATCH v2 3/8] i965/fs: Add an enum for keeping track of texture instruciton sources

On Saturday, February 6, 2016 10:19:47 AM PST Jason Ekstrand wrote: > These logical texture instructions can have a *lot* of sources. It's much > safer if we have symbolic names for them. > --- > src/mesa/drivers/dri/i965/brw_fs.cpp | 46 > +++- > src/mesa/drivers

Re: [Mesa-dev] [PATCH] radeonsi: enable denorms for 64-bit and 16-bit floats

On 02/08/2016 12:38 PM, Marek Olšák wrote: > On Mon, Feb 8, 2016 at 5:08 PM, Tom Stellard wrote: >> On Sat, Feb 06, 2016 at 01:15:42PM +0100, Marek Olšák wrote: >>> From: Marek Olšák >>> >>> This fixes FP16 conversion instructions for VI, which has 16-bit floats, >>> but not SI & CI, which can't

Re: [Mesa-dev] OpenGL ES context using EGL on framebuffer

Perhaps you'd be interested in having a look at kmscube: https://github.com/robclark/kmscube This is a simple demo which uses GBM and passes the resulting buffers to KMS for scanout. Make sure you build mesa with --enable-gbm and --enable-egl-platforms=drm [and x11 if you still want egl to work in

[Mesa-dev] [PATCH 3/4] mesa/readpix: Don't clip in _mesa_readpixels()

From: Nanley Chery The clipping is performed higher up in the call-chain. Signed-off-by: Nanley Chery --- src/mesa/main/readpix.c | 20 +++- 1 file changed, 7 insertions(+), 13 deletions(-) diff --git a/src/mesa/main/readpix.c b/src/mesa/main/readpix.c index a5b74bc..56e9d60 1

[Mesa-dev] [PATCH 4/4] mesa/readpix: Dedent former _mesa_readpixels() if block

From: Nanley Chery Formatting patch split out for easy reviewing. Signed-off-by: Nanley Chery --- src/mesa/main/readpix.c | 58 - 1 file changed, 29 insertions(+), 29 deletions(-) diff --git a/src/mesa/main/readpix.c b/src/mesa/main/readpix.c in

[Mesa-dev] [PATCH 2/4] mesa/readpix: Clip ReadPixels() area to the ReadBuffer's

From: Nanley Chery The fast path for Intel's ReadPixels() unintentionally omits clipping the specified area to a valid one. Rather than clip in various corner-cases, perform this operation in the API validation stage. The bug in intel_readpixels_tiled_memcpy() showed itself when the winsys ReadB

[Mesa-dev] [PATCH 1/4] mesa/image: Make _mesa_clip_readpixels() work with renderbuffers

From: Nanley Chery v2: Use gl_renderbuffer::{Width,Height} (Jason) Cc: "11.0 11.1" Signed-off-by: Nanley Chery --- src/mesa/main/image.c | 22 +- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/src/mesa/main/image.c b/src/mesa/main/image.c index e79e3e6..99f

[Mesa-dev] OpenGL ES context using EGL on framebuffer

Is there a way to create an OpenGL ES context using EGL on a Intel Atom E3845 without XServer? For an embedded board running a Linux (based on Yocto

[Mesa-dev] [PATCH] mesa: add missing error check in _mesa_CallLists()

Generate GL_INVALID_VALUE if n < 0. Return early if n==0. --- src/mesa/main/dlist.c | 9 + 1 file changed, 9 insertions(+) diff --git a/src/mesa/main/dlist.c b/src/mesa/main/dlist.c index cd8e3b6..24aea35 100644 --- a/src/mesa/main/dlist.c +++ b/src/mesa/main/dlist.c @@ -9105,6 +9105,15

Re: [Mesa-dev] [PATCH 4/5] nir: Handle large unsigned values in opt_algebraic.

On Thursday, February 4, 2016 5:48:00 PM PST Matt Turner wrote: > The next patch adds an algebraic rule that uses the constant 0xff00ff00. > > Without this change, the build fails with > >return hex(struct.unpack('I', struct.pack('i', self.value))[0]) >struct.error: 'i' format requires -2

Re: [Mesa-dev] [PATCH] radeonsi: enable denorms for 64-bit and 16-bit floats

On Mon, Feb 8, 2016 at 5:16 PM, Matt Arsenault wrote: > > On Feb 8, 2016, at 08:08, Tom Stellard wrote: > > Do SI/CI support fp64 denorms? If so, won't this hurt performance? > > We should tell the compiler we are enabling fp-64 denorms by adding > +fp64-denormals to the feature string. It woul

[Mesa-dev] [Bug 94040] clGetPlatformIDs causes futex race condition

https://bugs.freedesktop.org/show_bug.cgi?id=94040 Francisco Jerez changed: What|Removed |Added CC||curroje...@riseup.net --- Comment #6 f

Re: [Mesa-dev] [PATCH] radeonsi: enable denorms for 64-bit and 16-bit floats

On Mon, Feb 8, 2016 at 5:08 PM, Tom Stellard wrote: > On Sat, Feb 06, 2016 at 01:15:42PM +0100, Marek Olšák wrote: >> From: Marek Olšák >> >> This fixes FP16 conversion instructions for VI, which has 16-bit floats, >> but not SI & CI, which can't disable denorms for those instructions. > > Do you

Re: [Mesa-dev] [PATCH 5/5] nir: Recognize open-coded bitfield_reverse.

Quoting Jason Ekstrand (2016-02-08 12:04:15) [snip] > >I trust Dylan on patch 4.  I was just trying to ensure that we got/used a >32-bit value. >--Jason >  I mentioned to you offline, but I think it might be worth converting at least the opt algebraic passes to use numpy, since

Re: [Mesa-dev] [PATCH 1/6] nir: const_index helpers

On Mon, Feb 8, 2016 at 12:16 PM, Rob Clark wrote: > On Mon, Feb 8, 2016 at 3:13 PM, Jason Ekstrand > wrote: > >> + if (info->index_map[NIR_INTRINSIC_BASE] || > >> + info->index_map[NIR_INTRINSIC_WRMASK]) { > >> + fprintf(fp, " /*"); > >> + if (info->index_map[NIR_INTRINSIC_BASE

Re: [Mesa-dev] [PATCH 2/5] nir: Recognize sum of open-coded pow()s.

On Mon, Feb 8, 2016 at 12:18 PM, Matt Turner wrote: > On Mon, Feb 8, 2016 at 12:01 PM, Jason Ekstrand > wrote: > > On Thu, Feb 4, 2016 at 5:47 PM, Matt Turner wrote: > >> > >> Prevents regressions in the next commit. > >> --- > >> src/compiler/nir/nir_opt_algebraic.py | 1 + > >> 1 file change

Re: [Mesa-dev] [PATCH 2/5] nir: Recognize sum of open-coded pow()s.

On Mon, Feb 8, 2016 at 12:01 PM, Jason Ekstrand wrote: > On Thu, Feb 4, 2016 at 5:47 PM, Matt Turner wrote: >> >> Prevents regressions in the next commit. >> --- >> src/compiler/nir/nir_opt_algebraic.py | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/src/compiler/nir/nir_opt_algebrai

[Mesa-dev] [Bug 94050] test_vec4_register_coalesce regression

https://bugs.freedesktop.org/show_bug.cgi?id=94050 --- Comment #1 from Ilia Mirkin --- >From a quick glance, this appears to be a test shortcoming, not an issue with the actual patch. It assumes that prog_data is there, which is true in real life, but I guess the test doesn't set that up. -- Yo

[Mesa-dev] [Bug 94050] test_vec4_register_coalesce regression

https://bugs.freedesktop.org/show_bug.cgi?id=94050 Bug ID: 94050 Summary: test_vec4_register_coalesce regression Product: Mesa Version: git Hardware: x86-64 (AMD64) OS: Linux (All) Status: NEW Keywords: bi

Re: [Mesa-dev] [PATCH] i965: Don't add barrier deps for FB write messages.

Reviewed-by: Connor Abbott FWIW, in this area, another place where we unnecessarily introduce dependencies between instructions is when multiple instructions write to different parts of a virtual register, for example when setting up message headers. Instead of tracking dependencies per-vgrf, we

Re: [Mesa-dev] [PATCH 5/5] nir: Recognize open-coded bitfield_reverse.

On Thu, Feb 4, 2016 at 5:48 PM, Matt Turner wrote: > Helps 11 shaders in UnrealEngine4 demos. > > I seriously hope they would have given us bitfieldReverse() if we > exposed GL 4.0 (but we do expose ARB_gpu_shader5, so why not use that > anyway?). > > instructions in affected programs: 4875 -> 46

Re: [Mesa-dev] [PATCH 2/5] nir: Recognize sum of open-coded pow()s.

On Thu, Feb 4, 2016 at 5:47 PM, Matt Turner wrote: > Prevents regressions in the next commit. > --- > src/compiler/nir/nir_opt_algebraic.py | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/src/compiler/nir/nir_opt_algebraic.py > b/src/compiler/nir/nir_opt_algebraic.py > index 60df69f..0a

Re: [Mesa-dev] [PATCH] i965: Don't add barrier deps for FB write messages.

On Mon, Feb 8, 2016 at 11:31 AM, Kenneth Graunke wrote: > There are never render target reads, so there are no scheduling hazards. > > Giving the extra flexibility to the scheduler makes it possible to do > FB writes as soon as their sources are available, reducing register > pressure. It also ma

[Mesa-dev] [PATCH] i965: Don't add barrier deps for FB write messages.

There are never render target reads, so there are no scheduling hazards. Giving the extra flexibility to the scheduler makes it possible to do FB writes as soon as their sources are available, reducing register pressure. It also makes it possible to do the payload setup for more than one FB write

Re: [Mesa-dev] [RFCv3 11/11] mesa/st: add support for NIR as possible driver IR

On Mon, Feb 8, 2016 at 2:00 PM, Ilia Mirkin wrote: > On Mon, Feb 8, 2016 at 1:55 PM, Rob Clark wrote: >> On Mon, Feb 8, 2016 at 1:01 PM, Ilia Mirkin wrote: >>> On Mon, Feb 8, 2016 at 8:59 AM, Rob Clark wrote: On Mon, Feb 8, 2016 at 6:58 AM, Roland Scheidegger wrote: > Am 06.02.2

Re: [Mesa-dev] [RFCv3 11/11] mesa/st: add support for NIR as possible driver IR

On Mon, Feb 8, 2016 at 1:55 PM, Rob Clark wrote: > On Mon, Feb 8, 2016 at 1:01 PM, Ilia Mirkin wrote: >> On Mon, Feb 8, 2016 at 8:59 AM, Rob Clark wrote: >>> On Mon, Feb 8, 2016 at 6:58 AM, Roland Scheidegger >>> wrote: Am 06.02.2016 um 22:30 schrieb Marek Olšák: > On Sat, Feb 6, 2016

Re: [Mesa-dev] [PATCH] mesa/extensions: Fix NVX_gpu_memory_info lexicographical order.

On Sat, Feb 06, 2016 at 01:20:30PM +0100, Kai Wasserbäch wrote: > Hey Vinson, > I would say the test is wrong. If I sort as a human, "NV_" comes before > "NVX_". > > And running this through sort (the tool), it agrees: > > $ echo -e "NVX_gpu_memory_info\nNV_blend_square" | sort -d > NV_blend_squ

Re: [Mesa-dev] [PATCH 1/2] draw: use util_pstipple_create_fragment_shader

Thanks for this this. Series looks good to me. Reviewed-by: Jose Fonseca Sorry for not replying sooner -- I missed it. (Unfortunately I haven't been able to keep up with mesa-dev traffic and if I'm not CC'ed the odds are I miss things.) Jose On 08/02/16 14:59, Nicolai Hähnle wrote: Pin

Re: [Mesa-dev] [RFCv3 11/11] mesa/st: add support for NIR as possible driver IR

On Mon, Feb 8, 2016 at 1:01 PM, Ilia Mirkin wrote: > On Mon, Feb 8, 2016 at 8:59 AM, Rob Clark wrote: >> On Mon, Feb 8, 2016 at 6:58 AM, Roland Scheidegger >> wrote: >>> Am 06.02.2016 um 22:30 schrieb Marek Olšák: On Sat, Feb 6, 2016 at 2:45 PM, Rob Clark wrote: > On Sun, Jan 31, 2016

Re: [Mesa-dev] [PATCH 4/5] nir: Handle large unsigned values in opt_algebraic.

This seems perfectly fine to me. For what it's worth: Reviewed-by: Dylan Baker Quoting Matt Turner (2016-02-04 17:48:00) > The next patch adds an algebraic rule that uses the constant 0xff00ff00. > > Without this change, the build fails with > >return hex(struct.unpack('I', struct.pack('i'

Re: [Mesa-dev] [PATCH 3/5] nir: Do opt_algebraic in reverse order.

On Mon, Feb 8, 2016 at 9:52 AM, Jason Ekstrand wrote: > Good enough for me. Please add that to the commit message. R-B Thanks, will do. Do you plan to review any of the others in the series? ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http

Re: [Mesa-dev] [PATCH v2] workarounds: Update workaround names and platforms

On Mon, Feb 08, 2016 at 09:09:30AM -0800, Kibey, Sameer wrote: > > > > -Original Message- > > From: Widawsky, Benjamin > > Sent: Saturday, February 06, 2016 10:30 AM > > To: Kibey, Sameer > > Cc: mesa-dev@lists.freedesktop.org; Sharp, Sarah A > > Subject: Re: [PATCH v2] workarounds: Updat

Re: [Mesa-dev] [RFCv3 11/11] mesa/st: add support for NIR as possible driver IR

On Mon, Feb 8, 2016 at 8:59 AM, Rob Clark wrote: > On Mon, Feb 8, 2016 at 6:58 AM, Roland Scheidegger wrote: >> Am 06.02.2016 um 22:30 schrieb Marek Olšák: >>> On Sat, Feb 6, 2016 at 2:45 PM, Rob Clark wrote: On Sun, Jan 31, 2016 at 3:16 PM, Rob Clark wrote: > + // XXX get from pipe_

Re: [Mesa-dev] [PATCH 3/5] nir: Do opt_algebraic in reverse order.

On Feb 8, 2016 9:17 AM, "Matt Turner" wrote: > > On Sun, Feb 7, 2016 at 8:06 AM, Jason Ekstrand wrote: > > > > On Feb 4, 2016 5:45 PM, "Matt Turner" wrote: > >> > >> Walking the SSA definitions in order means that we consider the smallest > >> algebraic optimizations before larger optimizations.

Re: [Mesa-dev] [PATCH 3/3] st/mesa: don't allocate bitmap drawing state until needed

On 02/08/2016 10:10 AM, Gustaw Smolarczyk wrote: 2016-02-08 18:07 GMT+01:00 Brian Paul : Most apps don't use glBitmap so don't allocate the bitmap cache or gallium state objects/shaders/etc until the first call to st_Bitmap(). --- src/mesa/state_tracker/st_cb_bitmap.c | 145 ++-

Re: [Mesa-dev] [PATCH 3/5] nir: Do opt_algebraic in reverse order.

On Sun, Feb 7, 2016 at 8:06 AM, Jason Ekstrand wrote: > > On Feb 4, 2016 5:45 PM, "Matt Turner" wrote: >> >> Walking the SSA definitions in order means that we consider the smallest >> algebraic optimizations before larger optimizations. So if a smaller >> rule is part of a larger rule, the small

Re: [Mesa-dev] [PATCH 3/3] st/mesa: don't allocate bitmap drawing state until needed

2016-02-08 18:07 GMT+01:00 Brian Paul : > Most apps don't use glBitmap so don't allocate the bitmap cache or > gallium state objects/shaders/etc until the first call to st_Bitmap(). > --- > src/mesa/state_tracker/st_cb_bitmap.c | 145 > ++ > src/mesa/state_tracker/

Re: [Mesa-dev] [PATCH v2] workarounds: Update workaround names and platforms

> -Original Message- > From: Widawsky, Benjamin > Sent: Saturday, February 06, 2016 10:30 AM > To: Kibey, Sameer > Cc: mesa-dev@lists.freedesktop.org; Sharp, Sarah A > Subject: Re: [PATCH v2] workarounds: Update workaround names and > platforms > > On Fri, Feb 05, 2016 at 01:59:23PM -080

Re: [Mesa-dev] [RFCv3 11/11] mesa/st: add support for NIR as possible driver IR

Am 08.02.2016 um 14:59 schrieb Rob Clark: > On Mon, Feb 8, 2016 at 6:58 AM, Roland Scheidegger wrote: >> Am 06.02.2016 um 22:30 schrieb Marek Olšák: >>> On Sat, Feb 6, 2016 at 2:45 PM, Rob Clark wrote: On Sun, Jan 31, 2016 at 3:16 PM, Rob Clark wrote: > + // XXX get from pipe_screen?

[Mesa-dev] [PATCH 1/3] st/mesa: refactor some bitmap drawing code

Move setup/restoration of rendering state into helper functions. This makes the draw_bitmap_quad() function much more concise. --- src/mesa/state_tracker/st_cb_bitmap.c | 90 ++- 1 file changed, 57 insertions(+), 33 deletions(-) diff --git a/src/mesa/state_tracker/

[Mesa-dev] [PATCH 3/3] st/mesa: don't allocate bitmap drawing state until needed

Most apps don't use glBitmap so don't allocate the bitmap cache or gallium state objects/shaders/etc until the first call to st_Bitmap(). --- src/mesa/state_tracker/st_cb_bitmap.c | 145 ++ src/mesa/state_tracker/st_cb_bitmap.h | 3 - src/mesa/state_tracker/st_con

[Mesa-dev] [PATCH 2/3] st/mesa: move the setup_bitmap_vertex_data() code into draw_bitmap_quad()

Now all the code to setup the vertex data and draw it is in one place. --- src/mesa/state_tracker/st_cb_bitmap.c | 168 -- 1 file changed, 78 insertions(+), 90 deletions(-) diff --git a/src/mesa/state_tracker/st_cb_bitmap.c b/src/mesa/state_tracker/st_cb_bitmap.c

[Mesa-dev] [PATCH 10/23] i965: Use constant pointer when checking for compression

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.h | 2 +- src/mesa/drivers/dri/i965/brw_surface_formats.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h ind

[Mesa-dev] [PATCH 23/23] i965/gen9: Enable lossless compression

I tried first creating the auxiliary buffer the same time with the color buffer. That, however, led me into a situation where we would later create the rest of the mip-levels and the compression would need to be disabled (it is only supported for single level buffers). Here we try to create it on

[Mesa-dev] [PATCH 21/23] i965/gen9: Setup MCS for compressed texture surfaces

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/gen8_surface_state.c | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c index b140ff4..eaf5874 100644 --- a/src/

[Mesa-dev] [PATCH 13/23] i965: Resolve color buffer also in lossless compression case

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 6f46385..6ec02d8 100644 --- a/src/mesa/driv

[Mesa-dev] [PATCH 01/23] i965: Let caller of intel_miptree_create_layout() decide msaa layout

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 15 +++ 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 108dd87..0edd59f 100644 --- a

[Mesa-dev] [PATCH 11/23] i965/gen8: Remove dead assertion

The assertion is inside a condition mandating num_samples > 1 and therefore the first half of the constraint is always met. The second half in turn would only be applicable for single sampled case and moreover it is trying to falsely check against surface type instead of format. Subsequent patches

[Mesa-dev] [PATCH 02/23] i965: Use miptree non-aligned dimensions directly for x-tiled

The logic in intel_miptree_create() uses the local copies for 64-byte aligned equivalent but only for stencil buffers which in turn are never x-tiled. This makes the logic a little more explicit and helps to keep subsequent patches easier to read. Signed-off-by: Topi Pohjolainen --- src/mesa/dri

[Mesa-dev] [PATCH 22/23] i965: Add helper for checking for lossless compressible

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 21 + src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 3 +++ 2 files changed, 24 insertions(+) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mi

[Mesa-dev] [PATCH 20/23] i965: Expose logic telling if non-msrt mcs is supported

Alos use the opportunity to mark inputs constant. (Context has to be given as read-write to intel_miptree_supports_non_msrt_fast_clear() to support debug output). Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 9 + src/mesa/drivers/dri/i965/intel_mipm

[Mesa-dev] [PATCH 16/23] i965: Add a few assertions on lossless compression

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 4 src/mesa/drivers/dri/i965/brw_context.c | 4 2 files changed, 8 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp index bc008

[Mesa-dev] [PATCH 15/23] i965: Add a flag telling color resolve pass to ignore CCS_E

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.c | 12 +++- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 10 +- src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 9 + 3 files changed, 29 insertions(+), 2 deletions(-) diff --git a/src/mes

[Mesa-dev] [PATCH 17/23] i965: Set buffer cleared after actually clearing it

Subsequent patch will modify the surface state to set state to unresolved whenever the surface is used as render target. Color resolve itself will use the same surface setup path and marking the buffer as cleared after the draw call ensures that the state correct after the resolve Signed-off-by: T

[Mesa-dev] [PATCH 18/23] i965/gen9: Prepare surface state setup for lossless compression

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_defines.h| 1 + src/mesa/drivers/dri/i965/gen8_surface_state.c | 6 ++ 2 files changed, 7 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index fa71865..f7f

[Mesa-dev] [PATCH 03/23] i965: Separate miptree creation from auxiliary buffer setup

Currently the logic allocating and setting up miptrees is closely combined with decision making when to re-allocate buffers in X-tiled layout and when to associate colors with auxiliary buffers. These auxiliary buffers are in turn also represented as miptrees and are created by the same miptree cr

[Mesa-dev] [PATCH 04/23] i965: Don't try to create aux buffer for non-msrt aux-buffer

In addition to simply calling miptree_create() the higher level call intel_miptree_create() also considers if the buffer should be associated with an auxiliary buffer based on the given format. Here we are allocating an auxiliary buffer which in turn has such format that would mislead intel_miptre

[Mesa-dev] i965/gen9: Compression support for single-sampled

This series enables compression for single sampled color surfaces, also referred to as "lossless compression". This is yet only for driver internal use easing pressure on memory bandwidth and caches when writing, blending and sampling surfaces uing gpu. As a side effect the need for color buffer r

[Mesa-dev] [PATCH 05/23] i965: Stop considering if msrt aux buffers need aux buffer

Auxiliary buffers are always created with sample number of zero which effectively prevents intel_miptree_create_layout() from trying to associate auxiliary buffers with auxiliary buffers. Now that there is more direct path available lets start using it instead and stop even checking for such (im)p

[Mesa-dev] [PATCH 14/23] i965: Add means for limiting color resolves

Until now there has been only one type of color buffer that needs to resolved - namely single sampled fast clear. As even the sampler engine in GPU doesn't understand the associated meta data, the color values need to be always resolved prior to reading them. From SKL onwards there is new scheme s

[Mesa-dev] [PATCH 06/23] i965/gen9: Add buffer layout representing lossless compression

Skylake introduces compression support also for the single-sampled color buffers. Similarly to the multi-sampled case the color buffer will be associated with an auxiliary surface tracking the compression state. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp_blit.cpp |

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