On Sat, Aug 8, 2015 at 8:38 AM, Oded Gabbay wrote:
> On Sat, Aug 8, 2015 at 3:11 AM, Jason Ekstrand wrote:
>> On Fri, Aug 7, 2015 at 12:24 PM, Oded Gabbay wrote:
>>> This patch fixes a bug that is manifested in the read path of mesa when
>>> running on big-endian machines. The effects can be see
I noticed this when looking into Matts locking changes. Other objects are like
ly also doing this check more times then required.
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In all cases the comparison is either alreay done, or in the case
of deletes comparing against NULL.
gcc wasn't optimising it away either
---
src/mesa/main/samplerobj.c | 13 ++---
src/mesa/main/samplerobj.h | 11 +--
2 files changed, 7 insertions(+), 17 deletions(-)
diff --git a
On Sat, Aug 8, 2015 at 3:11 AM, Jason Ekstrand wrote:
> On Fri, Aug 7, 2015 at 12:24 PM, Oded Gabbay wrote:
>> This patch fixes a bug that is manifested in the read path of mesa when
>> running on big-endian machines. The effects can be seen when running
>> piglit sanity test and/or taking a scre
OpenGL 2.0 function StencilOp() is in part internally implemented via
StencilOpSeparate(). This change happened some time ago, however the
accompanying doxygen todo comment was not accordingly updated.
Replace the outdated portion of this doxygen todo comment, leaving the remainder
unchanged.
Als
On Sat, Aug 8, 2015 at 12:08 AM, Rob Clark wrote:
>
> On Fri, Aug 7, 2015 at 8:11 PM, Jason Ekstrand wrote:
> > On Fri, Aug 7, 2015 at 12:24 PM, Oded Gabbay wrote:
> >> This patch fixes a bug that is manifested in the read path of mesa when
> >> running on big-endian machines. The effects can be
On Aug 7, 2015 21:08, "Rob Clark" wrote:
>
> On Fri, Aug 7, 2015 at 8:11 PM, Jason Ekstrand
wrote:
> > On Fri, Aug 7, 2015 at 12:24 PM, Oded Gabbay
wrote:
> >> This patch fixes a bug that is manifested in the read path of mesa when
> >> running on big-endian machines. The effects can be seen whe
On Fri, Aug 7, 2015 at 8:11 PM, Jason Ekstrand wrote:
> On Fri, Aug 7, 2015 at 12:24 PM, Oded Gabbay wrote:
>> This patch fixes a bug that is manifested in the read path of mesa when
>> running on big-endian machines. The effects can be seen when running
>> piglit sanity test and/or taking a scre
On Fri, 2015-08-07 at 10:09 -0700, Ian Romanick wrote:
> I know we've talked about this about 100 times, but something in the
> back of my mind tells me that we have a pre-existing race. What happens
> if the p_atomic_dec_zero happens on thread A while thread B is between
> the _mesa_lookup_render
On Fri, Aug 7, 2015 at 1:14 PM, Chris Wilson
wrote:
> Fixes regression from
> commit 8c17d53823c77ac1c56b0548e4e54f69a33285f1
> Author: Kenneth Graunke
> Date: Wed Apr 15 03:04:33 2015 -0700
>
> i965: Make intel_emit_linear_blit handle Gen8+ alignment restrictions.
>
> which adjusted the c
On Fri, Aug 7, 2015 at 12:24 PM, Oded Gabbay wrote:
> This patch fixes a bug that is manifested in the read path of mesa when
> running on big-endian machines. The effects can be seen when running
> piglit sanity test and/or taking a screen capture.
piglit sanity isn't all that convincing. It's
On Fri, Jul 31, 2015 at 5:20 AM, Francisco Jerez wrote:
> Jason Ekstrand writes:
>
>> Curro,
>> What are we still wainting on for the image_load_store extension? I
>> think I've given you R-B's on all but one or two of the compiler
>> patches. Is the state setup stuff reviewed? Is there anythi
I don't see anything in the docs that changes with SKL that affects
this function.
Reviewed-by: Jason Ekstrand
On Wed, May 13, 2015 at 9:37 AM, Francisco Jerez wrote:
> This works as-is on SKL, only the assertion needs to be relaxed.
> ---
> src/mesa/drivers/dri/i965/brw_program.c | 2 +-
> 1
I'm not a huge fan of this patch. Really, given how complicated 3-D
textures are on SKL, there really is no sensible horizontal slice
pitch. We could return 0 as an "invalid value" but I think I'd rather
keep it an assert. Code that is dealing with 3-D textures should no
better than to just blin
On Wed, May 13, 2015 at 9:43 AM, Francisco Jerez wrote:
> v2: Add SKL support.
> ---
> src/mesa/drivers/dri/i965/brw_context.h | 2 +
> src/mesa/drivers/dri/i965/brw_surface_formats.c | 109
> +++
> src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 77 ++
On Fri, Aug 7, 2015 at 2:45 AM, Michel Thierry wrote:
> Gen8+ supports 48-bit virtual addresses, but some objects must always be
> allocated inside the 32-bit address range.
>
> In specific, any resource used with flat/heapless (0x-0xf000)
> General State Heap or Intruction State Heap
Thanks for adding the comments.
Reviewed-by: Jason Ekstrand
On Thu, Aug 6, 2015 at 7:19 AM, Francisco Jerez wrote:
> Francisco Jerez writes:
>
>> "Pohjolainen, Topi" writes:
>>
>>> On Wed, Aug 05, 2015 at 12:11:02PM +0300, Pohjolainen, Topi wrote:
On Mon, Jul 20, 2015 at 07:17:48PM +0300
Reviewed-by: Jason Ekstrand
On Mon, Jul 20, 2015 at 9:23 AM, Francisco Jerez wrote:
> v2: Add CS support.
> ---
> src/mesa/drivers/dri/i965/brw_cs.cpp | 3 ++-
> src/mesa/drivers/dri/i965/brw_gs.c | 1 +
> src/mesa/drivers/dri/i965/brw_vs.c | 3 ++-
> src/mesa/drivers/dri/i965/brw_wm.c |
I'm not 100% sure what's going on here but Topi reviewed it and it all
looks sane to me, so
Acked-by: Jason Ekstrand
On Mon, Jul 20, 2015 at 9:23 AM, Francisco Jerez wrote:
> v2: Add CS support. Move the image_params array back to
> brw_stage_prog_data.
> ---
> src/mesa/drivers/dri/i965/b
On Thu, Jul 23, 2015 at 10:33 AM, Francisco Jerez wrote:
> Accounting for the padding required for 1D arrays in certain cases.
> ---
> .../drivers/dri/i965/brw_fs_surface_builder.cpp| 52
> ++
> 1 file changed, 52 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/b
On Fri, Jul 31, 2015 at 9:58 AM, Francisco Jerez wrote:
> Jason Ekstrand writes:
>
>> On Fri, Jul 31, 2015 at 6:15 AM, Francisco Jerez
>> wrote:
>>> Jason Ekstrand writes:
>>>
On Thu, Jul 23, 2015 at 4:38 AM, Francisco Jerez
wrote:
> Jason Ekstrand writes:
>
>> This al
On Fri, Aug 7, 2015 at 6:01 PM, Jason Ekstrand wrote:
> On Fri, Aug 7, 2015 at 2:59 PM, Ilia Mirkin wrote:
>> FWIW I would very much prefer that things like this stay at the GLSL
>> IR level, otherwise we'll have to duplicate it in st/mesa (or do it at
>> the GLSL IR level).
>
> That's why you sh
On Fri, Aug 7, 2015 at 2:59 PM, Ilia Mirkin wrote:
> FWIW I would very much prefer that things like this stay at the GLSL
> IR level, otherwise we'll have to duplicate it in st/mesa (or do it at
> the GLSL IR level).
That's why you should start using nir_to_tgsi in st/mesa. :-P
> On Fri, Aug 7,
FWIW I would very much prefer that things like this stay at the GLSL
IR level, otherwise we'll have to duplicate it in st/mesa (or do it at
the GLSL IR level).
On Fri, Aug 7, 2015 at 5:56 PM, Jason Ekstrand wrote:
> Out of pure curiosity, why did you choose to do this at the GLSL IR
> level? Why
Out of pure curiosity, why did you choose to do this at the GLSL IR
level? Why not pass it through to NIR and do the lowering there? Not
that you *should* do it there, but I'm curious as to what motivated
the choice. I'm honestly not sure which would have been easier.
--Jason
On Thu, Aug 6, 201
On Fri, Aug 7, 2015 at 2:22 PM, Jason Ekstrand wrote:
> Shader-db results for vec4 programs using NIR on HSW:
>
>total instructions in shared programs: 1838157 -> 1828469 (-0.53%)
>instructions in affected programs: 275978 -> 266290 (-3.51%)
>helped:
On 7 August 2015 at 20:57, Ilia Mirkin wrote:
> On Fri, Aug 7, 2015 at 5:45 AM, Michel Thierry
> wrote:
>> Gen8+ supports 48-bit virtual addresses, but some objects must always be
>> allocated inside the 32-bit address range.
>>
>> In specific, any resource used with flat/heapless (0x-0x
Shader-db results for vec4 programs using NIR on HSW:
total instructions in shared programs: 1838157 -> 1828469 (-0.53%)
instructions in affected programs: 275978 -> 266290 (-3.51%)
helped:2827
HURT: 244
GAINED:
My C++ application was using OpenGLES 2.0 and I have a requirement to port
that app onto a MIPS(Linux) platform which support DirectFB. I have learned
from this forum that MESA-3D can be used as a bridge between my OpenGL
app and DirectFB. I have cross-compiled latest MESA for mips and statical
We do not want bug reports from this early stepping of SKL. Few if any were ever
shipped outside of Intel to early enabling partners, and none will be sold.
There is a functional change here. If you're using new mesa on an old
kernel/libdrm, the revid will be -1, and we'll use new SKL values inste
On Fri, Aug 7, 2015 at 10:37 PM, Oded Gabbay wrote:
> On Fri, Aug 7, 2015 at 10:30 PM, Matt Turner wrote:
>> On Fri, Aug 7, 2015 at 12:24 PM, Oded Gabbay wrote:
>>> This patch fixes a bug that is manifested in the read path of mesa when
>>> running on big-endian machines. The effects can be seen
All GEN GPU can bind to any piece of memory (thanks UMA), and so through
a special ioctl we can map a chunk of page-aligned client memory into
the GPU address space. However, not all GEN are equal. Some have
cache-coherency between the CPU and the GPU, whilst the others are
incoherent and rely on s
Since the introduction of reporting alphaless winsys buffers, the
GL_IMPLEMENTATION_COLOR_READ_FORMAT_OES query started reporting GL_RGBA
instead of the preferred GL_BGRA format (demos/readpix reports a
difference of almost 1000x for picking the wrong format).
Signed-off-by: Chris Wilson
---
src
The preferred image datatype for MESA_FORMAT_B8G8R8X8_UNORM and
MESA_FORMAT_B8G8R8A8_UNORM textures (including framebuffers) should be
GL_UNSIGNED_INT_8_8_8_8_REV so that an application querying
GL_IMPLEMENTATION_COLOR_READ_FORMAT_OES and
GL_IMPLEMENTATION_COLOR_READ_TYPE_OES supplies data in the d
While it is preferrable to use a fast manual detiling method for LLC
(does not require synchronisation with a busy GPU and for accessing main
memory both the CPU and GPU have the same bandwidth), if we don't have
such a path then using the GPU to perform the blit is far preferable to
a coherent mma
We only need the batch promotion for secure dispatch if we need to
modify privileged registers, so only request it when we do register
loads and stores.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.c | 12 ++--
src/mesa/drivers/dri/i965/brw_batch.h
GL_DEPTH_COMPONENT and GL_STENCIL_INDEX are simple array formats of the
indiciated types, but were absent from the get_swizzle_from_format()
table causing them to be neglect and triggering
unreachable("Unsupported format").
Signed-off-by: Chris Wilson
---
src/mesa/main/glformats.c | 2 ++
1 file
Similar to glReadPixels, using the GPU to blit back into the client's
buffer is preferrable to using a coherent mmaping (but not manual
detiling for several reasons).
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/intel_tex_image.c | 129
1 file changed, 1
The GL format/datatype for GL_DEPTH_STENCIL_EXT (GL_UNSIGNED_INT_24_8_EXT)
was lacking a translation to the internal MESA format (Z24_UNORM_S8_UINT),
and similarly for the packed floating point DEPTH_STENCIL.
Signed-off-by: Chris Wilson
---
src/mesa/main/glformats.c | 8
1 file changed,
There are only a handful of distinct cache domains (less than 16), and
internally the kernel simply doesn't differentiate between the GPU cache
domains - for recent kernels we just pass in whether the object is being
written to (for read/write busyness tracking) and whether it requires the
global G
Fixes regression from
commit 8c17d53823c77ac1c56b0548e4e54f69a33285f1
Author: Kenneth Graunke
Date: Wed Apr 15 03:04:33 2015 -0700
i965: Make intel_emit_linear_blit handle Gen8+ alignment restrictions.
which adjusted the coordinates to be relative to the nearest cacheline.
However, this th
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/intel_buffer_objects.c | 14 +-
1 file changed, 5 insertions(+), 9 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_buffer_objects.c
b/src/mesa/drivers/dri/i965/intel_buffer_objects.c
index 2b18e2c..e0566b0 100644
--
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_meta_stencil_blit.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_meta_stencil_blit.c
b/src/mesa/drivers/dri/i965/brw_meta_stencil_blit.c
index f13a8b7..4d1473a 100644
--- a/src/
We have accurate dirty tracking for normal render buffers and textures
within a batch, and so for when we only need to do a normal invalidation
of the texture cache before the next primitive we can remove the manual
flushes. We have to keep the flushes required for changing certain bits
of internal
On LLC, all buffers are normally cache coherent between the CPU and the
GPU, giving both parties fast access to shared data.
However, older architectures or Atoms, do not implement LLC between the
CPU and GPU. Instead they utilise a snooping architecture where the GPU
can snoop the CPU cache when
Avoid unrequired synchronization if the user requests to map an unused
range on active buffer, equivalent to BufferSubData.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/intel_buffer_objects.c | 76 +---
1 file changed, 42 insertions(+), 34 deletions(-)
diff --gi
Since the purpose of transform feedback tends to be for the client to
act upon the results to change the geometry in the scene, it is likely
that the client will soon be waiting upon the results. Flush the batch
early so that we don't build up a long queue of commands afterwards that
could delay th
Reuse the common upload bo for the temporary blitter storage to try and
minimise resource usage.
Caveats: this may impose a read-read relationship on the buffer between
the blitter and render engines, and may add stalls on old kernels.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/i
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_blorp.cpp | 16 +---
src/mesa/drivers/dri/i965/brw_clear.c | 11 +--
src/mesa/drivers/dri/i965/brw_context.c | 4 +++-
src/mesa/drivers/dri/i965/brw_context.h | 2 ++
src/
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_context.c | 1 -
src/mesa/drivers/dri/i965/brw_context.h | 1 -
2 files changed, 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
b/src/mesa/drivers/dri/i965/brw_context.c
index ad8ddee..117cce4 100644
--- a/src/me
Rather than allocating a fresh page every time we clear a buffer, keep
that page around between invocations by tracking the last used offset
and only allocating a fresh page when we wrap.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_meta_fast_clear.c | 17 ++---
1 fi
Since we use fences internally for tracking buffer busyness within
brw_batch.c, we can expose those directly for GL/DRI2 sync objects.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.c | 41 +-
src/mesa/drivers/dri/i965/brw_batch.h | 23 +++-
src/mesa/
Remove the old hashtable approach and switch over to the inline write
tracking with brw-batch.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.c| 71 +++-
src/mesa/drivers/dri/i965/brw_batch.h| 9 +---
src/mesa/drivers/dri/i965/brw_con
We have many flushes outside of the batch buffer critical sections that
need wrapping. Introduce a simple function to wrap the brw_emit_mi_flush()
with the begin/end.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_clear.c | 4 ++--
src/mesa/drivers/dri/i965/brw_context
In order to reduce future churn, move the callbacks for starting and
finishing the batch from intel_batchbuffer to the brw_context.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_context.c | 84 +++
src/mesa/drivers/dri/i965/brw_context.h | 3 +
We need to wrap all batch buffer access inside begin/end. In order to
make that transformation for brw_performance_monitor.c requires a small
amount of code motion, but otherwise straightforward.
To simply the number of places where we try and access the batch, we
move the start/stop based on oa_u
To ease intermediate patches.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.h | 2 ++
src/mesa/drivers/dri/i965/brw_compute.c | 4 ++--
src/mesa/drivers/dri/i965/brw_context.h | 1 -
src/mesa/drivers/dri/i965/brw_draw.c | 4 ++--
src/mesa/driver
Simple non-functional change to ease later patches.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.h | 22 ++
src/mesa/drivers/dri/i965/intel_batchbuffer.h | 22 --
2 files changed, 22 insertions(+), 22 deletions(-)
diff --git
In order to track aperture usage correctly and flush the batch at safe
transition points, we need to wrap all batch buffer access in begin/end
introduced in the previous patch.
Note, this patch doesn't transform everything - we leave the small
flushes to a later refactor and treat brw_performance_
If we have to flush the batchbuffer early that has performance
implications, and if it is a result of user action we should report that
through the perf_debug interface.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.h| 3 ++
src/mesa/drivers/dri/i965/brw_blorp.
With mesa/drm commit cd2f91e18db087edf93fed828e568ee53b887860
Author: Kristian Høgsberg Kristensen
Date: Fri Jul 31 10:47:50 2015 -0700
intel: Drop aub dumping functionality
the drm_intel_aub routines are mere stubs and do nothing. Likewise
remove our invocations.
Signed-off-by: Chris Wil
Since we can distinguish when mapping between READ and WRITE, we can
pass along the map mode to avoid stalls and flushes where possible.
Signed-off-by: Chris Wilson
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 28 ++-
1 file changed, 1
Process the postdraw resolves (including setting the buffer dirty flag)
before any conditional batch flush as that flush will want to clear the
dirty flag.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_draw.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git
Rather than spend an instruction deciding whether we need to, just zero
out the single integer to reset the HW binding tables.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_binding_tables.c | 6 --
src/mesa/drivers/dri/i965/brw_context.c| 3 +--
src/mesa/drivers/dri/i
Rather than split the render batch setup between two hooks, coalesce it
into a single callback. To simplify this, move some of the state
dirtying from the start to the finish hook hook.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.h | 6 ++---
src/mesa/drivers/dri
No external users, so no need to export the symbol outside of our
compilation unit.
Signed-off-by: Chris Wilson
Reviewed-by: Kenneth Graunke
Reviewed-by: Martin Peres
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 56 +--
src/mesa/drivers/dri/i965/intel_mipmap_tree
Just to ease the next intermediate patch.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.h | 1 +
src/mesa/drivers/dri/i965/brw_blorp.cpp| 10 +++---
src/mesa/drivers/dri/i965/brw_compute.c| 6 ++--
src/mesa/drivers/dri/i965/brw_draw.c
Refactor the aperture test, roll back and retry logic to a common idiom.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.h | 9 +
src/mesa/drivers/dri/i965/brw_blorp.cpp | 43 +--
src/mesa/drivers/dri/i965/brw_compute.c | 39 +-
In preparation for the next patch, just transplant some functions
between header files.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.h | 41 +++
src/mesa/drivers/dri/i965/intel_batchbuffer.h | 40 --
2 files changed,
Provide a common routine for doing conditional batch flushes.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.h | 6 ++
src/mesa/drivers/dri/i965/brw_blorp.cpp | 3 +--
src/mesa/drivers/dri/i965/brw_compute.c | 3 +--
src/mesa/drivers/dri/i965/brw_draw.c| 3 +--
4 f
It is essential that the value we write into the batch buffer matches
the value we record in the relocation entry (and that value also
corresponds with the presumed offset the target buffer). To ensure this
is true we combine adding relocation entry to the batch buffer with
recording the target add
Since we always flush the intel_batchbuffer before calling
intel_front_flush(), simply more that call into intel_front_flush()
itself.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_context.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/src/mesa/driv
Simple rename and parameter passing changes now to avoid doing so inside
a much larger patch.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.h | 5 +
src/mesa/drivers/dri/i965/brw_context.c | 3 ++-
src/mesa/drivers/dri/i965/brw_context.h | 2 ++
s
When processing the packed fields, it often much easier to pass around
the dword value (as would be seen by hardware) than it is manipulating
the bitfield. By aliasing the bitfield with a uint32_t member, we can
treat the value as either a collection of bits or a single value
depending upon the sit
Since brw_batch will become the dominate interface for brw_bo, move the
pointer now to reduce later churn.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.h | 2 ++
src/mesa/drivers/dri/i965/brw_binding_tables.c | 2 +-
src/mesa/drivers/dri/i965/brw_conte
To reduce churn later, move the HW context variable from brw_context to
brw_batch.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.h | 2 ++
src/mesa/drivers/dri/i965/brw_context.c | 22 +++---
src/mesa/drivers/dri/i965/brw_context.h | 2 --
In order to reduce later churn, move a few parameters from the general
brw_context into the intel_batchbuffer.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.h | 20 ++
src/mesa/drivers/dri/i965/brw_blorp.cpp | 2 +-
src/mesa/drivers/dri/i965/b
We have a few instances where we set a register to an immediate value
(MI_LOAD_REGISTER_IMM), so let's replace them with a simple routine.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_draw.c| 6 +-
src/mesa/drivers/dri/i965/brw_performance_monitor.c | 17 +++
Churn now to reduce churn later.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.h | 34 +++
src/mesa/drivers/dri/i965/brw_binding_tables.c | 3 +-
src/mesa/drivers/dri/i965/brw_context.c| 3 +-
.../drivers/dri/i965/brw_performance_m
Move the computation of the state offset into a smaller helper to reduce
churn later.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_state_dump.c | 62 --
1 file changed, 33 insertions(+), 29 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_stat
The introduction of brw_bo_create() allows us to pass a new flag down
when creating a linear buffer to allow the allocator to return a
currently active buffer. (Previously all linear buffers were presumed to
be allocated for CPU access and so the allocator only returned an idle
buffer.)
Signed-off
A simple helper to check whether the last batch buffer submitted to the
hardware is still busy. Extract it now to reduce churn later.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.h | 5 +
src/mesa/drivers/dri/i965/brw_cs.cpp | 5 ++---
src/mesa/drivers/dri/i965/brw_
gen7_sol_state loads the SOL_OFFSET registers from its scratch buffer
by hand, switch it over to the common routine for emitting that command.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/gen7_sol_state.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --g
To reduce churn later, move the brw->render_cache dirty set into the
batch (i.e. brw->batch.render_cache).
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.h | 7 +++
src/mesa/drivers/dri/i965/brw_context.h | 7 ---
src/mesa/drivers/dri/i965/intel_fbo.c | 12
Move the pipelined register access out of intel_batchbuffer into its
own utility file in preparation for replacing intel_batchbuffer. This
also gives us the opportunity to refactor a few similar routines for
writing registers, and so should prove useful in its own right.
Signed-off-by: Chris Wilso
To reduce later churn, extract drm_intel_bo_madvise() with a smaller
wrapper.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.h| 5 +
src/mesa/drivers/dri/i965/brw_object_purgeable.c | 4 ++--
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/src/
Just to reduce some later churn, pull out the flink wrapper.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.h| 7 +++
src/mesa/drivers/dri/i965/brw_context.c | 11 +--
src/mesa/drivers/dri/i965/intel_screen.c | 6 ++
3 files changed, 14 insertions(+),
Upcoming patches eliminate the intel_batchbuffer interface and one of
the minor changes that causes a lot of churn is the removal of the
header, along with the occassional need to now call intel_reg.h
themselves. This patch moves the individual includes into brw_context.h.
Signed-off-by: Chris Wil
If we don't have pipelined register access (e.g. Haswell before kernel
v4.2), then we can only implement EXT_transform_feedback by reseting the
SO offsets *between* batches. However, if we do have pipelined access to
the SO registers on gen7, we can simply emit an inline reset of the SO
registers w
Since the workaround bo is used strictly as a write-only buffer, we need
only allocate one per screen and use the same one from all contexts.
(The caveat here is during extension initialisation, where we write into
and read back register values from the buffer, but that is performed only
once for
Similarly to the pipelined SO_OFFSET check, this moves the global HW
compatability check to the screen next to the other global checks.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/intel_extensions.c | 68 +---
src/mesa/drivers/dri/i965/intel_screen.c | 1
intel_update_winsys_renderbuffer_miptree() will release the existing
miptree when wrapping a new DRI2 buffer, so we can remove the early
release and so prevent a NULL mt dereference should importing the new
DRI2 name fail for any reason. (Reusing the old DRI2 name will result
in the rendering going
Combining the multiple access checks into a few batches and a single
serialising read can reduce detection times from around 100us to 70us on
a fast Haswell system.
Signed-off-by: Chris Wilson
Cc: Kenneth Graunke
---
src/mesa/drivers/dri/i965/intel_screen.c | 165 +++
To further reduce churn when replacing the buffer object implementation,
wrap the existing drm_intel_bo_reference/drm_intel_bo_unreference.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.h | 12 +++
src/mesa/drivers/dri/i965/brw_context.c| 25
Moving the test to the screen places it alongside the other global HW
feature tesst that want to be shared between contexts.
Signed-off-by: Chris Wilson
Cc: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_context.c | 2 +
src/mesa/drivers/dri/i965/intel_extensions.c | 69 ---
To ease future transitions.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.h | 31 +++
src/mesa/drivers/dri/i965/brw_context.h | 31 ---
2 files changed, 31 insertions(+), 31 deletions(-)
diff --git a/src/mesa/driver
In order to reduce future churn, rename the intel_batchbuffer struct.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.h | 4 ++--
src/mesa/drivers/dri/i965/brw_context.h | 2 +-
src/mesa/drivers/dri/i965/brw_state_batch.c | 6 ++
src/mesa/drivers/dri/i965/
In preparation for a local batch manager with a new buffer object, first
reduce the churn by renaming the existing buffer objects:
s/drm_intel_bo/brw_bo/
We only have to be careful to leave the global screen drm_intel_bo as
they are.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/Mak
GCC's read access for single bits in a bitfield is reasonable (just a
move + flag comparison), so let's save some cachelines by packing the
write-once/read-many booleans together.
textdata bss dec hex filename
6490134 191992 26192 6708318 665c5e lib64/i965_dri.so
6491766 19
Just a couple of functions for removing an element from one list and
adding to another (perhaps even the same list, just at the head or
tail).
Used in future patches.
Signed-off-by: Chris Wilson
---
src/util/list.h | 27 +--
1 file changed, 21 insertions(+), 6 deletions(
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