Re: [Mesa-dev] [PATCH 13/78] i965/nir/vec4: Implement conditional statements (nir_cf_node_if)

On Tue, 2015-06-30 at 09:30 -0700, Jason Ekstrand wrote: > On Fri, Jun 26, 2015 at 1:06 AM, Eduardo Lima Mitev wrote: > > From: Iago Toral Quiroga > > > > The same we do in the FS NIR backend, only that here we need to consider > > the number of components in the condition and adjust the swizzle

Re: [Mesa-dev] [RFC] DRI3 support for EGL

On 02.07.2015 13:34, Boyan Ding wrote: > Forgot to mention that I was running piglit on platform x11_egl. > > Actually, I found egl and glx on dri2 both passes this test, but > glx/dri3 fails. That's why you saw the failure without my patch. I know, my point is that the failure probably isn't dir

Re: [Mesa-dev] [PATCH] mesa: reset the source packing when creating temp transfer image

On Wed, 2015-07-01 at 15:18 -0400, Ilia Mirkin wrote: > Commit 4b249d2ee (mesa: Handle transferOps in texstore_rgba) introduced > proper transferops handling, but in updating the source to the newly > allocated temporary image neglected to reset the source packing. Set it > to the default which sho

Re: [Mesa-dev] [PATCH] mesa/prog: relative offsets into constbufs are not constant

On 02/07/15 06:55, Matt Turner wrote: On Wed, Jul 1, 2015 at 3:22 PM, Ilia Mirkin wrote: The optimization logic relies on being able to read out constbuf values from program parameters. However that only works if there's no relative addressing involved. Bugzilla: https://bugs.freedesktop.org/s

[Mesa-dev] Extension to get Mesa IRs (Was: [Bug 91173])

On 01/07/15 22:30, bugzilla-dae...@freedesktop.org wrote:> *Comment # 14 > on bug 91173 from > Ilia Mirkin * > > Erm... ok... > > MOV R0.zw, c[A0.x + 9]; > M

Re: [Mesa-dev] [PATCH] mesa/prog: relative offsets into constbufs are not constant

On Wed, Jul 1, 2015 at 3:22 PM, Ilia Mirkin wrote: > The optimization logic relies on being able to read out constbuf values > from program parameters. However that only works if there's no relative > addressing involved. > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91173 > Signed-of

[Mesa-dev] [Bug 90264] [Regression, bisected] Tooltip corruption in Chrome

https://bugs.freedesktop.org/show_bug.cgi?id=90264 --- Comment #31 from Furkan --- FWIW, I tried temporarily enabling DRI3, and the effect for me is exactly the same as it is with DRI2. I have other problems with DRI3 and Chrome (that's why I keep it disabled), but that's a subject for another b

Re: [Mesa-dev] [PATCH 05/11] mesa: implement _mesa_GetTextureSubImage()

Brian, what happened to this series? Was there some conflict with DSA and so you held off? On Sat, Dec 13, 2014 at 9:42 AM, Brian Paul wrote: > One of the two new functions in GL_ARB_get_texture_sub_image. > --- > src/mesa/main/texgetimage.c | 305 > ++--

Re: [Mesa-dev] [RFC] DRI3 support for EGL

Forgot to mention that I was running piglit on platform x11_egl. Actually, I found egl and glx on dri2 both passes this test, but glx/dri3 fails. That's why you saw the failure without my patch. Regards, Boyan Ding 2015-07-02 10:58 GMT+08:00 Michel Dänzer : > On 02.07.2015 00:31, Boyan Ding wr

Re: [Mesa-dev] [PATCH] mesa/prog: relative offsets into constbufs are not constant

Seems fair. Reviewed-by: Chris Forbes On Thu, Jul 2, 2015 at 10:22 AM, Ilia Mirkin wrote: > The optimization logic relies on being able to read out constbuf values > from program parameters. However that only works if there's no relative > addressing involved. > > Bugzilla: https://bugs.freedes

[Mesa-dev] [Bug 91173] Oddworld: Stranger's Wrath HD: disfigured models in wrong colors

https://bugs.freedesktop.org/show_bug.cgi?id=91173 --- Comment #17 from Béla Gyebrószki --- (In reply to Ilia Mirkin from comment #16) > The second issue is fixed for real by > > http://patchwork.freedesktop.org/patch/53442/ Confirming, the patch fixes the remaining issue in the game and models

Re: [Mesa-dev] [RFC] DRI3 support for EGL

On 02.07.2015 00:31, Boyan Ding wrote: > > piglit shows only one regression, gl-1.0-swapbuffers-behavior went from > pass to fail (quite strange, I don't know why). That test also breaks when enabling DRI3 without your patch. -- Earthling Michel Dänzer | http://www.

Re: [Mesa-dev] [PATCH] nvc0: tune PREFER_BLIT_BASED_TEXTURE_TRANSFER capability

Amended locally to put this back into the "supported caps" section (but at the bottom), rather than the non-boolean caps section. Will push this out shortly. On Wed, Jul 1, 2015 at 10:36 PM, Alexandre Courbot wrote: > Prefer blit-based texture transfers only if the chip has dedicated VRAM > since

[Mesa-dev] [PATCH] nvc0: tune PREFER_BLIT_BASED_TEXTURE_TRANSFER capability

Prefer blit-based texture transfers only if the chip has dedicated VRAM since it would translate to a copy into the same memory on shared-memory chips. Signed-off-by: Alexandre Courbot Reported-by: Ilia Mirkin --- src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 3 ++- 1 file changed, 2 inserti

[Mesa-dev] [PATCH 1/2] i965/gs: Move vertex_count != 0 check up a level; skip one caller.

Paul's original code had emit_control_data_bits() skip the URB write if vertex_count was 0. This meant wrapping every control data write in a conditional write. We accumulate control data bits in a single UD (32-bit) register. For simple shaders that don't emit many vertices, the control data he

[Mesa-dev] [PATCH 2/2] i965: Fix indentation in emit_control_data_bits().

The last patch left the code indented too far. Signed-off-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp | 142 +++--- 1 file changed, 70 insertions(+), 72 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp b/src/mesa/drivers/

Re: [Mesa-dev] [PATCH] i965/chv|skl: Apply sampler bypass w/a

On Wed, Jul 01, 2015 at 04:03:53PM -0700, Ben Widawsky wrote: > Certain compressed formats require this setting. The docs don't go into much > detail as to why it's needed exactly. > > This fixes 0 piglit failures with a GBM gpu piglit run. I just ran this again in piglit since Chris asked me to

[Mesa-dev] [PATCH mesa v2] i965/gen8+: bo in state base address must be in 32-bit address range

Gen8+ supports 48-bit virtual addresses, but some objects must always be allocated inside the 32-bit address range. In specific, any resource used with flat/heapless (0x-0xf000) General State Heap or Intruction State Heap must be in a 32-bit range (GSH / ISH), because the General State

Re: [Mesa-dev] [RFC] DRI3 support for EGL

On Wed, 1 Jul 2015, Eero Tamminen wrote: Hi, Does this address comments raised for the 2014 EGL/DRI3 patch: http://patchwork.freedesktop.org/patch/35399/ ? - Eero Hello, The patch you mention wasn't really bringing DRI3 support to EGL, it was just using PRESENT to speed up

Re: [Mesa-dev] [PATCH] mesa/prog: relative offsets into constbufs are not constant

Ian, looks like you added this code back in antiquity... commit 54c48a95e6e0573886433f94ac83293876ffe03d Author: Ian Romanick Date: Thu Feb 10 15:48:27 2011 -0800 mesa: Add partial constant propagation pass for Mesa IR On Wed, Jul 1, 2015 at 6:22 PM, Ilia Mirkin wrote: > The optimization

[Mesa-dev] [PATCH] i965/skl: Emit new 3DSTATE_VF_COMPONENT_PACKING

We don't yet have a use for this state, but initializing it to known values is always considered wise. In general NULL state can probably go in the misc state upload, I only put it here because I assume it might be useful at some point. Signed-off-by: Ben Widawsky --- I've had this patch sitting

[Mesa-dev] [PATCH] i965/chv|skl: Apply sampler bypass w/a

Certain compressed formats require this setting. The docs don't go into much detail as to why it's needed exactly. This fixes 0 piglit failures with a GBM gpu piglit run. Signed-off-by: Ben Widawsky --- I had this one sitting around for almost 2 months. I'm not sure why I didn't send it out soo

Re: [Mesa-dev] [PATCH] nir: Don't allow copying SSA destinations

Assuming this passes piglit, Reviewed-by: Connor Abbott On Wed, Jul 1, 2015 at 4:00 PM, Jason Ekstrand wrote: > --- > src/glsl/nir/nir.c | 22 +++--- > 1 file changed, 11 insertions(+), 11 deletions(-) > > diff --git a/src/glsl/nir/nir.c b/src/glsl/nir/nir.c > index f661249..78

[Mesa-dev] [PATCH] nir: Don't allow copying SSA destinations

--- src/glsl/nir/nir.c | 22 +++--- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/src/glsl/nir/nir.c b/src/glsl/nir/nir.c index f661249..78ff886 100644 --- a/src/glsl/nir/nir.c +++ b/src/glsl/nir/nir.c @@ -147,18 +147,18 @@ void nir_src_copy(nir_src *dest, const n

[Mesa-dev] [Bug 91173] Oddworld: Stranger's Wrath HD: disfigured models in wrong colors

https://bugs.freedesktop.org/show_bug.cgi?id=91173 --- Comment #16 from Ilia Mirkin --- The second issue is fixed for real by http://patchwork.freedesktop.org/patch/53442/ -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.

[Mesa-dev] [PATCH] mesa/prog: relative offsets into constbufs are not constant

The optimization logic relies on being able to read out constbuf values from program parameters. However that only works if there's no relative addressing involved. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91173 Signed-off-by: Ilia Mirkin --- src/mesa/program/prog_opt_constant_fold

[Mesa-dev] [PATCH 6/6] i965/vs: Get rid of brw_vs_compile completely.

After tearing it out another level or two, and just passing the key and vp directly, we can finally remove this struct. It also eliminates a pointless memcpy() of the key. Signed-off-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_vec4.cpp | 37 +- src/mesa

[Mesa-dev] [PATCH 4/6] i965/vec4: Move c->last_scratch into vec4_visitor.

Nothing outside of vec4_visitor uses it, so we may as well keep it internal. Commit db9c915abcc5ad78d2d11d0e732f04cc94631350 for the vec4 backend. (The empty class will be going away soon.) Signed-off-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_vec4.cpp | 4 ++-- src/me

[Mesa-dev] [PATCH 2/6] i965/vec4: Move perf_debug about register spilling into the visitor.

This patch makes us only issue the performance warning about register spilling if we actually spilled registers. We also use scratch space for indirect addressing and the like. This is basically commit c51163b0cf7aff0375b1a5ea4cb3da9d9e164044 for the vec4 backend. Signed-off-by: Kenneth Graunke

[Mesa-dev] [PATCH 1/6] i965/vec4: Plumb log_data through so the backend_shader field gets set.

Jason plumbed this through a while back in the FS backend, but apparently we were just passing NULL in the vec4 backend. This patch passes brw in as intended. Signed-off-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_vec4.cpp| 2 +- src/mesa/drivers/dri/i965/brw_vec4.h

[Mesa-dev] [PATCH 5/6] i965/vs: Remove 'c'/vs_compile from vec4_vs_visitor.

At this point, the brw_vs_compile structure only contains the key and gl_vertex_program pointer. We may as well pass and store them directly; it's simpler and more convenient (key-> instead of vs_compile->key...). Signed-off-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_vec4.cpp

[Mesa-dev] [PATCH 3/6] i965/vec4: Move total_scratch calculation into the visitor.

This is more consistent with how we do it in the FS backend, and reduces a tiny bit of duplication. It'll also allow for a bit more tidying. Signed-off-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_gs.c | 5 + src/mesa/drivers/dri/i965/brw_vec4.cpp | 7 +-- src/mesa/drivers/

Re: [Mesa-dev] [PATCH] mesa: reset the source packing when creating temp transfer image

On Wed, Jul 1, 2015 at 12:18 PM, Ilia Mirkin wrote: > Commit 4b249d2ee (mesa: Handle transferOps in texstore_rgba) introduced > proper transferops handling, but in updating the source to the newly > allocated temporary image neglected to reset the source packing. Set it > to the default which shou

Re: [Mesa-dev] [PATCH] i965: allocate at least 1 BLEND_STATE element

Reviewed-by: Chris Forbes On Thu, Jul 2, 2015 at 4:16 AM, Mike Stroyan wrote: > When there are no color buffer render targets, gen6 and gen7 still > use the first BLEND_STATE element to determine alpha test. > gen6_upload_blend_state was allocating zero elements when > ctx->Color.AlphaEnabled wa

Re: [Mesa-dev] [PATCH 2/5] i965/fs: fix stride and type for hw_reg's in regs_read()

Personally, I think this is sensible given that, in the generator, we just copy+paste the fixed_hw_reg field. However, I'd like a second opinion. --Jason On Wed, Jul 1, 2015 at 11:51 AM, Connor Abbott wrote: > sources with file == HW_REG get all their information from the > fixed_hw_reg field, s

Re: [Mesa-dev] [PATCH 5/5] i965/fs: don't make unused payload registers interfere

Reviewed-by: Jordan Justen On 2015-07-01 11:51:39, Connor Abbott wrote: > From: Connor Abbott > > Before, we were setting payload_last_use_ip for unused payload > registers to 0, which made them interfere with whatever the first > instruction wrote to due to the workaround for SIMD16 uniform ar

Re: [Mesa-dev] [Mesa-stable] [PATCH] mesa: reset the source packing when creating temp transfer image

Seems reasonable to me. Reviewed-by: Chris Forbes On Thu, Jul 2, 2015 at 7:18 AM, Ilia Mirkin wrote: > Commit 4b249d2ee (mesa: Handle transferOps in texstore_rgba) introduced > proper transferops handling, but in updating the source to the newly > allocated temporary image neglected to reset th

Re: [Mesa-dev] [PATCH v3] glsl: fix some strict aliasing issues in exec_list

On 01/07/15 16:46, Eero Tamminen wrote: Hi, On 06/30/2015 01:15 AM, Davin McCall wrote: This is the third iteration of a patch to resolve a strict aliasing problem in the exec_list structure. At the suggestion of Francisco Jerez this is a return to the original (v1) style of the patch, which r

Re: [Mesa-dev] [PATCH 4/5] i965/fs: remove special case in setup_payload_interference()

On 2015-07-01 11:51:38, Connor Abbott wrote: > From: Connor Abbott > > regs_read() will handle LINTERP for us since the previous commit. In > addition, we were being too conservative, since it will only read 2 > registers on SIMD8. > > instructions in affected programs: 9061 -> 8893 (-1.85%)

Re: [Mesa-dev] [PATCH 1/5] i965/fs: fix regs_read() for LINTERP

Reviewed-by: Jordan Justen On 2015-07-01 11:51:35, Connor Abbott wrote: > The second source always stays within the same SIMD8 register. > > Signed-off-by: Connor Abbott > --- > src/mesa/drivers/dri/i965/brw_fs.cpp | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/src

Re: [Mesa-dev] [PATCH 3/5] i965/fs: Mark last used ip for all regs read in the payload

On 2015-07-01 11:51:37, Connor Abbott wrote: > From: Jordan Justen > > If a source register in the push constant registers uses more than on Doh. I have to point out my own typo. :) on=>one > register, then we wouldn't update payload_last_use_ip for subsequent > registers. > > Unlike most uni

[Mesa-dev] [Bug 91173] Oddworld: Stranger's Wrath HD: disfigured models in wrong colors

https://bugs.freedesktop.org/show_bug.cgi?id=91173 --- Comment #15 from Ilia Mirkin --- The following patch fully fixes the problem for me (in addition to the color thing obviously). Still need to figure out exactly which opt is broken. Kinda tempted to just remove the whole thing... diff --git

[Mesa-dev] [Bug 91173] Oddworld: Stranger's Wrath HD: disfigured models in wrong colors

https://bugs.freedesktop.org/show_bug.cgi?id=91173 --- Comment #14 from Ilia Mirkin --- Erm... ok... MOV R0.zw, c[A0.x + 9]; MOV R1.x, c[0].w; ADD R0.x, c[A0.x + 9].y, R1; FLR R0.y, R0.x; vs 0: MAD TEMP[0].xy, IN[1], CONST[7]., CONST[7]. 3: MOV TEMP[0].zw, CONST[ADDR[0].x+9] 7: F

[Mesa-dev] [Bug 91173] Oddworld: Stranger's Wrath HD: disfigured models in wrong colors

https://bugs.freedesktop.org/show_bug.cgi?id=91173 --- Comment #13 from Ilia Mirkin --- Created attachment 116854 --> https://bugs.freedesktop.org/attachment.cgi?id=116854&action=edit tgsi shader generated by that program Note that the headers of that program have stuff like #var float4 c62 :

Re: [Mesa-dev] [PATCH 4/4] gallium/ttn: mark location specially in nir for color0-writes-all

Rob Clark writes: > From: Ilia Mirkin > > We need to distinguish a shader that has separate writes to each MRT > from one which is supposed to write the data from MRT 0 to all the MRTs. > In TGSI this is done with a property. NIR doesn't have that, so encode > it as a funny location and decode o

Re: [Mesa-dev] [PATCH 2/4] gallium/ttn: IN/OUT are only array if ArrayID != 0

Rob Clark writes: > From: Rob Clark > > Fixes issue with gallium HUD. See this thread for details: > http://lists.freedesktop.org/archives/mesa-dev/2015-June/087140.html I had to apply and git show -b to make any sense of this. This block is getting really ugly looking (I think a "num_decls"

[Mesa-dev] [Bug 91173] Oddworld: Stranger's Wrath HD: disfigured models in wrong colors

https://bugs.freedesktop.org/show_bug.cgi?id=91173 --- Comment #12 from Ilia Mirkin --- The problem draw appears to be the one at call 838845. The previous one 838747 still doesn't show any bits of the model. It uses a vertex program (ARB_fp) with indirect constbuf accesses... I'm assuming it's

[Mesa-dev] [Bug 91173] Oddworld: Stranger's Wrath HD: disfigured models in wrong colors

https://bugs.freedesktop.org/show_bug.cgi?id=91173 --- Comment #11 from Béla Gyebrószki --- (In reply to Ilia Mirkin from comment #9) > Fix for the color issue available at: > http://patchwork.freedesktop.org/patch/53425/ > > Béla, any chance you could supply a screenshot of what the models are

Re: [Mesa-dev] [PATCH] i965: allocate at least 1 BLEND_STATE element

Fixes: (Flickering shadows in unreleased title trace) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80500 On Wed, Jul 1, 2015 at 10:16 AM, Mike Stroyan wrote: > When there are no color buffer render targets, gen6 and gen7 still > use

[Mesa-dev] [Bug 91173] Oddworld: Stranger's Wrath HD: disfigured models in wrong colors

https://bugs.freedesktop.org/show_bug.cgi?id=91173 --- Comment #10 from Ilia Mirkin --- Created attachment 116850 --> https://bugs.freedesktop.org/attachment.cgi?id=116850&action=edit screenshot with HEAD + color patch OK, so I guess the model is a little wrong :) Looks like a clipping issue?

[Mesa-dev] [Bug 91173] Oddworld: Stranger's Wrath HD: disfigured models in wrong colors

https://bugs.freedesktop.org/show_bug.cgi?id=91173 --- Comment #9 from Ilia Mirkin --- Fix for the color issue available at: http://patchwork.freedesktop.org/patch/53425/ Béla, any chance you could supply a screenshot of what the models are supposed to look like? They don't appear to look *that*

[Mesa-dev] [PATCH] mesa: reset the source packing when creating temp transfer image

Commit 4b249d2ee (mesa: Handle transferOps in texstore_rgba) introduced proper transferops handling, but in updating the source to the newly allocated temporary image neglected to reset the source packing. Set it to the default which should be appropriate for the floats used. Fixes: 4b249d2ee (mes

[Mesa-dev] [PATCH 1/5] i965/fs: fix regs_read() for LINTERP

The second source always stays within the same SIMD8 register. Signed-off-by: Connor Abbott --- src/mesa/drivers/dri/i965/brw_fs.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index dd95519..3

[Mesa-dev] [PATCH 5/5] i965/fs: don't make unused payload registers interfere

From: Connor Abbott Before, we were setting payload_last_use_ip for unused payload registers to 0, which made them interfere with whatever the first instruction wrote to due to the workaround for SIMD16 uniform arguments. Just use -1 to mean "unused" instead, and then skip setting any interferenc

[Mesa-dev] [PATCH 2/5] i965/fs: fix stride and type for hw_reg's in regs_read()

sources with file == HW_REG get all their information from the fixed_hw_reg field, so we need to get the stride and type from there when computing the size. Signed-off-by: Connor Abbott --- src/mesa/drivers/dri/i965/brw_fs.cpp | 24 ++-- 1 file changed, 18 insertions(+), 6 de

[Mesa-dev] [PATCH 3/5] i965/fs: Mark last used ip for all regs read in the payload

From: Jordan Justen If a source register in the push constant registers uses more than on register, then we wouldn't update payload_last_use_ip for subsequent registers. Unlike most uniform data pushed into registers, the CS gl_LocalInvocationID data varies per execution channel. Therefore for S

[Mesa-dev] [PATCH 4/5] i965/fs: remove special case in setup_payload_interference()

From: Connor Abbott regs_read() will handle LINTERP for us since the previous commit. In addition, we were being too conservative, since it will only read 2 registers on SIMD8. instructions in affected programs: 9061 -> 8893 (-1.85%) helped:10 HURT:

[Mesa-dev] [Bug 91173] Oddworld: Stranger's Wrath HD: disfigured models in wrong colors

https://bugs.freedesktop.org/show_bug.cgi?id=91173 --- Comment #8 from Ilia Mirkin --- Created attachment 116848 --> https://bugs.freedesktop.org/attachment.cgi?id=116848&action=edit bisect log for color issue OK, so I bisected the color issue to $ git bisect good 4b249d2eed686384d6d7c36f3232

[Mesa-dev] [Bug 91173] Oddworld: Stranger's Wrath HD: disfigured models in wrong colors

https://bugs.freedesktop.org/show_bug.cgi?id=91173 --- Comment #7 from Béla Gyebrószki --- (In reply to Ilia Mirkin from comment #6) > The plot thickens... it actually renders fine on HSW (i965) on mesa 10.3.7, > but fails with (approx) HEAD. Actually I'm not 100% sure if it's fine, but > it's de

[Mesa-dev] [Bug 91173] Oddworld: Stranger's Wrath HD: disfigured models in wrong colors

https://bugs.freedesktop.org/show_bug.cgi?id=91173 --- Comment #6 from Ilia Mirkin --- The plot thickens... it actually renders fine on HSW (i965) on mesa 10.3.7, but fails with (approx) HEAD. Actually I'm not 100% sure if it's fine, but it's definitely nowhere near as messed up. -- You are rec

Re: [Mesa-dev] [PATCH 3/4] nir/lower_phis_to_scalar: undef is trivially scalarizable

On Wed, Jul 1, 2015 at 8:02 AM, Rob Clark wrote: > From: Rob Clark > > Signed-off-by: Rob Clark > --- > src/glsl/nir/nir_lower_phis_to_scalar.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/src/glsl/nir/nir_lower_phis_to_scalar.c > b/src/glsl/nir/nir_lower_phis_to_scalar.c > index a

Re: [Mesa-dev] [PATCH 1/4] tgsi: update docs for ArrayID usage

This patch: Reviewed-by: Marek Olšák Marek On Wed, Jul 1, 2015 at 5:02 PM, Rob Clark wrote: > From: Rob Clark > > Signed-off-by: Rob Clark > --- > src/gallium/docs/source/tgsi.rst | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/src/gallium/docs/source/tgsi.rst > b/src/gallium/docs

Re: [Mesa-dev] [PATCH v3] glsl: fix some strict aliasing issues in exec_list

Re-post, where lines are hopefully not wrapped. Davin From b946157dcac2ca198ccf1981151525a1fc3ae39f Mon Sep 17 00:00:00 2001 From: Davin McCall Date: Sat, 27 Jun 2015 13:48:41 +0100 Subject: [PATCH] glsl: fix some strict aliasing issues in exec_list There is a problem in exec_list due to it d

Re: [Mesa-dev] [PATCH v3] glsl: fix some strict aliasing issues in exec_list

Hi Neil, On 01/07/15 17:08, Neil Roberts wrote: If we wanted to avoid growing the size of exec_list to four pointers instead of three, maybe we could store it in a union like below: struct exec_list { union { struct { struct exec_node head_sentinel; struct exec_no

Re: [Mesa-dev] [PATCH 2/2] i965/fs: Use the builder directly for the gen6 interpolation add(32)

On Wed, Jul 1, 2015 at 3:21 AM, Francisco Jerez wrote: > Jason Ekstrand writes: > >> Now that we can create builders with a bigger width than their parent as >> long as it's exec_all, we don't need to create the instruction manually. >> --- >> src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 11 ++

[Mesa-dev] [PATCH] i965: allocate at least 1 BLEND_STATE element

When there are no color buffer render targets, gen6 and gen7 still use the first BLEND_STATE element to determine alpha test. gen6_upload_blend_state was allocating zero elements when ctx->Color.AlphaEnabled was false. That left _3DSTATE_CC_STATE_POINTERS or _3DSTATE_BLEND_STATE_POINTERS pointing t

Re: [Mesa-dev] [PATCH v3] glsl: fix some strict aliasing issues in exec_list

Hi, If we wanted to avoid growing the size of exec_list to four pointers instead of three, maybe we could store it in a union like below: struct exec_list { union { struct { struct exec_node head_sentinel; struct exec_node *dummy_pointer_a; }; struct {

Re: [Mesa-dev] [RFC] DRI3 support for EGL

Hi, Does this address comments raised for the 2014 EGL/DRI3 patch: http://patchwork.freedesktop.org/patch/35399/ ? - Eero On 07/01/2015 06:31 PM, Boyan Ding wrote: The patch that follows implements DRI3 support for EGL API. Most of the code is directly ported from dri3_glx.c, w

Re: [Mesa-dev] [PATCH v3] glsl: fix some strict aliasing issues in exec_list

Hi, On 06/30/2015 01:15 AM, Davin McCall wrote: This is the third iteration of a patch to resolve a strict aliasing problem in the exec_list structure. At the suggestion of Francisco Jerez this is a return to the original (v1) style of the patch, which replaces the three 'exec_node *' members i

[Mesa-dev] [RFC] DRI3 support for EGL

The patch that follows implements DRI3 support for EGL API. Most of the code is directly ported from dri3_glx.c, with changes to match the EGL API and to fit the style of egl_dri2 driver. And most of the code specific to DRI3 lives in platform_x11_dri3.c (and .h). It depends on another patch [1] fo

[Mesa-dev] [PATCH RFC] egl/dri2: Add dri3 support to x11 platform

Signed-off-by: Boyan Ding --- configure.ac |3 + src/egl/drivers/dri2/Makefile.am |5 + src/egl/drivers/dri2/egl_dri2.c | 65 +- src/egl/drivers/dri2/egl_dri2.h | 12 +- src/egl/drivers/dri2/platform_x11.c | 127 ++- src/egl/

[Mesa-dev] [Bug 91173] Oddworld: Stranger's Wrath HD: disfigured models in wrong colors

https://bugs.freedesktop.org/show_bug.cgi?id=91173 --- Comment #5 from Béla Gyebrószki --- (In reply to Ilia Mirkin from comment #4) > Béla (or anyone else): would probably also be good to check that the *trace* > replays OK with the nvidia blob drivers. Sometimes wine will do different > things

[Mesa-dev] [PATCH 2/4] gallium/ttn: IN/OUT are only array if ArrayID != 0

From: Rob Clark Fixes issue with gallium HUD. See this thread for details: http://lists.freedesktop.org/archives/mesa-dev/2015-June/087140.html Signed-off-by: Rob Clark --- src/gallium/auxiliary/nir/tgsi_to_nir.c | 143 ++-- 1 file changed, 81 insertions(+), 62 del

[Mesa-dev] [PATCH 0/4] smattering of tgsi/ttn/nir fixes (v2)

From: Rob Clark Resend, with the patches that didn't yet get an explicit r-b (hint, hint). No real changes, although did add a bit of info to the commit msg for 2/4. Also picked up a patch from Ilia for fixing MRT. This would be solved differently after we gain some proper nir enums/defines fo

[Mesa-dev] [PATCH 3/4] nir/lower_phis_to_scalar: undef is trivially scalarizable

From: Rob Clark Signed-off-by: Rob Clark --- src/glsl/nir/nir_lower_phis_to_scalar.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/glsl/nir/nir_lower_phis_to_scalar.c b/src/glsl/nir/nir_lower_phis_to_scalar.c index a57d253..739170d 100644 --- a/src/glsl/nir/nir_lower_phis_to_scalar.c

[Mesa-dev] [PATCH 1/4] tgsi: update docs for ArrayID usage

From: Rob Clark Signed-off-by: Rob Clark --- src/gallium/docs/source/tgsi.rst | 1 + 1 file changed, 1 insertion(+) diff --git a/src/gallium/docs/source/tgsi.rst b/src/gallium/docs/source/tgsi.rst index 89ca172..4e869e7 100644 --- a/src/gallium/docs/source/tgsi.rst +++ b/src/gallium/docs/sourc

[Mesa-dev] [PATCH 4/4] gallium/ttn: mark location specially in nir for color0-writes-all

From: Ilia Mirkin We need to distinguish a shader that has separate writes to each MRT from one which is supposed to write the data from MRT 0 to all the MRTs. In TGSI this is done with a property. NIR doesn't have that, so encode it as a funny location and decode on the other end. Signed-off-by

[Mesa-dev] [Bug 91173] Oddworld: Stranger's Wrath HD: disfigured models in wrong colors

https://bugs.freedesktop.org/show_bug.cgi?id=91173 --- Comment #4 from Ilia Mirkin --- Béla (or anyone else): would probably also be good to check that the *trace* replays OK with the nvidia blob drivers. Sometimes wine will do different things there since it has more support for NV_* extensions,

Re: [Mesa-dev] [PATCH] nouveau: rename var name for nouveau_vieux to avoid conflict with nouveau

On Wed, Jul 1, 2015 at 8:26 AM, Emil Velikov wrote: > On 1 July 2015 at 08:49, Ilia Mirkin wrote: >> We want to require different versions for nouveau and nouveau_vieux. >> autoconf will only check for NOUVEAU once if both drivers are enabled, >> meaning both version checks don't get executed. Re

Re: [Mesa-dev] [PATCH v2] glsls: Modify exec_list to avoid strict-aliasing violations

On 01/07/15 13:32, Eero Tamminen wrote: Hi, On 06/25/2015 04:56 PM, Davin McCall wrote: On 25/06/15 14:32, Eero Tamminen wrote: On 06/25/2015 03:53 PM, Davin McCall wrote: On 25/06/15 12:27, Eero Tamminen wrote: On 06/25/2015 02:48 AM, Davin McCall wrote: In terms of performance: (export L

Re: [Mesa-dev] [PATCH] Fix strict-aliasing violations in GLSL shader list implementation

Hi, On 06/24/2015 05:53 AM, Matt Turner wrote: On Tue, Jun 23, 2015 at 6:44 PM, Ian Romanick wrote: Please quote the spec. Section 6.5 Expressions of the draft C99 spec I have says (page 68, 80 of the pdf): 7 An object shall have its stored value accessed only by an lvalue expression that h

Re: [Mesa-dev] [PATCH v2 16/19] i965/fs: Use the builder dispatch_width for computing register offsets

Jason Ekstrand writes: > On Fri, Jun 26, 2015 at 11:51 AM, Francisco Jerez > wrote: >> Jason Ekstrand writes: >> >>> On Fri, Jun 26, 2015 at 8:52 AM, Francisco Jerez >>> wrote: Jason Ekstrand writes: > Reviewed-by: Topi Pohjolainen > --- > src/mesa/drivers/dri/i965/b

[Mesa-dev] [PATCH] i965/gen9: Use custom MOCS entries set up by the kernel on BXT.

Follow-up to "i965/gen9: Use custom MOCS entries set up by the kernel.", sent as a separate patch to make the SKL change easier to back-port to stable branches. --- This change depends on Ville's "[PATCH 1/2] i965: House MOCS settings in brw_context/brw_device_info": http://lists.freedesktop.org/a

[Mesa-dev] [PATCHv0.5] i965/gen9: Use custom MOCS entries set up by the kernel.

Instead of relying on hardware defaults the i915 kernel driver is going program custom MOCS tables system-wide on Gen9 hardware. The "WT" entry previously used for renderbuffers had a number of problems: It disabled caching on eLLC, it used a reserved L3 cacheability setting, and it used to overri

Re: [Mesa-dev] [PATCH] i965/fs: Don't use the pixel interpolater for centroid interpolation

Ben Widawsky writes: > I am not the right person to judge the complexity tradeoff, but it > seems like a worthwhile patch to me. I spent a few minutes thinking > about how it could hurt performance and was unable to come up with > anything. Thanks. I was thinking more that the complexity means m

Re: [Mesa-dev] [PATCH 33/78] i965/nir/vec4: Implement float-related functions

Hi Jason, thanks for the review. On mar, 2015-06-30 at 14:10 -0700, Jason Ekstrand wrote: > First off, this needs a different commit message. "float-related > functions" isn't particularly descriptive. How about "various > rounding functions" because these really are all "rounding modes". True

Re: [Mesa-dev] [PATCH] nouveau: rename var name for nouveau_vieux to avoid conflict with nouveau

On 1 July 2015 at 08:49, Ilia Mirkin wrote: > We want to require different versions for nouveau and nouveau_vieux. > autoconf will only check for NOUVEAU once if both drivers are enabled, > meaning both version checks don't get executed. Rename the nouveau_vieux > one to NVVIEUX to avoid the issue

[Mesa-dev] [PATCH] i965/wm/gen7: Refactor state setup

v2: Rebased to include consideration for atomic ops in the shader. CC: Kenneth Graunke Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_state.h | 9 +++ src/mesa/drivers/dri/i965/gen7_wm_state.c | 102 +++--- 2 files changed, 75 insertions(+),

Re: [Mesa-dev] [PATCH v2] glsls: Modify exec_list to avoid strict-aliasing violations

Hi, On 06/25/2015 04:56 PM, Davin McCall wrote: On 25/06/15 14:32, Eero Tamminen wrote: On 06/25/2015 03:53 PM, Davin McCall wrote: On 25/06/15 12:27, Eero Tamminen wrote: On 06/25/2015 02:48 AM, Davin McCall wrote: In terms of performance: (export LIBGL_ALWAYS_SOFTWARE=1; time glmark2) F

[Mesa-dev] [PATCH 04/10] i965/gen4: Use tex object format instead of the miptree format

Equivalent logic for newer generations (>= 7) use the tex object format instead. This patch prepares for merging the decision making for all generations. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) di

[Mesa-dev] i965: Yet another revision of tex surface setup refactoring

Here is a rebase of refactoring originally sent in early May. This is now based on Curro's work and applies on top of the current master. I chose to re-order my patches in order to keep them as tiny as possible. Especially the dispatch for the texture buffer surfaces is split in two parts - one pat

[Mesa-dev] [PATCH 01/10] i965: Use constant miptree pointer in tex surface setup

as it is only used for reading. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.h | 2 +- src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 2 +- src/mesa/drivers/dri/i965/gen8_surface_state.c| 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff

[Mesa-dev] [PATCH 10/10] i965: Remove update_texture_surface()

This is not needed anymore. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.h | 7 -- src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 29 --- src/mesa/drivers/dri/i965/gen8_surface_state.c| 26 3 files chan

[Mesa-dev] [PATCH 09/10] i965: Use emit_texture_surface_state() directly

instead of update_texture_surface(). For gen < 7 this interface can be supported relatively easily by changing the interface of brw_update_texture_surface(). I didn't switch BRW_SURFACE_LOD_SHIFT to be emitted using SET_FIELD() as the mask for it is not defined yet. This can be addressed as a sim

[Mesa-dev] [PATCH 08/10] i965: Refactor effective depth calculation

v2: Non-trivial rebase Reviewed-by: Matt Turner (v1) Reviewed-by: Kenneth Graunke (v1) Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.h | 1 + src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 9 - src/mesa/drivers/dri/i965/gen7_wm_surface_state.c

[Mesa-dev] [PATCH 03/10] i965: Move tex buffer dispatch into hw independent setup

All generations do the same exact dispatch and it could be therefore done in the hardware independent stage. v2: Rebased where there are still duplicate calls in gen7 and gen8 handlers. These will be dropped in subsequent patches. Reviewed-by: Matt Turner (v1) Reviewed-by: Kenneth Graunke (

[Mesa-dev] [PATCH 06/10] i965/gen7: Move tex gather format override into common dispatcher

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 4 1 file changed, 4 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index c14f00a..b68b136 100644 --- a/src/mesa/drivers/dr

[Mesa-dev] [PATCH 02/10] i965: Reduce the scope of input in buffer tex setup

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.h | 4 ++-- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 8 +++- src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 2 +- src/mesa/drivers/dri/i965/gen8_surface_state.c| 2 +- 4 files changed, 7 in

[Mesa-dev] [PATCH 07/10] i965: Move texture swizzle resolving into dispatcher

v2: Non-trivial rebase Reviewed-by: Matt Turner (v1) Reviewed-by: Kenneth Graunke (v1) Signed-off-by: Topi Pohjolainen Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.h | 2 +- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 14 -- src/mes

[Mesa-dev] [PATCH 05/10] i965: Move tex miptree and format resolving into dispatcher

All hardware platforms have this in common, so do it in the hardware independent dispatcher. v2 (Matt): Removed extra whitespace. v3: Non-trivial rebase Reviewed-by: Matt Turner (v1) Reviewed-by: Kenneth Graunke (v1) Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.h

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