Re: [Mesa-dev] [Mesa-stable] [PATCH] i965: Add missing BRW_NEW_*_PROG_DATA to texture/renderbuffer atoms.

Reviewed-by: Chris Forbes On Tue, Dec 23, 2014 at 3:58 PM, Kenneth Graunke wrote: > This was probably missed when moving from a fixed binding table layout > to a dynamic one that changes based on the shader. > > Fixes newly proposed Piglit test fbo-mrt-new-bind. > > Bugzilla: https://bugs.freede

Re: [Mesa-dev] [PATCH 0/3] i965: Use intel_try_pbo_upload for sub updates and 3D textures

On Monday, December 22, 2014 07:43:11 PM Kristian Høgsberg wrote: > On Mon, Dec 22, 2014 at 3:20 PM, Chris Forbes wrote: > > Are there some performance numbers to go with this? > > Once of the synmark test cases (terrain) hits this path (pbo upload to > a 2d texture array) and the idea is that im

Re: [Mesa-dev] [PATCH 0/3] i965: Use intel_try_pbo_upload for sub updates and 3D textures

On Mon, Dec 22, 2014 at 3:20 PM, Chris Forbes wrote: > Are there some performance numbers to go with this? Once of the synmark test cases (terrain) hits this path (pbo upload to a 2d texture array) and the idea is that implementing this avoids the MapTexture fallback paths. The MapTexture paths

[Mesa-dev] [PATCH 07/21] i965/fs: Implement SIMD16 64-bit integer multiplies on Gen 8.

This patch uses the new QWORD type introduced on Gen8. This allows us to perform the operation without requiring the additional MACH. Similar to Gen7, it seems we must demote SIMD16 to 2 SIMD8s. On the bright side, we get the results in 3 instructions, and no MACH. MACH is undesirable because it r

[Mesa-dev] [PATCH 15/21] i965: Enable ARB_GPU_SHADER5 for gen8+

Signed-off-by: Ben Widawsky --- src/mesa/drivers/dri/i965/intel_extensions.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c index 76f..49d92bb 100644 --- a/src/mesa/drivers/d

[Mesa-dev] [PATCH 10/21] i965/vec4: Address mul/mach constraints

This patch addresses the errata on GEN8+ which disallows the mul/mach macro to have a modifier on src1. This was previously listed as a FINISHME. Assertions for these cases will be added shortly. Signed-off-by: Ben Widawsky --- src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 23 +++

[Mesa-dev] [PATCH 18/21] i965/vec4: Extract dword multiplies

This is the analogous patch to i965/fs: Extract dword multiplies. Like that patch, we'll do the internal users separately to aid bisection. Because that patch was requested by Jason, this was is also indirectly requested by him. Cc: Jason Ekstrand Signed-off-by: Ben Widawsky --- src/mesa/drive

[Mesa-dev] [PATCH 01/21] i965/vec4: Correct MUL destination hazard

As it turns out, we were over-thinking the cause of the hang on Cherryview. It's simply errata for Cherryview. commit 88fea85f09e2252035bec66ab26c375b45b000f5 Author: Ben Widawsky Date: Fri Nov 21 10:47:41 2014 -0800 i965/vec4/gen8: Handle the MUL dest hazard exception This is an explanat

[Mesa-dev] [PATCH 20/21] i965/fs: Add users of emit_mul_dw

I couldn't find any other callers which have a DW operand in a mul. Signed-off-by: Ben Widawsky --- It would be good if someone else can take a look --- src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i9

[Mesa-dev] [PATCH 19/21] i965: Add some dw mul operands fixes

Because we now potentially change src0/src1 in the visitor, and internal callers can use this function, we need to make sure we won't emit a bad operation. Specifically, the requirement that src1 have the only immediate is easy to hit. While the existing assertion in brw_eu_emit.c will catch this

[Mesa-dev] [PATCH 21/21] i965/vec4: Add users of emit_mul_dw

This is the vec4 analogous patch to i965/fs: Add users of emit_mul_dw Signed-off-by: Ben Widawsky --- It would be good if someone else can take a look --- src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri

[Mesa-dev] [PATCH 17/21] i965/fs: Add W*W mul shortcut

If we have any case where both operands can fit in 16b, a plain old mul with no mach should be sufficient. Signed-off-by: Ben Widawsky --- src/mesa/drivers/dri/i965/brw_fs.cpp | 5 + 1 file changed, 5 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i9

[Mesa-dev] [PATCH 14/21] i965: Disallow saturation for MACH operations

"As mach is used to generate part of the 64-bit DWord integer results, saturation modifier should not be used. In fact, saturation modifier should not be used for any of these four instructions." I believe this never actually occurred anyway, and no tests should be effected. Similar to previous p

[Mesa-dev] [PATCH 06/21] i965/fs: Implement SIMD16 64-bit integer multiplies on Gen 7.

From: Matt Turner v2 by Ben: Keep the Gen8 code: Gen8 will be fixed later. The intent is to limit the platform impact of the patch to fixing just Gen7. The original Gen7 code as written by Matt did not work properly on Gen8 (I can't remember why). I haven't actually tested the code on Ge

[Mesa-dev] [PATCH 16/21] i965/fs: Extract dword multiplies

As previously mentioned, dword multiplies have a lot of quirks. Since there are a few places where we might wish to do such multiplies, extract the functionality. This was initially requested by Jason to assist in the NIR porting effort, but it generally makes sense. Callers will be updated separ

[Mesa-dev] [PATCH 12/21] i965: Extract scalar region checking logic

There are currently 2 users of this functionality. I have 2 more users coming up, and having a simple function makes the results much cleaner. The existing interface semantics was proposed by Matt. Cc: Matt Turner Signed-off-by: Ben Widawsky --- src/mesa/drivers/dri/i965/brw_eu_emit.c|

[Mesa-dev] [PATCH 05/21] i965/fs: Implement SIMD16 integer multiplies on Gen 7.

From: Matt Turner In order to do a full 32x32 integer multiply using the MUL/MACH macro, the operation must be split into 2 SIMD8 operations. This is required even if you don't care about the high bits. My interpretation of the requirement is that the accumulator simply doesn't have enough bits t

[Mesa-dev] [PATCH 11/21] i965: Add assertions for MACH instruction

"A source modifier must not be used on src1 for the macro operation. This applies to both mul and mach of the macro. If source modifier is required, an additional mov instruction may be used before the macro." Today, we only use MACH in the macro, so this assertion should always hold. This assert

[Mesa-dev] [PATCH 08/21] i965/vec4: implement imul_high for gen8

The fancy DW * DW = QW that was enabled earlier in the series for the fs does not work for the vec4 paths. vec4 paths use ALIGN16 mode, which is restricted from the extended precision granted by gen8. This is based on a similar patch from Ken for the FS backend which was no longer needed after I w

[Mesa-dev] [PATCH 02/21] i965: Fix assertion in brw_reg_type_letters

While using various debugging features (optimization debug, instruction dumping, etc) this function is called in order to get a readable letter for the type of unit. On GEN8, two new units were added, the Qword and the Unsigned Qword (Q, and UQ respectively). The existing assertion tries to determ

[Mesa-dev] [PATCH 03/21] i965: Add QWORD sizes to type_sz macro

GEN8 added the QWORD as a valid type for certain operations on the EU. In order to calculate the number of registers used one must have the type size as part of the equation. Quoting the formula in the code: regs_written = (dst.width * dst.stride * type_sz(dst.type) + 31) / 32; Adding this separat

[Mesa-dev] [PATCH 09/21] i965: Extract is_dword test

As it turns out, I have other uses for this tiny convenience function. Simple extraction for use by others. Matt was right for not liking the macro in the initial patch. While doing this, add it to a few easy to spot users of this functionality. Signed-off-by: Ben Widawsky --- src/mesa/drivers/

[Mesa-dev] [PATCH 04/21] i965/fs: Disallow SIMD16 multiplies on GEN8

As far as we know, this isn't allowed on GEN8. Quoting the IVB PRM which talks of the hazard for GEN7, "These features or behaviors are specific to IVB and may not continue to later generations" We have no evidence to the contrary. In a few patches, after enabling GEN7, we will minimize the impact

[Mesa-dev] [PATCH 13/21] i965/eu: Add new MUL assertions

There are lots of MUL quirks for gen8+. This patch is missing one assertion, "In Align16 mode, format conversion from double-float to floats is not allowed when source is immediate data" I don't believe we're using double floats, and I wasn't actually sure what the best way to make the assertion wa

[Mesa-dev] [PATCH 00/21] DW Multiplication fixes (+gpu_shader5 on gen8+)

This patch series is kind of a pot luck of dword multiplication patches. It started off as an attempt to make sure we're adhering to the rigorous requirements on Cherryview, but turned into making sure we could properly due SIMD16 multiples across the board. The series primarily accomplishes 3 thi

Re: [Mesa-dev] [PATCH] i965: Set dirty bit for NOS fragment shader change

On Monday, December 22, 2014 05:22:06 PM Mike Stroyan wrote: > This patch fixes a problem I reported as > [Bug 87619] Changes to state such as render targets change fragment shader > without marking it dirty. > > I sent a test that demonstrates the problem to the piglit mailing list as > fbo: Cha

Re: [Mesa-dev] [PATCH 8/8] i965/vec4: Do copy before constant propagation after opt_vector_float().

On 12/21/2014 03:24 PM, Matt Turner wrote: > total instructions in shared programs: 5877012 -> 5876617 (-0.01%) > instructions in affected programs: 33140 -> 32745 (-1.19%) > > From before the commit that allows VF constant propagation (which hurt > some programs) to here, the results are: >

Re: [Mesa-dev] [PATCH 7/8] i965/vec4: Allow constant propagation of VF immediates.

On 12/21/2014 03:24 PM, Matt Turner wrote: > total instructions in shared programs: 5877951 -> 5877012 (-0.02%) > instructions in affected programs: 155923 -> 154984 (-0.60%) > > Helps 1233, hurts 156 shaders. The hurt shaders are addressed in the > next commit. > --- > .../drivers/dri/i965/b

[Mesa-dev] [PATCH] i965: Add missing BRW_NEW_*_PROG_DATA to texture/renderbuffer atoms.

This was probably missed when moving from a fixed binding table layout to a dynamic one that changes based on the shader. Fixes newly proposed Piglit test fbo-mrt-new-bind. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=87619 Signed-off-by: Kenneth Graunke Cc: Mike Stroyan Cc: "10.4 10.

Re: [Mesa-dev] [PATCH 2/8] i965: Add support for saturating immediates.

On 12/21/2014 03:24 PM, Matt Turner wrote: > I don't feel great about unreachable("unimplemented: ...") but these > cases do only seem possible under some currently impossible circumstances. > --- > src/mesa/drivers/dri/i965/brw_fs.cpp | 16 +++ > src/mesa/drivers/dri/i965/brw_shader.c

Re: [Mesa-dev] [PATCH 0/8] i965/vec4: Use Vector-float immediates.

On 12/21/2014 03:23 PM, Matt Turner wrote: > This series adds support to i965's vec4 backend for using vector-float > immediates. The shader-db results are pretty nice: > > total instructions in shared programs: 5889529 -> 5876617 (-0.22%) > instructions in affected programs: 465347 -> 452435

Re: [Mesa-dev] [PATCH] i965: Cache register write capability checks.

On Monday, December 22, 2014 05:50:33 PM Ben Widawsky wrote: > On Mon, Dec 22, 2014 at 01:28:32AM -0800, Kenneth Graunke wrote: > > Our ability to perform register writes depends on the hardware and > > kernel version. It shouldn't ever change on a per-context basis, > > so we only need to check o

Re: [Mesa-dev] [PATCH] i965: Cache register write capability checks.

On Mon, Dec 22, 2014 at 01:28:32AM -0800, Kenneth Graunke wrote: > Our ability to perform register writes depends on the hardware and > kernel version. It shouldn't ever change on a per-context basis, > so we only need to check once. That's actually not true. The kernel currently supports dynamic

Re: [Mesa-dev] [PATCH] i965: Set dirty bit for NOS fragment shader change

On 12/22/2014 04:22 PM, Mike Stroyan wrote: > A fragment program can change because of Non-Orthogonal-State changes. > brw_update_texture_surfaces needs to run because of changed surface offsets. > Set BRW_NEW_FRAGMENT_PROGRAM dirty bit in brw_upload_wm_prog to signal that. Please add Bugzilla: h

[Mesa-dev] [PATCH v2] i965: Allow intel_try_pbo_upload for 3D and array textures

I just realised I made regular cube map textures stop working via the blit path with this patch. Here is a v2 which just adds GL_TEXTURE_CUBE_MAP to the switch in intel_try_pbo_upload. I've tested that it still works with a hacky tweak to the piglit test case. --- >8 --- (use git a

[Mesa-dev] [PATCH] i965: Set dirty bit for NOS fragment shader change

A fragment program can change because of Non-Orthogonal-State changes. brw_update_texture_surfaces needs to run because of changed surface offsets. Set BRW_NEW_FRAGMENT_PROGRAM dirty bit in brw_upload_wm_prog to signal that. --- src/mesa/drivers/dri/i965/brw_wm.c | 9 - 1 file changed, 8 i

[Mesa-dev] [PATCH] i965: Set dirty bit for NOS fragment shader change

This patch fixes a problem I reported as [Bug 87619] Changes to state such as render targets change fragment shader without marking it dirty. I sent a test that demonstrates the problem to the piglit mailing list as fbo: Changing mrt binding with same shader source The root cause of problem is r

[Mesa-dev] [Bug 86701] [regression] weston-simple-egl not running anymore inside qemu

https://bugs.freedesktop.org/show_bug.cgi?id=86701 nerdopol...@verizon.net changed: What|Removed |Added CC||nerdopol...@verizon.net -- You

[Mesa-dev] [Bug 82253] JanusVR Browser rendering misses floors on radeonsi, works on intel

https://bugs.freedesktop.org/show_bug.cgi?id=82253 Christoph Haag changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

Re: [Mesa-dev] [PATCH 0/3] i965: Use intel_try_pbo_upload for sub updates and 3D textures

Are there some performance numbers to go with this? On Tue, Dec 23, 2014 at 12:08 PM, Neil Roberts wrote: > Here are some patches to make the i965 driver use the blit pipeline > for sub-texture updates and also for 3D textures and array textures > (including cube map arrays) when using PBOs. I've

[Mesa-dev] [PATCH 3/3] i965: Allow intel_try_pbo_upload for 3D and array textures

intel_try_pbo_upload now iterates over each slice of the uploaded data and and does a separate blit for each image. This copies in some fiddly details store_texsubimage in order to handle the image stride correctly for 1D array textures. --- src/mesa/drivers/dri/i965/intel_tex.h | 4 +-

[Mesa-dev] [PATCH 2/3] i965: Allow GL_UNPACK_SKIP_ROWS/PIXELS in intel_try_pbo_upload

This should just be a simple case of adding the skip values to the src offset so we can trivially implement it. --- src/mesa/drivers/dri/i965/intel_tex_image.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c b/src/mesa/drivers/

[Mesa-dev] [PATCH 0/3] i965: Use intel_try_pbo_upload for sub updates and 3D textures

Here are some patches to make the i965 driver use the blit pipeline for sub-texture updates and also for 3D textures and array textures (including cube map arrays) when using PBOs. I've also posted some patches to update the texsubimage test in Piglit to make sure these codepaths are actually teste

[Mesa-dev] [PATCH 1/3] i965: Use try_pbo_upload for glTexSubImage* as well

There is an existing function to attempt to upload texture data from a PBO via the blit pipeline called try_pbo_upload. However it was only used for the glTexImage* functions. This patches renames it to intel_try_pbo_upload and adds parameters to specify the x/y offsets and size and makes intelTexS

Re: [Mesa-dev] [PATCH 3/8] i965: Store the atoms directly in the context

On Dec 22, 2014 2:49 PM, "Ian Romanick" wrote: > > On 12/19/2014 06:20 PM, Jason Ekstrand wrote: > > I wrote basically this same patch when I was trying to speed up > > basically the same test. Unfortunately, I wasn't able to get much of an > > improvement out of it. Other than the one nit below

Re: [Mesa-dev] [PATCH 4/8] mesa: Only validate shaders that can exist in the context

On 12/22/2014 11:03 AM, Ian Romanick wrote: > On 12/21/2014 10:03 PM, Kenneth Graunke wrote: >> On Friday, December 19, 2014 02:20:55 PM Ian Romanick wrote: >>> From: Ian Romanick >>> >>> On Bay Trail-D using Fedora 20 compile flags (-m64 -O2 -mtune=generic >>> for 64-bit and -m32 -march=i686 -mtu

Re: [Mesa-dev] [PATCH 8/8] mesa: Micro-optimize _mesa_is_valid_prim_mode

On 12/21/2014 11:33 PM, Kenneth Graunke wrote: > On Friday, December 19, 2014 02:20:59 PM Ian Romanick wrote: >> From: Ian Romanick >> >> You would not believe the mess GCC 4.8.3 generated for the old >> switch-statement. >> >> On Bay Trail-D using Fedora 20 compile flags (-m64 -O2 -mtune=generic

Re: [Mesa-dev] [PATCH 3/8] i965: Store the atoms directly in the context

On 12/19/2014 06:20 PM, Jason Ekstrand wrote: > I wrote basically this same patch when I was trying to speed up > basically the same test. Unfortunately, I wasn't able to get much of an > improvement out of it. Other than the one nit below, > Reviewed-by: Jason Ekstrand

Re: [Mesa-dev] [PATCH 4/4] i965: Use safer pointer arithmetic in gather_oa_results()

On 12/19/2014 11:58 AM, Ian Romanick wrote: > On 12/18/2014 10:14 PM, Kenneth Graunke wrote: >> On Tuesday, November 18, 2014 09:11:26 PM Chad Versace wrote: >>> This patch reduces the likelihood of pointer arithmetic overflow bugs in >>> gather_oa_results(), like the one fixed by b69c7c5dac. >>

Re: [Mesa-dev] [PATCH 3/8] i965: Store the atoms directly in the context

On 12/21/2014 09:11 PM, Kenneth Graunke wrote: > On Friday, December 19, 2014 02:20:54 PM Ian Romanick wrote: >> From: Ian Romanick >> >> Instead of having an extra pointer indirection in one of the hottest >> loops in the driver. >> >> On Bay Trail-D using Fedora 20 compile flags (-m64 -O2 -mtune

Re: [Mesa-dev] [PATCH 4/8] mesa: Only validate shaders that can exist in the context

On 12/21/2014 10:03 PM, Kenneth Graunke wrote: > On Friday, December 19, 2014 02:20:55 PM Ian Romanick wrote: >> From: Ian Romanick >> >> On Bay Trail-D using Fedora 20 compile flags (-m64 -O2 -mtune=generic >> for 64-bit and -m32 -march=i686 -mtune=atom for 32-bit), affects >> Gl32Batch7: >> >> 3

[Mesa-dev] [PATCH 1/4] egl: Add Haiku code and support

* This is the cleaned up work of the Haiku GCI student Adrián Arroyo Calle adrian.arroyoca...@gmail.com * Several patches were consolidated to prevent unnecessary touching of non-related code --- include/EGL/eglplatform.h | 10 +- src/SConscript |4 + src/e

[Mesa-dev] [PATCH 4/4] egl/haiku: Clean up SConscript whitespace

--- src/egl/drivers/haiku/SConscript | 25 - 1 files changed, 12 insertions(+), 13 deletions(-) diff --git a/src/egl/drivers/haiku/SConscript b/src/egl/drivers/haiku/SConscript index 2c38599..9dd2f70 100644 --- a/src/egl/drivers/haiku/SConscript +++ b/src/egl/drivers/hai

[Mesa-dev] [PATCH 3/4] egl/dri2: Fix build of dri2 egl driver with SCons

* egl/dri2 was missing a SConscript * Problem caught by Adrián Arroyo Calle --- src/egl/drivers/dri2/SConscript | 40 +++ 1 files changed, 40 insertions(+), 0 deletions(-) create mode 100644 src/egl/drivers/dri2/SConscript diff --git a/src/egl/drivers/dri2/S

[Mesa-dev] [PATCH 2/4] egl: Clean up Haiku visual creation

* Only create one struct * 'final' also is a language conflict * Some style cleanup --- src/egl/drivers/haiku/egl_haiku.cpp | 96 +-- 1 files changed, 47 insertions(+), 49 deletions(-) diff --git a/src/egl/drivers/haiku/egl_haiku.cpp b/src/egl/drivers/haiku/egl_

Re: [Mesa-dev] [PATCH 09/12] egl: Adding Haiku configs, not stable yet

On 22/12/14 15:32, kallisti5 wrote: > On 2014-12-22 09:24, Emil Velikov wrote: >> On 22/12/14 14:36, Alexander von Gluck IV wrote: >>> From: Adrián Arroyo Calle >>> >>> --- >>> src/egl/drivers/dri2/egl_dri2.c |7 ++ >>> src/egl/drivers/dri2/platform_haiku.cpp | 172 >>> ++

Re: [Mesa-dev] [PATCH 09/12] egl: Adding Haiku configs, not stable yet

On 22/12/14 14:36, Alexander von Gluck IV wrote: > From: Adrián Arroyo Calle > > --- > src/egl/drivers/dri2/egl_dri2.c |7 ++ > src/egl/drivers/dri2/platform_haiku.cpp | 172 > +-- > src/egl/main/SConscript | 14 ++- > src/egl/main/egld

Re: [Mesa-dev] [PATCH 08/12] egl: Resolve Haiku build issues

On 22/12/14 14:36, Alexander von Gluck IV wrote: > From: Adrián Arroyo Calle > > * Builds perfect and it loads the driver. > * It still reports EGL_NOT_INITIALIZED > --- > src/egl/drivers/dri2/SConscript |8 +++- > src/egl/drivers/dri2/platform_haiku.cpp |4 > src/egl/ma

Re: [Mesa-dev] [PATCH 01/12] egl: add void library, we need to implement driver on platform_haiku.cpp

Hello guys, On 22/12/14 14:40, kallisti5 wrote: > On 2014-12-22 08:36, Alexander von Gluck IV wrote: >> From: Adrián Arroyo Calle >> >> --- >> include/EGL/eglplatform.h | 10 ++- >> src/SConscript |3 +- >> src/egl/drivers/dri2/SConscript

Re: [Mesa-dev] [PATCH 06/12] egl_dri2: a ton of blob

On Mon, Dec 22, 2014 at 6:36 AM, Alexander von Gluck IV wrote: > From: Emil Velikov > > Attempt to get a egl_dri2 SConscript > - Drop going into the gallium egl-static > - Promote the main library to a shared one. > - Convert libEGL_Haiku into a conv. library - shove a demo platform_x11. > -

Re: [Mesa-dev] [PATCH] i965: Cache register write capability checks.

Reviewed-by: Matt Turner ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 12/12] Works if we disable the EGL_BAD_SURFACE error

From: Adrián Arroyo Calle --- src/egl/drivers/haiku/egl_haiku.cpp | 175 +-- src/egl/main/eglapi.c |2 + 2 files changed, 87 insertions(+), 90 deletions(-) diff --git a/src/egl/drivers/haiku/egl_haiku.cpp b/src/egl/drivers/haiku/egl_haiku.cpp

[Mesa-dev] [PATCH 08/12] egl: Resolve Haiku build issues

From: Adrián Arroyo Calle * Builds perfect and it loads the driver. * It still reports EGL_NOT_INITIALIZED --- src/egl/drivers/dri2/SConscript |8 +++- src/egl/drivers/dri2/platform_haiku.cpp |4 src/egl/main/SConscript |4 ++-- src/egl/main/egldispla

[Mesa-dev] [PATCH 10/12] egl: Improve configuration creation for Haiku.

From: Adrián Arroyo Calle * Creates a configuration, but it does not work --- src/egl/drivers/dri2/platform_haiku.cpp | 51 ++- 1 files changed, 50 insertions(+), 1 deletions(-) diff --git a/src/egl/drivers/dri2/platform_haiku.cpp b/src/egl/drivers/dri2/platform_h

[Mesa-dev] [PATCH 07/12] egl: scons: link against libloader

From: Emil Velikov Signed-off-by: Emil Velikov --- src/egl/main/SConscript |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/src/egl/main/SConscript b/src/egl/main/SConscript index 08cc42e..6582621 100644 --- a/src/egl/main/SConscript +++ b/src/egl/main/SConscript @@ -30,

[Mesa-dev] [PATCH 01/12] egl: add void library, we need to implement driver on platform_haiku.cpp

From: Adrián Arroyo Calle --- include/EGL/eglplatform.h | 10 ++- src/SConscript |3 +- src/egl/drivers/dri2/SConscript | 24 + src/egl/drivers/dri2/platform_haiku.cpp | 42 +++ src/egl/main/

[Mesa-dev] [PATCH 06/12] egl_dri2: a ton of blob

From: Emil Velikov Attempt to get a egl_dri2 SConscript - Drop going into the gallium egl-static - Promote the main library to a shared one. - Convert libEGL_Haiku into a conv. library - shove a demo platform_x11. - s/HAVE_EGL_PLATFORM_HAIKU/HAVE_HAIKU_PLATFORM/ - A ton of extra crap all ove

[Mesa-dev] [PATCH 03/12] egl_dri2: fix plafrom_haiku includes

From: Emil Velikov Drop the gralloc_drm which is android specific header and remove the leading .. in the loader inclusion. Signed-off-by: Emil Velikov --- src/egl/drivers/dri2/platform_haiku.cpp |3 +-- 1 files changed, 1 insertions(+), 2 deletions(-) diff --git a/src/egl/drivers/dri2/pl

[Mesa-dev] [PATCH 05/12] egl_dri2/haiku: coding style fixes

From: Emil Velikov Signed-off-by: Emil Velikov --- src/egl/drivers/dri2/egl_dri2.h |4 ++-- src/egl/drivers/dri2/platform_haiku.cpp | 27 --- 2 files changed, 14 insertions(+), 17 deletions(-) diff --git a/src/egl/drivers/dri2/egl_dri2.h b/src/egl/drivers/

[Mesa-dev] [PATCH 11/12] Haiku: Remove DRI2 code as it doesn't support Haiku yet.

From: Adrián Arroyo Calle * EGL on Haiku now working --- src/SConscript |5 +- src/egl/drivers/dri2/egl_dri2.c |5 - src/egl/drivers/dri2/egl_dri2.h |5 - src/egl/drivers/dri2/platform_haiku.cpp | 300 -- src/egl/drivers/h

[Mesa-dev] [PATCH 04/12] egl_dri2/haiku: whitespace cleanup

From: Emil Velikov Signed-off-by: Emil Velikov --- src/egl/drivers/dri2/platform_haiku.cpp | 102 +++--- 1 files changed, 51 insertions(+), 51 deletions(-) diff --git a/src/egl/drivers/dri2/platform_haiku.cpp b/src/egl/drivers/dri2/platform_haiku.cpp index 77b88a9..dc

[Mesa-dev] [PATCH 09/12] egl: Adding Haiku configs, not stable yet

From: Adrián Arroyo Calle --- src/egl/drivers/dri2/egl_dri2.c |7 ++ src/egl/drivers/dri2/platform_haiku.cpp | 172 +-- src/egl/main/SConscript | 14 ++- src/egl/main/egldisplay.c |4 + 4 files changed, 160 insertions(+

[Mesa-dev] [PATCH 02/12] egl: More functions for Haiku

From: Adrián Arroyo Calle --- src/egl/drivers/dri2/egl_dri2.h | 13 src/egl/drivers/dri2/platform_haiku.cpp | 117 +-- 2 files changed, 123 insertions(+), 7 deletions(-) diff --git a/src/egl/drivers/dri2/egl_dri2.h b/src/egl/drivers/dri2/egl_dri2.h in

Re: [Mesa-dev] [PATCH] mesa: Add mesa SHA-1 functions

On Fri, Dec 19, 2014 at 11:44:42AM -0800, Kenneth Graunke wrote: > On Sunday, December 14, 2014 03:06:41 PM Emil Velikov wrote: > > On 11/12/14 21:51, Carl Worth wrote: > > > From: Kristian Høgsberg > > > > > > The upcoming shader cache uses the SHA-1 algorithm for cryptographic > > > naming. The

Re: [Mesa-dev] [PATCH V2] glsl: check if implicitly sized arrays match explicitly sized arrays across the same stage

OK, cool. This patch is Reviewed-by: Chris Forbes On Mon, Dec 22, 2014 at 11:44 PM, Timothy Arceri wrote: > > > > > > - Original Message - > From: Chris Forbes > >>Does this work correctly for arrays of interface blocks too? > >> > > Hi Chris, sorry this got lost in my indox. > > > Ju

[Mesa-dev] [PATCH] i965: Cache register write capability checks.

Our ability to perform register writes depends on the hardware and kernel version. It shouldn't ever change on a per-context basis, so we only need to check once. Checking introduces a synchronization point between the CPU and GPU: even though we submit very few GPU commands, the GPU might be bus