Re: [Mesa-dev] [RFC PATCH 03/56] mesa/main: Add tessellation shader structs

On Sunday, September 21, 2014 01:40:43 PM Chris Forbes wrote: > From: Fabian Bieler > > --- > src/mesa/main/mtypes.h | 121 > + > 1 file changed, 121 insertions(+) > > diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h > index 59e6eeb..

Re: [Mesa-dev] [RFC PATCH 03/56] mesa/main: Add tessellation shader structs

> +struct gl_tess_eval_program_state > +{ > + GLboolean Enabled; /**< GL_ARB_TESSELLATION_SHADER */ > + GLboolean _Enabled; /**< Enabled and valid program? */ > + struct gl_tess_eval_program *Current; /**< user-bound tessellation > control program */ Will s/contr

Re: [Mesa-dev] [RFC PATCH 00/56] ARB_tessellation_shader for core mesa

The first six are Reviewed-by: Matt Turner Only 50 more to go! ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [RFC PATCH 03/56] mesa/main: Add tessellation shader structs

On Sat, Sep 20, 2014 at 6:40 PM, Chris Forbes wrote: > From: Fabian Bieler > > --- > src/mesa/main/mtypes.h | 121 > + > 1 file changed, 121 insertions(+) > > diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h > index 59e6eeb..7a8f5f3 10

Re: [Mesa-dev] [RFC PATCH 05/56] mesa/main: Add tessellation shader state and limits

On Sat, Sep 20, 2014 at 6:40 PM, Chris Forbes wrote: > diff --git a/src/mesa/main/shaderapi.c b/src/mesa/main/shaderapi.c > index 79d2e94..c11ad4f 100644 > --- a/src/mesa/main/shaderapi.c > +++ b/src/mesa/main/shaderapi.c > @@ -105,6 +105,7 @@ _mesa_get_shader_flags(void) > void > _mesa_init_sha

Re: [Mesa-dev] [RFC PATCH 00/56] ARB_tessellation_shader for core mesa

Also available in my git repo, as the series is huge: https://github.com/chrisforbes/mesa/tree/tess-core-v1 On Sun, Sep 21, 2014 at 1:40 PM, Chris Forbes wrote: > This series adds all the driver-independent bits for ARB_tessellation_shader. > It's not quite finished, and there are still a handfu

[Mesa-dev] [RFC PATCH 55/56] glsl: Account for extra level of arrayness when linking VS->TES

--- src/glsl/link_interface_blocks.cpp | 4 +++- src/glsl/link_varyings.cpp | 11 --- 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/src/glsl/link_interface_blocks.cpp b/src/glsl/link_interface_blocks.cpp index b97cb95..d575b1f 100644 --- a/src/glsl/link_interfac

[Mesa-dev] [RFC PATCH 56/56] glsl: allow indexing of gl_out with gl_InvocationID even if length not known

Not all shaders are required to declare the output size; writing our outputs doesn't require the output size to be known, so don't require it. --- src/glsl/ast_array_index.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/glsl/ast_array_index.cpp b/src/glsl/ast_array_inde

[Mesa-dev] [RFC PATCH 50/56] glsl: Add ir node for barrier

--- src/glsl/ir.h | 24 src/glsl/ir_hierarchical_visitor.cpp | 9 + src/glsl/ir_hierarchical_visitor.h | 1 + src/glsl/ir_hv_accept.cpp | 6 ++ src/glsl/ir_print_visitor.cpp

[Mesa-dev] [RFC PATCH 51/56] glsl: Add builtin barrier() function

--- src/glsl/builtin_functions.cpp | 17 + 1 file changed, 17 insertions(+) diff --git a/src/glsl/builtin_functions.cpp b/src/glsl/builtin_functions.cpp index 9be7f6d..f502105 100644 --- a/src/glsl/builtin_functions.cpp +++ b/src/glsl/builtin_functions.cpp @@ -99,6 +99,12 @@ gs_on

[Mesa-dev] [RFC PATCH 52/56] glsl: Validate restrictions on use of barrier()

With the exception of always-taken switch cases (which are indistinguishable from straight line code in our IR), this disallows use of the builtin barrier() function in all the places it may not appear. Signed-off-by: Chris Forbes --- src/glsl/linker.cpp | 99

[Mesa-dev] [RFC PATCH 45/56] glsl: Support patch variables in ir_set_program_inouts

--- src/glsl/ir_set_program_inouts.cpp | 12 +--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/src/glsl/ir_set_program_inouts.cpp b/src/glsl/ir_set_program_inouts.cpp index 91c7ba3..eadc9c7 100644 --- a/src/glsl/ir_set_program_inouts.cpp +++ b/src/glsl/ir_set_program_inou

[Mesa-dev] [RFC PATCH 47/56] glsl: support separate vertex count for producer when linking

Before tessellation, the only special case was linking VS -> GS, where the VS has one output vertex and the GS has N input vertices. Now we also get to deal with the TCS -> TES linking, where both sides are arrays of vertices. --- src/glsl/ir_optimization.h | 2 +- src/glsl/link_varyings

[Mesa-dev] [RFC PATCH 43/56] glsl: Require tess input/output blocks to be arrays

--- src/glsl/ast_to_hir.cpp | 21 + 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp index 91c54d5..3a8c18f 100644 --- a/src/glsl/ast_to_hir.cpp +++ b/src/glsl/ast_to_hir.cpp @@ -5737,8 +5737,18 @@ ast_interface_bl

[Mesa-dev] [RFC PATCH 54/56] glsl: fix linker with no tcs

--- src/glsl/linker.cpp | 14 ++ 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/src/glsl/linker.cpp b/src/glsl/linker.cpp index cb27746..c1e9063 100644 --- a/src/glsl/linker.cpp +++ b/src/glsl/linker.cpp @@ -2164,16 +2164,22 @@ update_array_sizes(struct gl_shader_progra

[Mesa-dev] [RFC PATCH 53/56] glsl: Allow redeclaration of TCS gl_out[]

Signed-off-by: Chris Forbes --- src/glsl/ast_to_hir.cpp | 20 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp index 3a8c18f..ac075d8 100644 --- a/src/glsl/ast_to_hir.cpp +++ b/src/glsl/ast_to_hir.cpp @@ -5640,16

[Mesa-dev] [RFC PATCH 44/56] glsl: pass shader stage to lower_output_reads and handle tess control

From: Ilia Mirkin Tessellation control outputs can be read in directly without first having been written. Accessing these will require some special logic anyways, so just let them through. Signed-off-by: Ilia Mirkin --- src/glsl/ir_optimization.h | 2 +- src/glsl/lower_output_

[Mesa-dev] [RFC PATCH 48/56] glsl: Support patch variables in varying packing

--- src/glsl/lower_packed_varyings.cpp | 15 +-- 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/src/glsl/lower_packed_varyings.cpp b/src/glsl/lower_packed_varyings.cpp index 41ce8f4..d601836 100644 --- a/src/glsl/lower_packed_varyings.cpp +++ b/src/glsl/lower_packed_var

[Mesa-dev] [RFC PATCH 49/56] glsl: Analyze TES usage of gl_ClipDistance

--- src/glsl/linker.cpp| 19 +++ src/mesa/main/mtypes.h | 7 +++ 2 files changed, 26 insertions(+) diff --git a/src/glsl/linker.cpp b/src/glsl/linker.cpp index 7721d78..1dde5cc 100644 --- a/src/glsl/linker.cpp +++ b/src/glsl/linker.cpp @@ -629,6 +629,17 @@ validate_vertex

[Mesa-dev] [RFC PATCH 33/56] glsl: Don't lower indexing with gl_InvocationID in the TCS to cond assign

From: Fabian Bieler --- src/glsl/ir_optimization.h | 5 +-- src/glsl/lower_variable_index_to_cond_assign.cpp | 39 src/glsl/test_optpass.cpp| 3 +- src/mesa/drivers/dri/i965/brw_shader.cpp | 3 +- src/mesa/program/

[Mesa-dev] [RFC PATCH 42/56] glsl: make gl_PatchVerticesIn a system value

From: Ilia Mirkin Signed-off-by: Ilia Mirkin --- src/glsl/builtin_variables.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/glsl/builtin_variables.cpp b/src/glsl/builtin_variables.cpp index 5c363b8..a0befbd 100644 --- a/src/glsl/builtin_variables.cpp +++ b/src/gl

[Mesa-dev] [RFC PATCH 37/56] glsl: Add builtin constants for ARB_tessellation_shader

--- src/glsl/builtin_variables.cpp | 16 src/glsl/glsl_parser_extras.cpp | 11 +++ src/glsl/glsl_parser_extras.h | 11 +++ 3 files changed, 38 insertions(+) diff --git a/src/glsl/builtin_variables.cpp b/src/glsl/builtin_variables.cpp index 0909818..5c363b8 1006

[Mesa-dev] [RFC PATCH 38/56] glsl: more implicit sizing probably junk

--- src/glsl/ast_array_index.cpp | 17 +++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/src/glsl/ast_array_index.cpp b/src/glsl/ast_array_index.cpp index 1ad8361..e0110fe 100644 --- a/src/glsl/ast_array_index.cpp +++ b/src/glsl/ast_array_index.cpp @@ -107,9 +107,22

[Mesa-dev] [RFC PATCH 40/56] glsl: Restrict indexing for writes to TCS outputs to gl_InvocationID

Signed-off-by: Chris Forbes --- src/glsl/ast_to_hir.cpp | 67 + 1 file changed, 56 insertions(+), 11 deletions(-) diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp index 63f486e..f962d1e 100644 --- a/src/glsl/ast_to_hir.cpp +++ b/src/g

[Mesa-dev] [RFC PATCH 41/56] glsl: properly size unsized arrays in tess stages

--- src/glsl/ast_to_hir.cpp | 30 ++ 1 file changed, 30 insertions(+) diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp index f962d1e..91c54d5 100644 --- a/src/glsl/ast_to_hir.cpp +++ b/src/glsl/ast_to_hir.cpp @@ -3150,6 +3150,33 @@ process_initializer(ir_

[Mesa-dev] [RFC PATCH 39/56] glsl: Fix linking of VS outputs to TCS inputs

In the TCS, these are all arrays, just like GS inputs. --- src/glsl/link_varyings.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/glsl/link_varyings.cpp b/src/glsl/link_varyings.cpp index 53c26d2..5d232482 100644 --- a/src/glsl/link_varyings.cpp +++ b/src/glsl/link_va

[Mesa-dev] [RFC PATCH 46/56] glsl: Push vertex count determination down one level

We have the prog here, so we don't need the caller to work this out for us. --- src/glsl/link_varyings.cpp | 12 ++-- src/glsl/link_varyings.h | 3 +-- src/glsl/linker.cpp| 10 +++--- 3 files changed, 10 insertions(+), 15 deletions(-) diff --git a/src/glsl/link_varyings.cpp

[Mesa-dev] [RFC PATCH 32/56] glsl: Make stand-alone compiler work with tessellation shaders.

From: Fabian Bieler --- src/glsl/main.cpp | 8 +++- src/glsl/standalone_scaffolding.cpp | 1 + src/glsl/standalone_scaffolding.h | 4 3 files changed, 12 insertions(+), 1 deletion(-) diff --git a/src/glsl/main.cpp b/src/glsl/main.cpp index a4452e0..9043fa7 100644 --

[Mesa-dev] [RFC PATCH 30/56] glsl: Add "In" or "Out" suffix to name when flattening interface blocks.

From: Fabian Bieler This is to prevent a name conflict in tessellation shaders built-in interface blocks. --- src/glsl/lower_named_interface_blocks.cpp | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/glsl/lower_named_interface_blocks.cpp b/src/glsl/lower_named_int

[Mesa-dev] [RFC PATCH 27/56] glsl: lower_tess_level: Use writemask instead of vector insert op for constant swizzle.

From: Fabian Bieler --- src/glsl/lower_tess_level.cpp | 46 +++ 1 file changed, 29 insertions(+), 17 deletions(-) diff --git a/src/glsl/lower_tess_level.cpp b/src/glsl/lower_tess_level.cpp index ece5988..55029d4 100644 --- a/src/glsl/lower_tess_level.cpp

[Mesa-dev] [RFC PATCH 28/56] glsl: patch in/out qualifier

From: Fabian Bieler --- src/glsl/ast.h| 1 + src/glsl/ast_to_hir.cpp | 48 +--- src/glsl/ast_type.cpp | 3 +- src/glsl/builtin_variables.cpp| 18 +--- src/glsl/glsl_lexer.ll|

[Mesa-dev] [RFC PATCH 34/56] glsl: relax unsized input/output block arrays for TCS/TES

--- src/glsl/ast_to_hir.cpp | 29 - 1 file changed, 24 insertions(+), 5 deletions(-) diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp index 2490990..63f486e 100644 --- a/src/glsl/ast_to_hir.cpp +++ b/src/glsl/ast_to_hir.cpp @@ -5712,12 +5712,31 @@ ast_int

[Mesa-dev] [RFC PATCH 26/56] glsl: Lower gl_TessLevel* from float[n] to vecn.

From: Fabian Bieler Similar to gl_ClipDistance -> gl_ClipDistanceMESA V2 [Chris]: Fix rebase issues. --- src/glsl/Makefile.sources | 1 + src/glsl/ir_optimization.h | 1 + src/glsl/link_varyings.cpp | 50 +++- src/glsl/link_varyings.h

[Mesa-dev] [RFC PATCH 35/56] glsl: Add missing newlines to various resource limit errors

Signed-off-by: Chris Forbes --- src/glsl/linker.cpp | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/glsl/linker.cpp b/src/glsl/linker.cpp index be86371..d2a818e 100644 --- a/src/glsl/linker.cpp +++ b/src/glsl/linker.cpp @@ -2478,7 +2478,7 @@ check_resources(stru

[Mesa-dev] [RFC PATCH 36/56] glsl: Allow nonconst indexing of arrays where we can work out an implicit size

Signed-off-by: Chris Forbes --- src/glsl/ast_array_index.cpp | 24 +++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/src/glsl/ast_array_index.cpp b/src/glsl/ast_array_index.cpp index 5ca85f6..1ad8361 100644 --- a/src/glsl/ast_array_index.cpp +++ b/src/glsl/ast

[Mesa-dev] [RFC PATCH 31/56] glsl: Add builtin uniforms for default inner/outer tess levels

If the hardware needs to always have a control shader present if and evaluation shader is present, then the control shader will need these values. --- src/glsl/builtin_variables.cpp| 14 ++ src/mesa/program/prog_statevars.c | 24 src/mesa/program/prog_state

[Mesa-dev] [RFC PATCH 25/56] glsl: Make lower_clip_distance work with tessellation shaders.

From: Fabian Bieler --- src/glsl/lower_clip_distance.cpp | 181 ++- 1 file changed, 102 insertions(+), 79 deletions(-) diff --git a/src/glsl/lower_clip_distance.cpp b/src/glsl/lower_clip_distance.cpp index 2d6138d..3490203 100644 --- a/src/glsl/lower_clip_dis

[Mesa-dev] [RFC PATCH 18/56] mesa: Support querying atomic counters referenced by tess stages

Signed-off-by: Chris Forbes --- src/mesa/main/uniforms.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mesa/main/uniforms.c b/src/mesa/main/uniforms.c index ceeadf4..60fd11a 100644 --- a/src/mesa/main/uniforms.c +++ b/src/mesa/main/uniforms.c @@ -1325,10 +1325,10 @@

[Mesa-dev] [RFC PATCH 20/56] vbo: Add patch size to primitive structure.

From: Fabian Bieler --- src/mesa/vbo/vbo.h| 3 ++- src/mesa/vbo/vbo_exec_api.c | 2 ++ src/mesa/vbo/vbo_exec_array.c | 4 3 files changed, 8 insertions(+), 1 deletion(-) diff --git a/src/mesa/vbo/vbo.h b/src/mesa/vbo/vbo.h index 6e1a4aa..4fe4427 100644 --- a/src/mesa/vbo/vbo.

[Mesa-dev] [RFC PATCH 24/56] glsl: Allow tess control and tess eval shaders without VS if separate

Signed-off-by: Chris Forbes --- src/glsl/linker.cpp | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/glsl/linker.cpp b/src/glsl/linker.cpp index e7c8974..6ed54db 100644 --- a/src/glsl/linker.cpp +++ b/src/glsl/linker.cpp @@ -2776,13 +2776,15 @@ link_shaders(struct gl_

[Mesa-dev] [RFC PATCH 29/56] glsl: keep track of which inputs/outputs are per-patch

From: Ilia Mirkin --- src/glsl/ir_set_program_inouts.cpp | 21 +++-- src/mesa/main/mtypes.h | 3 +++ 2 files changed, 18 insertions(+), 6 deletions(-) diff --git a/src/glsl/ir_set_program_inouts.cpp b/src/glsl/ir_set_program_inouts.cpp index ff15362..91c7ba3 100644

[Mesa-dev] [RFC PATCH 17/56] mesa: Add support for UNIFORM_BLOCK_REFERENCED_BY_TESS_*_SHADER

Signed-off-by: Chris Forbes --- src/mesa/main/uniforms.c | 21 + 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/src/mesa/main/uniforms.c b/src/mesa/main/uniforms.c index 0d0cbf5..ceeadf4 100644 --- a/src/mesa/main/uniforms.c +++ b/src/mesa/main/uniforms.c @@ -1

[Mesa-dev] [RFC PATCH 16/56] mesa/program: Add misc tessellation shader support.

From: Fabian Bieler --- src/mesa/program/program.c | 44 ++ src/mesa/program/program.h | 60 +- 2 files changed, 103 insertions(+), 1 deletion(-) diff --git a/src/mesa/program/program.c b/src/mesa/program/program.c inde

[Mesa-dev] [RFC PATCH 15/56] mesa/main: Add misc tessellation shader stuff.

From: Fabian Bieler --- src/mesa/main/context.c | 6 + src/mesa/main/mtypes.h| 3 ++- src/mesa/main/shaderapi.c | 29 src/mesa/main/state.c | 67 +-- 4 files changed, 102 insertions(+), 3 deletions(-) diff --git a/

[Mesa-dev] [RFC PATCH 21/56] glsl: Add tessellation shader defines and built-in variables.

From: Fabian Bieler --- src/glsl/builtin_variables.cpp | 62 +- src/glsl/glcpp/glcpp-parse.y | 3 ++ 2 files changed, 64 insertions(+), 1 deletion(-) diff --git a/src/glsl/builtin_variables.cpp b/src/glsl/builtin_variables.cpp index 5b6f4ae..7ba0fe8 10

[Mesa-dev] [RFC PATCH 22/56] glsl: Add tessellation shader parsing support.

From: Fabian Bieler --- src/glsl/ast.h | 46 + src/glsl/ast_to_hir.cpp | 145 +++- src/glsl/ast_type.cpp | 112 ++- src/glsl/glsl_parser.yy | 118 ++

[Mesa-dev] [RFC PATCH 08/56] mesa: Support tess stages in glGetProgramPipelineiv

From: Fabian Bieler --- src/mesa/main/pipelineobj.c | 15 +++ 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/src/mesa/main/pipelineobj.c b/src/mesa/main/pipelineobj.c index b713d95..61a5785 100644 --- a/src/mesa/main/pipelineobj.c +++ b/src/mesa/main/pipelineobj.c @@

[Mesa-dev] [RFC PATCH 14/56] mesa/main: Add tessellation shader getters.

From: Fabian Bieler --- src/mesa/main/get.c | 1 + src/mesa/main/get_hash_params.py | 21 src/mesa/main/shaderapi.c| 73 3 files changed, 95 insertions(+) diff --git a/src/mesa/main/get.c b/src/mesa/main/get.c index 0e2

[Mesa-dev] [RFC PATCH 12/56] mesa: Add tessellation shader builtin varyings.

From: Fabian Bieler --- src/mesa/main/mtypes.h| 15 ++- src/mesa/program/prog_print.c | 4 2 files changed, 18 insertions(+), 1 deletion(-) diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h index 9e989d7..9088e97 100644 --- a/src/mesa/main/mtypes.h +++ b/src

[Mesa-dev] [RFC PATCH 23/56] glsl: Allow linking of tessellation shaders.

Signed-off-by: Chris Forbes --- src/glsl/link_interface_blocks.cpp | 9 +- src/glsl/linker.cpp| 248 - 2 files changed, 252 insertions(+), 5 deletions(-) diff --git a/src/glsl/link_interface_blocks.cpp b/src/glsl/link_interface_blocks.cpp in

[Mesa-dev] [RFC PATCH 19/56] mesa: add system value for gl_PatchVerticesIn

From: Ilia Mirkin Signed-off-by: Ilia Mirkin Conflicts: src/mesa/main/mtypes.h --- src/mesa/main/mtypes.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h index 9bd78e4..b03afd2 100644 --- a/src/mesa/main/mtypes.h +++ b/src/mesa/main/m

[Mesa-dev] [RFC PATCH 09/56] mesa: Allow tess stages in glUseProgramStages

--- src/mesa/main/pipelineobj.c | 17 + 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/src/mesa/main/pipelineobj.c b/src/mesa/main/pipelineobj.c index 61a5785..c902107 100644 --- a/src/mesa/main/pipelineobj.c +++ b/src/mesa/main/pipelineobj.c @@ -243,14 +243,13 @@ _

[Mesa-dev] [RFC PATCH 11/56] mesa: Require VS if TCS or TES is present in pipeline

Signed-off-by: Chris Forbes --- src/mesa/main/pipelineobj.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mesa/main/pipelineobj.c b/src/mesa/main/pipelineobj.c index b91289e..75edac1 100644 --- a/src/mesa/main/pipelineobj.c +++ b/src/mesa/main/pipelineobj.c @@ -767

[Mesa-dev] [RFC PATCH 03/56] mesa/main: Add tessellation shader structs

From: Fabian Bieler --- src/mesa/main/mtypes.h | 121 + 1 file changed, 121 insertions(+) diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h index 59e6eeb..7a8f5f3 100644 --- a/src/mesa/main/mtypes.h +++ b/src/mesa/main/mtypes.h @@ -2274

[Mesa-dev] [RFC PATCH 02/56] mesa/main: Add ARB_tessellation_shader to extension table.

From: Fabian Bieler --- src/mesa/main/extensions.c | 1 + src/mesa/main/mtypes.h | 1 + 2 files changed, 2 insertions(+) diff --git a/src/mesa/main/extensions.c b/src/mesa/main/extensions.c index 553c01e..e676e18 100644 --- a/src/mesa/main/extensions.c +++ b/src/mesa/main/extensions.c @@ -1

[Mesa-dev] [RFC PATCH 10/56] mesa: Generalize sso stage interleaving check for tess

Signed-off-by: Chris Forbes --- src/mesa/main/pipelineobj.c | 53 +++-- 1 file changed, 37 insertions(+), 16 deletions(-) diff --git a/src/mesa/main/pipelineobj.c b/src/mesa/main/pipelineobj.c index c902107..b91289e 100644 --- a/src/mesa/main/pipelineobj.c

[Mesa-dev] [RFC PATCH 13/56] mesa/main: Allow setting of patch parameters.

From: Fabian Bieler --- src/mesa/main/shaderapi.c | 30 -- 1 file changed, 28 insertions(+), 2 deletions(-) diff --git a/src/mesa/main/shaderapi.c b/src/mesa/main/shaderapi.c index c11ad4f..cfad210 100644 --- a/src/mesa/main/shaderapi.c +++ b/src/mesa/main/shaderapi.

[Mesa-dev] [RFC PATCH 05/56] mesa/main: Add tessellation shader state and limits

--- src/mesa/main/config.h| 8 src/mesa/main/context.c | 10 ++ src/mesa/main/mtypes.h| 9 + src/mesa/main/shaderapi.c | 7 +++ 4 files changed, 34 insertions(+) diff --git a/src/mesa/main/config.h b/src/mesa/main/config.h index 4ec4b75..c0b5914 100644 --

[Mesa-dev] [RFC PATCH 07/56] mesa: Allow drawing of patch primitives

Signed-off-by: Chris Forbes --- src/mesa/main/api_validate.c | 43 ++- 1 file changed, 42 insertions(+), 1 deletion(-) diff --git a/src/mesa/main/api_validate.c b/src/mesa/main/api_validate.c index 51a3d1f..64ed465 100644 --- a/src/mesa/main/api_validate.c

[Mesa-dev] [RFC PATCH 04/56] mesa: Add tessellation shader enums

From: Fabian Bieler V2 [Chris]: Adjust meta.c as well to avoid undefined behavior. --- src/mesa/drivers/common/meta.c | 2 ++ src/mesa/main/mtypes.h | 8 +--- src/mesa/main/shaderobj.h | 4 src/mesa/program/prog_print.c | 6 ++ src/mesa/program/program.h | 8 ++

[Mesa-dev] [RFC PATCH 06/56] mesa/program: Add tessellation shader init functions.

From: Fabian Bieler V2 [Chris]: Fix rebase issues; helper previously used here no longer exists. Signed-off-by: Chris Forbes --- src/mesa/program/program.c | 32 src/mesa/program/program.h | 10 ++ 2 files changed, 42 insertions(+) diff --git a/src/mes

[Mesa-dev] [RFC PATCH 00/56] ARB_tessellation_shader for core mesa

This series adds all the driver-independent bits for ARB_tessellation_shader. It's not quite finished, and there are still a handful of ugly hacks to remove, but I think it's complete enough to start getting some review feedback. ___ mesa-dev mailing lis

[Mesa-dev] [RFC PATCH 01/56] mapi: Add ARB_tessellation_shader

From: Fabian Bieler V2 [Chris]: Remove display list support; we will only do tessellation shders in the core profile. --- src/mapi/glapi/gen/ARB_tessellation_shader.xml | 62 ++ src/mapi/glapi/gen/gl_API.xml | 6 ++- src/mapi/glapi/gen/gl_enums.py

Re: [Mesa-dev] [PATCH 41/41] SQUASH: i965/fs: Force a high register for the final FB write

On Saturday, September 20, 2014 01:56:11 PM Jason Ekstrand wrote: > On Sat, Sep 20, 2014 at 12:44 PM, Connor Abbott wrote: > > > On Sat, Sep 20, 2014 at 1:23 PM, Jason Ekstrand > > wrote: > > > --- > > > src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 24 > > ++- > > > s

Re: [Mesa-dev] [PATCH 41/41] SQUASH: i965/fs: Force a high register for the final FB write

On Sat, Sep 20, 2014 at 5:58 PM, Jason Ekstrand wrote: > > On Sep 20, 2014 2:52 PM, "Connor Abbott" wrote: >> >> On Sat, Sep 20, 2014 at 4:56 PM, Jason Ekstrand >> wrote: >> > >> > >> > On Sat, Sep 20, 2014 at 12:44 PM, Connor Abbott >> > wrote: >> >> >> >> On Sat, Sep 20, 2014 at 1:23 PM, Jaso

Re: [Mesa-dev] [PATCH 41/41] SQUASH: i965/fs: Force a high register for the final FB write

On Sep 20, 2014 2:52 PM, "Connor Abbott" wrote: > > On Sat, Sep 20, 2014 at 4:56 PM, Jason Ekstrand wrote: > > > > > > On Sat, Sep 20, 2014 at 12:44 PM, Connor Abbott wrote: > >> > >> On Sat, Sep 20, 2014 at 1:23 PM, Jason Ekstrand > >> wrote: > >> > --- > >> > src/mesa/drivers/dri/i965/brw_fs

Re: [Mesa-dev] [PATCH 41/41] SQUASH: i965/fs: Force a high register for the final FB write

On Sat, Sep 20, 2014 at 4:56 PM, Jason Ekstrand wrote: > > > On Sat, Sep 20, 2014 at 12:44 PM, Connor Abbott wrote: >> >> On Sat, Sep 20, 2014 at 1:23 PM, Jason Ekstrand >> wrote: >> > --- >> > src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 24 >> > ++- >> > src/mesa/dr

Re: [Mesa-dev] [PATCH 41/41] SQUASH: i965/fs: Force a high register for the final FB write

On Sat, Sep 20, 2014 at 12:44 PM, Connor Abbott wrote: > On Sat, Sep 20, 2014 at 1:23 PM, Jason Ekstrand > wrote: > > --- > > src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 24 > ++- > > src/mesa/drivers/dri/i965/intel_screen.h | 5 + > > 2 files changed,

[Mesa-dev] [Bug 84124] New: Please revert 8449121971ce1db03fea19665d314e523fdc10dd

https://bugs.freedesktop.org/show_bug.cgi?id=84124 Priority: medium Bug ID: 84124 Assignee: mesa-dev@lists.freedesktop.org Summary: Please revert 8449121971ce1db03fea19665d314e523fdc10dd Severity: normal Classification: Unclassified

Re: [Mesa-dev] [PATCH 41/41] SQUASH: i965/fs: Force a high register for the final FB write

On Sat, Sep 20, 2014 at 1:23 PM, Jason Ekstrand wrote: > --- > src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 24 > ++- > src/mesa/drivers/dri/i965/intel_screen.h | 5 + > 2 files changed, 28 insertions(+), 1 deletion(-) > > diff --git a/src/mesa/drivers/dr

Re: [Mesa-dev] [PATCH 00/41] Welcome back Matt!

One more quick note. If you find it nicer, the whole thing can be found here: http://cgit.freedesktop.org/~jekstrand/mesa/tree/?h=kill-mrf-v1 On Sat, Sep 20, 2014 at 10:22 AM, Jason Ekstrand wrote: > This series does a bunch of refactoring of the i965 fs backend IR to add > concepts of registe

[Mesa-dev] [PATCH 41/41] SQUASH: i965/fs: Force a high register for the final FB write

--- src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 24 ++- src/mesa/drivers/dri/i965/intel_screen.h | 5 + 2 files changed, 28 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_fs_reg

[Mesa-dev] [PATCH 35/41] i966/fs: Add a function for getting a component of a 8 or 16-wide register

--- src/mesa/drivers/dri/i965/brw_fs.h | 10 ++ 1 file changed, 10 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h index 491fc4d..fe450a8 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.h +++ b/src/mesa/drivers/dri/i965/brw_fs.h @@ -161,6

[Mesa-dev] [PATCH 38/41] i965/fs: Add a an optional source to the FS_OPCODE_FB_WRITE instruction

Previously, we were use the base_mrf parameter of fs_inst to store the MRF location. In preparation for doing FB writes from the GRF, we now also allow you to set inst->base_mrf to -1 and provide a source register. --- src/mesa/drivers/dri/i965/brw_eu.h | 4 +-- src/mesa/drivers/dri/

[Mesa-dev] [PATCH 36/41] i965/fs: Use the GRF for UNTYPED_ATOMIC instructions

--- src/mesa/drivers/dri/i965/brw_eu.h | 2 +- src/mesa/drivers/dri/i965/brw_eu_emit.c| 4 +-- src/mesa/drivers/dri/i965/brw_fs.cpp | 3 ++ src/mesa/drivers/dri/i965/brw_fs.h | 1 + src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 8 ++--- src/mesa/dr

[Mesa-dev] [PATCH 37/41] i965/fs: Use the GRF for UNTYPED_SURFACE_READ instructions

--- src/mesa/drivers/dri/i965/brw_fs.cpp | 3 +++ src/mesa/drivers/dri/i965/brw_fs.h | 1 + src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 7 --- src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 29 ++ 4 files changed, 24 insertions(+), 16 del

[Mesa-dev] [PATCH 40/41] i965/fs: Use the GRF for FB writes on gen >= 7

On gen 7, the MRF was removed and we gained the ability to do send instructions directly from the GRF. This commit enables that functinoality for FB writes. --- src/mesa/drivers/dri/i965/brw_fs.cpp | 4 + src/mesa/drivers/dri/i965/brw_fs.h | 1 + src/mesa/drivers/dri/i965/br

[Mesa-dev] [PATCH 39/41] i965/fs: Add split_virtual_grfs and compute_to_mrf after lower_load_payload

If we are going to use LOAD_PAYLOAD operations to fill MRF registers, then we will need this. --- src/mesa/drivers/dri/i965/brw_fs.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index 7f5b5a8..b971252 100644 --

[Mesa-dev] [PATCH 33/41] i965/fs: Use exec_size instead of force_uncompressed in dump_instruction

--- src/mesa/drivers/dri/i965/brw_fs.cpp | 13 - 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index e06e083..11f5323 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dr

[Mesa-dev] [PATCH 34/41] i965/fs: Use the instruction execution size directly for texture generation

Signed-off-by: Jason Ekstrand --- src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 13 ++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp index 00cf3ec..5b2eb31 100644 --- a/

[Mesa-dev] [PATCH 22/41] i965/fs: Fix a bug in register coalesce

This commit fixes a bug in register coalesce that happens when one register is moved to another the proper number of times but the channels are re-arranged. When this happens, the previous code would happily coalesce the registers regardless of the fact that the channel mappins were wrong. --- sr

[Mesa-dev] [PATCH 23/41] i965/fs: Determine partial writes based on the destination width

Now that we track both halves of a 16-wide vgrf, we no longer need to worry about force_sechalf or force_uncompressed. The only real issue is if the destination is too small. Signed-off-by: Jason Ekstrand --- src/mesa/drivers/dri/i965/brw_fs.cpp | 4 ++-- src/mesa/drivers/dri/i965/

[Mesa-dev] [PATCH 30/41] i965/fs: Remove unneeded uses of force_uncompressed

Signed-off-by: Jason Ekstrand --- src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h | 8 ++-- src/mesa/drivers/dri/i965/brw_fs.cpp | 22 +++--- src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 4 3 files changed, 9 insertions(+), 25 deletions(-) diff --git a/src/me

[Mesa-dev] [PATCH 27/41] i965/fs: Better guess the width of LOAD_PAYLOAD

--- src/mesa/drivers/dri/i965/brw_fs.cpp | 11 +-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index 6157c0c..bd11691 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/

[Mesa-dev] [PATCH 28/41] i965/fs: Make fs_reg::effective_width take fs_inst* instead of fs_visitor*

Now that we have execution sizes, we can use that instead of the dispatch width. This way it also works for 8-wide instructions in SIMD16. --- src/mesa/drivers/dri/i965/brw_fs.cpp | 10 +- src/mesa/drivers/dri/i965/brw_fs.h| 4 ++-- src/mesa/drivers/d

[Mesa-dev] [PATCH 29/41] i965/fs: Derive force_uncompressed from instruction exec_size

Signed-off-by: Jason Ekstrand --- src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp index d519a3a..bc607be 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_v

[Mesa-dev] [PATCH 24/41] i965/fs: Add an exec_size field to fs_inst

This will, eventually, allow us to manage execution sizes of instructions in a much more natural way from the fs_visitor level. Signed-off-by: Jason Ekstrand --- src/mesa/drivers/dri/i965/brw_fs.cpp | 69 +++- src/mesa/drivers/dri/i965/brw_fs.h | 18

[Mesa-dev] [PATCH 19/41] SQUASH: i965/fs: Properly handle register widths and odd register sizes in spilling

--- src/mesa/drivers/dri/i965/brw_fs.h| 2 + src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 48 --- 2 files changed, 35 insertions(+), 15 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h index 93d11d0..4b9

[Mesa-dev] [PATCH 32/41] i965/fs: Use instruction execution sizes instead of heuristics

Signed-off-by: Jason Ekstrand --- src/mesa/drivers/dri/i965/brw_fs.cpp | 19 --- src/mesa/drivers/dri/i965/brw_fs_live_variables.cpp | 10 +- .../drivers/dri/i965/brw_schedule_instructions.cpp| 4 +--- 3 files changed, 10 insertions(+), 23 deletions

[Mesa-dev] [PATCH 26/41] SQUASH: i965/blorp: Explicitly set instruction execute sizes

Since blorp is all 16-wide and nothing isn't, in general, very careful about register widtsh, we'll just set it all explicitly. --- src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp | 2 +- src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h | 32 - src/mesa/drivers/dri/i965/brw

[Mesa-dev] [PATCH 31/41] i965/fs: Use instruction execution sizes to set compression state

Signed-off-by: Jason Ekstrand --- src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 23 ++- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp index f20a4a7..00cf3ec 100

[Mesa-dev] [PATCH 25/41] SQUASH: i965/fs: Explicitly set instruction execute size a couple of places

--- src/mesa/drivers/dri/i965/brw_fs.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index f6c9b46..cd64f59 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -406,6

[Mesa-dev] [PATCH 07/41] SQUASH: i965/fs: Use the register width when applying offsets

This reworks both byte_offset() and offset() to be more intelligent. The byte_offset() funciton now supports offsets bigger than 32. The offset() function uses the byte_offset() function togehter with the register width and the type size to offset the register by the correct amount. --- src/mesa/

[Mesa-dev] [PATCH 17/41] SQUASH: i965/fs: Properly handle widths in copy propagation

--- src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp b/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp index 6344ff5..42b023a 100644 --- a/src/mesa/drivers/d

[Mesa-dev] [PATCH 16/41] SQUASH: i965/fs: Properly handle register widths in register_coalesce

--- src/mesa/drivers/dri/i965/brw_fs_register_coalesce.cpp | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_register_coalesce.cpp b/src/mesa/drivers/dri/i965/brw_fs_register_coalesce.cpp index d7966d2..a4abb88 100644 --- a/src/mesa/driver

[Mesa-dev] [PATCH 14/41] SQUASH: i965/fs: Make sources and destinations interfere in 16-wide

--- src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 24 +++ 1 file changed, 24 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp index f3f6ef4..f0b118f 100644 --- a/src/mesa/drivers/dri/i965/br

[Mesa-dev] [PATCH 21/41] i965/fs: Rework GEN5 texturing code to use fs_reg and offset()

Now that offset() can properly handle MRF registers, we can use an MRF fs_reg and let offset() handle incrementing it correctly for different dispatch widths. While this doesn't have any noticable effect currently, it does ensure that the destination register is 16-wide which will be necisary late

[Mesa-dev] [PATCH 18/41] SQUASH: i965/fs: Properly handle register widths in VARYING_PULL_CONSTANT_LOAD

--- src/mesa/drivers/dri/i965/brw_fs.cpp | 10 +++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index d954523..412c851 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i

[Mesa-dev] [PATCH 10/41] SQUASH: i965/fs: Properly handle register widths in LOAD_PAYLOAD

The LOAD_PAYLOAD instruction is a bit special because it collects a bunch of registers (with possibly different widths) into a single payload block. Once the payload is constructed, it's treated as a single block of data and most of the information such as register widths doesn't matter anymore. I

[Mesa-dev] [PATCH 03/41] i965/fs: Add a concept of a width to fs_reg

Every register in i965 assembly implicitly has a concept of a "width". Usually, this is derived from the execution size of the instruction. However, when writing a compiler it turns out that it is frequently a useful to have the width explicitly in the register and derive the execution size of the

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