This code should execute without regard to the currently executing
channels. Asking for gl_SampleID inside control flow might break in
strange ways. It appears to break even at the top of the program in
SIMD16 mode occasionally as well.
Signed-off-by: Kenneth Graunke
Cc: mesa-sta...@lists.freed
First of all, I think this should be two patches, one which adds the
helper and one which makes radeonsi use it.
On 16.07.2014 01:19, Tom Stellard wrote:
> diff --git a/src/gallium/auxiliary/util/u_math.h
> b/src/gallium/auxiliary/util/u_math.h
> index b9ed197..cd3cf04 100644
> --- a/src/gallium
https://bugs.freedesktop.org/show_bug.cgi?id=80615
Alexandre Demers changed:
What|Removed |Added
CC||deathsim...@vodafone.de,
On Monday, July 14, 2014 03:48:34 PM Ian Romanick wrote:
> From: Ian Romanick
>
> Previously we had to keep unreachable global symbols in the symbol table
> because the symbol table is used during linking. Having the symbol
> table retain pointers to freed memory... what could possibly go wrong?
https://bugs.freedesktop.org/show_bug.cgi?id=81139
Boyan Ding changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
Currently it indicates that this is never supported, but soon it will
be supported for gen8+.
Signed-off-by: Jordan Justen
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 10 ++
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 4
2 files changed, 14 insertions(+)
diff --git a/s
We now skip allocating a hiz miptree for gen8. Instead, we calculate
the required hiz buffer parameters and allocate a bo directly.
Signed-off-by: Jordan Justen
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 91 +++
1 file changed, 91 insertions(+)
diff --git a/src/
For gen8, we can sample from depth while using the hiz buffer. This
allows us to sample depth without resolving from hiz to the depth
texture.
To do this we must resolve to hiz before drawing so we can use the hiz
buffer to sample while rendering. Hopefully the hiz buffer will
already be resolved
For hiz, the qpitch may be different than the main miptree.
In "i965: Wrap MCS miptree in intel_miptree_aux_buffer" we set
aux_buf->qpitch to mt->qpitch, so for MCS, this should be a no-op.
Signed-off-by: Jordan Justen
---
src/mesa/drivers/dri/i965/gen8_surface_state.c | 4 ++--
1 file changed,
For gen8+ this will indicate when we should allow hiz based sampling
during rendering.
Signed-off-by: Jordan Justen
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/
This will allow us to treat HiZ and MCS the same when using them as
auxiliary surface buffers.
Signed-off-by: Jordan Justen
---
src/mesa/drivers/dri/i965/gen8_surface_state.c | 28 +-
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/src/mesa/drivers/dri/i96
We are still allocating a miptree for hiz, but we only use fields from
intel_miptree_aux_buffer. This will allow us to switch over to not
allocating a miptree.
Signed-off-by: Jordan Justen
Reviewed-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/gen7_blorp.cpp| 6 +++---
src/mesa/drivers
This will allow us to treat HiZ and MCS the same when using as an
auxiliary surface buffer.
Signed-off-by: Jordan Justen
---
src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 2 +-
src/mesa/drivers/dri/i965/gen7_blorp.cpp | 4 +-
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c |
GEN8_SURFACE_AUX_MODE_NONE is 0, so this is a no-op.
Yet, this also makes it clear that we can compare aux_mode to the
other GEN8_SURFACE_AUX_MODE_ values. We will want to compare to
GEN8_SURFACE_AUX_MODE_HIZ.
Signed-off-by: Jordan Justen
---
src/mesa/drivers/dri/i965/gen8_surface_state.c | 4 +
Today we allocate a miptree's for the hiz buffer. We needed this in
the past because we would point the hardware at offsets of the hiz
buffer. Since the hiz format is not documented, this is not a good
idea.
Since moving to support layered rendering on Gen7+, we no longer point
at an offset into t
We now skip allocating a hiz miptree for gen7. Instead, we calculate
the required hiz buffer parameters and allocate a bo directly.
Signed-off-by: Jordan Justen
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 95 ++-
1 file changed, 93 insertions(+), 2 deletions(-)
d
1. No longer allocate a miptree structure for hiz on gen7+. This was
previously sent out in the series: "i965 gen7+ hiz buffer change;
always enable gen8 hiz"
2. Always enable HiZ for depth on gen8+. (Also part of the previous
series.)
3. Enable HiZ Auxiliary Buffer support on gen8. This
After modifying the hiz buffer allocation and qpitch calculation, hiz
appears to work in all cases on gen8.
Signed-off-by: Jordan Justen
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tr
From: Kenneth Graunke
Signed-off-by: Kenneth Graunke
[jordan.l.jus...@intel.com: convert from aux_mt to aux_buf]
Signed-off-by: Jordan Justen
---
src/mesa/drivers/dri/i965/gen8_surface_state.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/gen
We are still allocating a miptree for hiz, but we only use fields from
intel_miptree_aux_buffer. This will allow us to switch over to not
allocating a miptree.
Signed-off-by: Jordan Justen
Reviewed-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/gen8_depth_state.c | 6 +++---
1 file changed,
https://bugs.freedesktop.org/show_bug.cgi?id=81174
--- Comment #14 from Roland Scheidegger ---
In my testing this seems to be *both* a core (vbo) and a draw problem.
With my piglit test the first error (without redrawing) appears with 4097
vertices - despite that the vbo code can handle 5460 (per
https://bugs.freedesktop.org/show_bug.cgi?id=80183
Roland Scheidegger changed:
What|Removed |Added
Component|Mesa core |Other
--- Comment #6 from Roland Sc
https://bugs.freedesktop.org/show_bug.cgi?id=80183
Roland Scheidegger changed:
What|Removed |Added
Component|Other |Mesa core
--- Comment #5 from Rolan
Series is
Reviewed-by: Matt Turner
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Hello,
The mesa/main support for ARB_gs5 is nearly ready, and I have the
various mesa/st patches all sent out. The last bit is the dynamic
sampler support which I think will Just Work in mesa/st once glsl lets
it through.
Most extensions are enabled on the basis of a PIPE_CAP_*, either it
being e
It doesn't handle things like (vector * matrix) correctly, and
apparently Matt's intention was to bail.
Fixes shader compilation in Natural Selection 2.
Signed-off-by: Kenneth Graunke
---
src/glsl/opt_rebalance_tree.cpp | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/
This helped me track down the bug fixed in the previous commit.
Signed-off-by: Kenneth Graunke
---
src/glsl/opt_rebalance_tree.cpp | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/glsl/opt_rebalance_tree.cpp b/src/glsl/opt_rebalance_tree.cpp
index 7ef0d2d..f82b16b 10064
components() includes matrix columns, so if this code encountered a
matrix, it would ask for something like a vec9 or vec16. This is
clearly not what you want.
Earlier code now prevents this from seeing matrices, but we should still
use vector_elements, for clarity.
Signed-off-by: Kenneth Graunk
So, a little update on these patches.
I've written some shaders for hitting each
specific case in the patch-series.
This shows that:
Patch 1 (X - X) == 0,and
Patch 9 (A - neg(B)) == A + B
have no effect at all.
The rest of the patches do indeed have
a positive effect on the special-case shade
I agree, agree, and agree. We do indeed have a neg( neg() ) pass.
Writing a shader similar to the one you suggest gives clean A + B
with current master due to this, so this patch will do no good.
2014-07-15 19:05 GMT+02:00 Ian Romanick :
> I haven't really looked at the other patches yet, but the
Michel Dänzer writes:
>> configurations are. All I need is something along the lines of:
>>
>> "The radeon team is OK with releasing commit "
...
[snip of the rest of my proposal]
> This sounds good, but...
Good! Thanks for reading this and giving me some feedback.
>> An
On 07/15/2014 01:14 PM, Matt Turner wrote:
Reported-by: Brian Paul
---
src/glsl/list.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/glsl/list.h b/src/glsl/list.h
index 3cc48ce..3ee6cda 100644
--- a/src/glsl/list.h
+++ b/src/glsl/list.h
@@ -411,9 +411,9 @@ static
Reported-by: Brian Paul
---
src/glsl/list.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/glsl/list.h b/src/glsl/list.h
index 3cc48ce..3ee6cda 100644
--- a/src/glsl/list.h
+++ b/src/glsl/list.h
@@ -411,9 +411,9 @@ static inline unsigned
exec_list_length(const struct
On Mon, Jun 2, 2014 at 3:00 AM, Pohjolainen, Topi
wrote:
> On Thu, May 29, 2014 at 01:53:53PM -0700, Jordan Justen wrote:
>> Since gen6 stencil only supports LOD0, we need to program an offset to
>> the LOD when emitting the stencil/hiz.
>>
>> Signed-off-by: Jordan Justen
>> ---
>> src/mesa/driv
On Tue, Jul 8, 2014 at 12:20 PM, Connor Abbott wrote:
> This series adds a couple things I need to exec_list for my work, and
> does some cleanups made possible. Only compile tested on i965.
>
> Connor Abbott (3):
> exec_list: add a prepend function
> exec_list: add a function to count the siz
On Tue, Jul 15, 2014 at 10:56 AM, Ian Romanick wrote:
> From: Ian Romanick
>
> brw_inst.h: In function 'brw_inst_set_src1_vstride':
> brw_inst.h:118:76: warning: unused parameter 'brw' [-Wunused-parameter]
>
> Signed-off-by: Ian Romanick
> ---
> src/mesa/drivers/dri/i965/brw_inst.h | 10 +++
On Sunday, July 13, 2014 01:52:00 PM Chris Forbes wrote:
> Signed-off-by: Chris Forbes
> ---
> src/glsl/lower_ubo_reference.cpp | 50
> 1 file changed, 30 insertions(+), 20 deletions(-)
>
> diff --git a/src/glsl/lower_ubo_reference.cpp
b/src/glsl/lower_
On Tuesday, July 15, 2014 10:28:07 PM Chris Forbes wrote:
> Accidentally replied privately only, sorry.
>
> -- Forwarded message --
> From: Chris Forbes
> Date: Tue, Jul 15, 2014 at 10:27 PM
> Subject: Re: [Mesa-dev] [PATCH 2/6] glsl: Mark entire UBO array active
> if indexed with
From: Ian Romanick
Signed-off-by: Ian Romanick
---
src/glsl/ast_to_hir.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp
index 885bee5..888f5ec 100644
--- a/src/glsl/ast_to_hir.cpp
+++ b/src/glsl/ast_to_hir.cpp
@@ -5137,7 +
These are just some warning clean ups that I made while doing other
work. I was going to send them with the other work, but that series is
taking longer (and getting longer) than I had hoped.
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From: Ian Romanick
brw_inst.h: In function 'brw_inst_set_src1_vstride':
brw_inst.h:118:76: warning: unused parameter 'brw' [-Wunused-parameter]
Signed-off-by: Ian Romanick
---
src/mesa/drivers/dri/i965/brw_inst.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/src/mesa/drivers/
From: Ian Romanick
brw_fs_visitor.cpp:2400:1: warning: unused parameter 'ir' [-Wunused-parameter]
Signed-off-by: Ian Romanick
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src
From: Ian Romanick
The parameter is an int16_t, and we're check that it's value will fit in
16-bits. Yes, the value that is stored in 16-bits will surely fit in
16-bits.
brw_inst.h: In function 'brw_inst_set_gen6_jump_count':
brw_inst.h:321:66: warning: comparison is always true due to limited
On Mon, Jul 14, 2014 at 3:48 PM, Ian Romanick wrote:
> Most of these patches have been sent to the list already in one form or
> another. There are a few changes, removals, and additions. The series
> has also been re-ordered.
>
> - The extra memory accounting code has been removed. This was su
I haven't really looked at the other patches yet, but the subject of
this one caught my eye.
I'm not sure this is useful. I believe we lower A-B to A+neg(B) for all
architectures. I'm pretty sure we also already have a pass that
converts A+neg(neg(B)) to A+B. Did you write any shaders to try to
On Tue, Jul 15, 2014 at 11:19 AM, Tom Stellard
wrote:
> ---
> src/gallium/auxiliary/util/u_math.h | 22 ++
> src/gallium/drivers/radeonsi/si_shader.c | 8 +---
> 2 files changed, 23 insertions(+), 7 deletions(-)
>
> diff --git a/src/gallium/auxiliary/util/u_math.h
>
https://bugs.freedesktop.org/show_bug.cgi?id=81174
--- Comment #13 from Roland Scheidegger ---
(In reply to comment #12)
> (In reply to comment #9)
> > (In reply to comment #8)
> > > Line loops aren't so critical, since they are rarely used. But what about
> > > triangle strips... every split kil
The is used for programs that have arrays of constants that
are accessed using dynamic indices. The shader will compute
the base address of the constants and then access them using
SMRD instructions.
---
src/gallium/drivers/radeon/r600_pipe_common.h | 5 +
src/gallium/drivers/radeon/radeon_e
---
src/gallium/auxiliary/util/u_math.h | 22 ++
src/gallium/drivers/radeonsi/si_shader.c | 8 +---
2 files changed, 23 insertions(+), 7 deletions(-)
diff --git a/src/gallium/auxiliary/util/u_math.h
b/src/gallium/auxiliary/util/u_math.h
index b9ed197..cd3cf04 100644
https://bugs.freedesktop.org/show_bug.cgi?id=81174
--- Comment #12 from Marek Olšák ---
(In reply to comment #9)
> (In reply to comment #8)
> > Line loops aren't so critical, since they are rarely used. But what about
> > triangle strips... every split kills 2 triangles...
>
> That shouldn't hap
https://bugs.freedesktop.org/show_bug.cgi?id=81174
--- Comment #11 from Marek Olšák ---
(In reply to comment #10)
> What I don't understand yet is why the effect is not stable (if my example
> is repainted several times, the wrap appears at different positions over
> time).
The wrap is done when
On Tue, Jul 15, 2014 at 11:53 AM, Michel Dänzer wrote:
> On 13.07.2014 01:35, Marek Olšák wrote:
>>
>> Border colors have been broken if texturing from multiple shader stages is
>> used. This patch doesn't change that.
>
> [...]
>
>> +/* Upload border colors and update the pointers in resource des
Before, we always reported zeros in the multisample columns of the
format list. Since PIXELFORMATDESCRIPTOR doesn't have fields for
multisample, we use a new format_info structure to extend that type.
We can only query this info with the wglGetPixelFormatAttribivARB()
function which is part of th
---
src/wgl/wglinfo.c |8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/wgl/wglinfo.c b/src/wgl/wglinfo.c
index 22d8d64..f628768 100644
--- a/src/wgl/wglinfo.c
+++ b/src/wgl/wglinfo.c
@@ -347,9 +347,9 @@ print_visual_attribs_verbose(int iPixelFormat, const struct
---
src/wgl/wglinfo.c |7 +++
1 file changed, 7 insertions(+)
diff --git a/src/wgl/wglinfo.c b/src/wgl/wglinfo.c
index 16008d2..22d8d64 100644
--- a/src/wgl/wglinfo.c
+++ b/src/wgl/wglinfo.c
@@ -334,6 +334,13 @@ print_visual_attribs_verbose(int iPixelFormat, const
struct format_info *inf
---
src/wgl/wglinfo.c | 59 +++---
src/xdemos/glinfo_common.c | 68 +++
src/xdemos/glinfo_common.h | 25 +
src/xdemos/glxinfo.c | 85
4 files changed, 113 inserti
As with glxinfo, we first report version/extension info for a compatibility
profile context, then report version/extension info for a core profile
context.
---
src/wgl/wglinfo.c | 134 +---
src/xdemos/glinfo_common.h | 24
src/xdemos/glx
On 07/15/2014 05:28 AM, Ilia Mirkin wrote:
On Wed, Jul 9, 2014 at 9:06 AM, Brian Paul wrote:
On 07/08/2014 08:40 PM, Ilia Mirkin wrote:
Signed-off-by: Ilia Mirkin
---
With ChrisF's patches to add support for this in core mesa, this generates
code like:
FRAG
DCL OUT[0], COLOR
DCL CONST[0]
D
On Wed, Jul 9, 2014 at 9:06 AM, Brian Paul wrote:
> On 07/08/2014 08:40 PM, Ilia Mirkin wrote:
>>
>> Signed-off-by: Ilia Mirkin
>> ---
>>
>> With ChrisF's patches to add support for this in core mesa, this generates
>> code like:
>>
>> FRAG
>> DCL OUT[0], COLOR
>> DCL CONST[0]
>> DCL CONST[1][0]
On Tue, Jul 15, 2014 at 6:28 AM, Chris Forbes wrote:
> Accidentally replied privately only, sorry.
>
> -- Forwarded message --
> From: Chris Forbes
> Date: Tue, Jul 15, 2014 at 10:27 PM
> Subject: Re: [Mesa-dev] [PATCH 2/6] glsl: Mark entire UBO array active
> if indexed with non-
On Sat, Jul 12, 2014 at 9:51 PM, Chris Forbes wrote:
> This series adds various relaxations and extra plumbing to allow indexing
> arrays of uniform blocks with dynamically uniform expressions rather than
> only constant expressions.
>
> Covers only the GLSL part -- there are still a few loose end
Oh dear. This hunk should have been squashed together with the change
to it later. By itself, it doesn't get us anywhere.
On Tue, Jul 15, 2014 at 10:26 PM, Ilia Mirkin wrote:
> On Sat, Jul 12, 2014 at 9:51 PM, Chris Forbes wrote:
>> Instead of falling back to just the block name (which we won't
Indeed, will fix.
On Tue, Jul 15, 2014 at 10:24 PM, Ilia Mirkin wrote:
> On Sat, Jul 12, 2014 at 9:51 PM, Chris Forbes wrote:
>> Previously this was a block index with special semantics for -1.
>> With ARB_gpu_shader5, this need not be a compile-time constant, so
>> allow any rvalue here and con
Accidentally replied privately only, sorry.
-- Forwarded message --
From: Chris Forbes
Date: Tue, Jul 15, 2014 at 10:27 PM
Subject: Re: [Mesa-dev] [PATCH 2/6] glsl: Mark entire UBO array active
if indexed with non-constant.
To: Ilia Mirkin
On Tue, Jul 15, 2014 at 10:20 PM, Ilia
On Sat, Jul 12, 2014 at 9:51 PM, Chris Forbes wrote:
> Instead of falling back to just the block name (which we won't find),
> look for the first element of the block array. We'll deal with the rest
> in the backend by arranging for the blocks to be laid out contiguously.
>
> Signed-off-by: Chris
On Sat, Jul 12, 2014 at 9:51 PM, Chris Forbes wrote:
> Previously this was a block index with special semantics for -1.
> With ARB_gpu_shader5, this need not be a compile-time constant, so
> allow any rvalue here and convert the -1 to a NULL pointer.
>
> Signed-off-by: Chris Forbes
> ---
> src/g
On Sat, Jul 12, 2014 at 9:51 PM, Chris Forbes wrote:
> Without doing a lot more work, we have no idea which indices may
> be used at runtime, so just mark them all.
>
> Signed-off-by: Chris Forbes
> ---
> src/glsl/link_uniform_block_active_visitor.cpp | 51
> --
> 1 file
Hello.
I am using Mesa with EGL platform FBDEV. In this setup the
native_window is always NULL.
It worked good, but after update to new version of Mesa it shows error
in creating EGLsurface.
I tracked it down to commit 91ff0d4c6510dc38f279c586ced17fba917873e7
egl: Check for NULL native_window in
On 13.07.2014 01:35, Marek Olšák wrote:
>
> Border colors have been broken if texturing from multiple shader stages is
> used. This patch doesn't change that.
[...]
> +/* Upload border colors and update the pointers in resource descriptors.
> + * There can only be 4096 border colors per context.
On Tue, Jul 15, 2014 at 2:18 AM, Michel Dänzer wrote:
> On 09.07.2014 08:10, Carl Worth wrote:
>>
>> 3. I'd like to receive a testing report from each driver team
>>
>> This is the meat of my proposal. I'm requesting that each driver
>> team designate one (or more) people that will b
https://bugs.freedesktop.org/show_bug.cgi?id=80266
Eero Tamminen changed:
What|Removed |Added
URL||http://blog.llvm.org/2011/0
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