TGSI_TEXTURE_BUFFER is one-dimensional. Assert that exec_tex() is never
called with TGSI_TEXTURE_BUFFER.
Signed-off-by: Chia-I Wu
---
src/gallium/auxiliary/tgsi/tgsi_exec.c |1 +
src/gallium/auxiliary/tgsi/tgsi_util.c |2 ++
2 files changed, 3 insertions(+)
diff --git a/src/gallium/aux
need_flush was uninitialized if hw3d->new_batch was true.
Fixes "Uninitialized scalar variable" defect reported by Coverity.
Signed-off-by: Vinson Lee
---
src/gallium/drivers/ilo/ilo_3d.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/ilo/ilo_3d.c b/src/
Michel Dänzer writes:
>> > For packed formats such as RGBA, the order used in these patches
>> > (which is what I suggested in my proposal) matches the order humans use
>> > for digits of numbers, as well as the Mesa formats. That seems more
>> > important to me than 'matching' any non-packed
On Thu, May 23, 2013 at 11:00 AM, Jordan Justen wrote:
> On Wed, May 22, 2013 at 3:56 PM, Eric Anholt wrote:
>> Jordan Justen writes:
>>> - surf[0] = BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
>>> + switch (gl_target) {
>>> + case GL_TEXTURE_CUBE_MAP_ARRAY:
>>> + case GL_TEXTURE_CUBE_MAP
On Wed, May 22, 2013 at 3:56 PM, Eric Anholt wrote:
> Jordan Justen writes:
>> - surf[0] = BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
>> + switch (gl_target) {
>> + case GL_TEXTURE_CUBE_MAP_ARRAY:
>> + case GL_TEXTURE_CUBE_MAP:
>> + surftype = BRW_SURFACE_2D;
>> + is_array = tru
Paul Berry writes:
> This series implements fast color clears, a Gen7+ feature which
> reduces memory bandwidth by deferring the memory writes involved in a
> glClear() until the same memory is later touched during rendering.
Comparing the branchpoint from master to the end of the series on my
I
https://bugs.freedesktop.org/show_bug.cgi?id=64877
Aaron Watry changed:
What|Removed |Added
Summary|R600 OpenCL Regression |R600: OpenCL Regression
https://bugs.freedesktop.org/show_bug.cgi?id=64877
--- Comment #5 from Aaron Watry ---
Think I found the commit in LLVM that broke things for me:
clang version used: aa3cef411387d1c (svn: 180748)
mesa: 1d09a8c3cdf02ed2c1
b6379de427c009284d47c5fc764f11bbd2bf2484 is the first bad commit
commit b6
https://bugs.freedesktop.org/show_bug.cgi?id=64590
Rafael Castillo changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
https://bugs.freedesktop.org/show_bug.cgi?id=64590
--- Comment #2 from Rafael Castillo ---
it did, omg i forgot to close the bug report
thanks
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https://bugs.freedesktop.org/show_bug.cgi?id=64590
--- Comment #1 from Chí-Thanh Christopher Nguyễn ---
Supposedly this is fixed since
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ff256ec0686bad0ccf3c9df99ba442773efbc181
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Paul Berry writes:
> diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
> b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
> index 9d1b91a..657532f 100644
> --- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
> @@ -1163,6 +1163,53 @
Jordan Justen writes:
> Signed-off-by: Jordan Justen
> ---
> src/mesa/main/texformat.c | 13 +
> src/mesa/main/texformat.h |2 ++
> 2 files changed, 15 insertions(+)
>
> diff --git a/src/mesa/main/texformat.c b/src/mesa/main/texformat.c
> index ed40b7e..a7df868 100644
> --- a/
Jordan Justen writes:
> Rather than pointing the surface_state directly at a single
> sub-image of the texture for rendering, we now point the
> surface_state at the top level of the texture, and configure
> the surface_state as needed based on this.
Thanks, this looks way better.
> @@ -550,7 +
https://bugs.freedesktop.org/show_bug.cgi?id=64877
--- Comment #4 from Aaron Watry ---
I've gone one step further and verified that the issue exists in:
llvm: e5c8c24ed5 (svn: 181222)
clang: c2fc4ab28c1 (svn: 181272)
drm: 8a88e349975a
mesa: 1d09a8c3cdf02ed2c1
kernel: 3.9.0
video: Radeon 5400 (ced
On Tue, May 21, 2013 at 04:34:51PM +0200, Vincent Lejeune wrote:
For the series:
Reviewed-by: Tom Stellard
> ---
> src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
Chris Forbes writes:
> Enables guardband clipping when the viewport covers the entire render
> target.
>
> No piglit regressions on Ironlake.
Reviewed-by: Eric Anholt
pgp8ilTi3Abfi.pgp
Description: PGP signature
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https://bugs.freedesktop.org/show_bug.cgi?id=41787
Roland Scheidegger changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
https://bugs.freedesktop.org/show_bug.cgi?id=64877
--- Comment #3 from Aaron Watry ---
Note that this is the first mesa commit that shows the issue.
The LLVM_REVISION.txt was bumped from LLVM revision 180753 to revision
181223... which means that it could've been an LLVM R600 change anywhere i
On 05/21/2013 04:52 PM, Paul Berry wrote:
Since we defer allocation of the MCS miptree until the time of the
fast clear operation, this patch also implements creation of the MCS
miptree.
In addition, this patch adds the field
intel_mipmap_tree::fast_clear_color_value, which holds the most recent
Ian Romanick writes:
> On 05/21/2013 06:11 PM, Eric Anholt wrote:
>> i965 and radeon use ra_set_node_reg() to force payload registers to
>> specific registers while exposing those registers to the allocator still.
>> We were treating those register nodes as unsuccessfully allocated in the
>> ra_s
On 05/21/2013 04:52 PM, Paul Berry wrote:
This patch ifdefs out intel_mipmap_tree::mcs_mt when building the i915
(pre-Gen4) driver (MCS buffers aren't supported until Gen7, so there
is no need for this field in the i915 driver). This should make it a
bit easier to implement fast color clears wit
On 05/21/2013 06:11 PM, Eric Anholt wrote:
We were expanding the live range too far, breaking register_coalesce_2()
and compute_to_mrf() on 16-wide shaders. Turning it back on improves
GLB2.7 performance by 0.239355% +/- 0.0850649% (n=398), though some
16-wide shaders are lost. shader-db stats
Patches 1 and 2 are
Reviewed-by: Ian Romanick
I had comments on 3 and 5.
On 05/21/2013 06:11 PM, Eric Anholt wrote:
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 8
1 file changed, 8 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src/mesa/drivers/
On 05/21/2013 06:11 PM, Eric Anholt wrote:
i965 and radeon use ra_set_node_reg() to force payload registers to
specific registers while exposing those registers to the allocator still.
We were treating those register nodes as unsuccessfully allocated in the
ra_simplify() step, leading to walking
Other than Eric's formatting nits in patch 2, the series is
Reviewed-by: Ian Romanick
On 05/13/2013 09:42 AM, Marek Olšák wrote:
to match the size of ctx->Texture.Unit, and it will also fix
piglit/max-samplers with the following commit.
---
src/mesa/swrast/s_context.c |6 +++---
src/mes
https://bugs.freedesktop.org/show_bug.cgi?id=64877
--- Comment #2 from Aaron Watry ---
Currently, I can reproduce the bug with the following components (all current
within the last hour):
llvm: e67c9c341f18a4 (svn: 182405)
clang: 097e0a2cb08 (svn: 182406)
drm: 8a88e349975a
mesa: ff68f61bedc2
kern
https://bugs.freedesktop.org/show_bug.cgi?id=64877
--- Comment #1 from vincent ---
What is your llvm HEAD ?
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On 05/16/2013 05:44 PM, Jordan Justen wrote:
With this change we now support interface block arrays.
For example, cases like this:
out block_name {
float f;
} block_instance[2];
This allows Mesa to pass the piglit glsl-1.50 test:
* execution/interface-blocks-complex-vs-fs.shader_test
Sign
https://bugs.freedesktop.org/show_bug.cgi?id=64877
Aaron Watry changed:
What|Removed |Added
Assignee|dri-devel@lists.freedesktop |mesa-dev@lists.freedesktop.
On 05/16/2013 05:44 PM, Jordan Justen wrote:
git://people.freedesktop.org/~jljusten/mesa interface-blocks-v4
v4:
* Incorporated Ken's feedback from v3.
* 9 of 17 patch now have r-b
- Missing r-b on 6-8, 10 & 14-17
Patches 1-14 are:
Reviewed-by: Kenneth Graunke
I just sent out propose
From: Jordan Justen
Verify that interface blocks match when combining compilation
units at the same stage. (For example, when merging all vertex
shaders.)
Fixes piglit glsl-1.50 test:
* linker/interface-blocks-multiple-vs-member-count-mismatch.shader_test
v5 (Ken): Rename to link_interface_bloc
Verify that interface blocks match when linking separate shader
stages into a program.
Fixes piglit glsl-1.50 tests:
* linker/interface-blocks-vs-fs-member-count-mismatch.shader_test
* linker/interface-blocks-vs-fs-member-order-mismatch.shader_test
Signed-off-by: Kenneth Graunke
Signed-off-by: J
On 05/16/2013 05:44 PM, Jordan Justen wrote:
Verify that interface blocks match when combining compilation
units at the same stage. (For example, when merging all vertex
shaders.)
Fixes piglit glsl-1.50 test:
* linker/interface-blocks-multiple-vs-member-count-mismatch.shader_test
Signed-off-by:
On 05/16/2013 05:44 PM, Jordan Justen wrote:
Verify that interface blocks match when linking separate shader
stages into a program.
Fixes piglit glsl-1.50 tests:
* linker/interface-blocks-vs-fs-member-count-mismatch.shader_test
* linker/interface-blocks-vs-fs-member-order-mismatch.shader_test
S
On 05/21/2013 06:11 PM, Eric Anholt wrote:
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 8
1 file changed, 8 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index b7bbaab..36d9cf0 100644
--- a/src/mesa/driv
On 05/21/2013 03:10 PM, Alexander von Gluck IV wrote:
* We generate a static library for Haiku
Gallium targets as our port system combines
the compiled rendering code into a modular
ar for each module (for example, our port
system combines llvm libsoftpipe.a libllvmpipe.a
into a si
https://bugs.freedesktop.org/show_bug.cgi?id=60518
--- Comment #2 from cor...@gmx.net ---
A workaround for the segfault is to explicitly disable vertex attribute arrays:
GLint n = 0;
glGetIntegerv(GL_MAX_VERTEX_ATTRIBS, &n);
for (GLint i = 0; i < n; ++i)
glDisableVertexAttribArray(i);
Which i
Roland,
Series looks good AFAICT. Thanks for nailing this nasty and long standing
issues.
- Original Message -
> On Tue, May 21, 2013 at 6:12 PM, wrote:
> > From: Roland Scheidegger
> >
> > This optimization disabled mask checks if the shader is simple enough.
> > While this should wo
Hi,
if I get the egl specs correctly then shouldn't querying these
attributes return the maximum supported pbuffer size? Does 0 mean the
size is unlimited or is it a bug in mesa egl implementation.
I am using mesa version 8.
Thanks & Regards,
Divick
___
On Mit, 2013-05-22 at 01:56 -0700, Jose Fonseca wrote:
> - Original Message -
> > On Die, 2013-05-21 at 23:15 -0700, Jose Fonseca wrote:
> > > - Original Message -
> > > > Jose Fonseca writes:
> > > > > - Original Message -
> > > > >> From: Richard Sandiford
> > > > >>
>
Enables guardband clipping when the viewport covers the entire render
target.
No piglit regressions on Ironlake.
Signed-off-by: Chris Forbes
---
src/mesa/drivers/dri/i965/brw_clip_state.c | 48 --
1 file changed, 45 insertions(+), 3 deletions(-)
diff --git a/src/mes
- Original Message -
> On Die, 2013-05-21 at 23:15 -0700, Jose Fonseca wrote:
> >
> > - Original Message -
> > > Jose Fonseca writes:
> > > > - Original Message -
> > > >> From: Richard Sandiford
> > > >>
> > > >> RGBA has R at byte 0 and A at byte 3, regardless of
On Die, 2013-05-21 at 23:15 -0700, Jose Fonseca wrote:
>
> - Original Message -
> > Jose Fonseca writes:
> > > - Original Message -
> > >> From: Richard Sandiford
> > >>
> > >> RGBA has R at byte 0 and A at byte 3, regardless of platform
> > >> endianness.
> > >
> > > Maybe
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