Re: [Mesa-dev] [PATCH 0/2] Patches to try to fix draw-pixel-with-textures in swrast

2011-11-17 Thread Yuanhan Liu
On Fri, Nov 18, 2011 at 03:38:46PM +0800, Yuanhan Liu wrote: > > The two patches tries to fix an issue that happened while calling glDrawPixels > with texture enabled. > > Here I attached a piglit testcase for this issue. > > > > > Yuanhan Liu (2): > swrast: simplify the prototype of funct

[Mesa-dev] [PATCH 2/2] swrast: fix unmatched span->array->ChanType

2011-11-17 Thread Yuanhan Liu
texture_combine converts the result rgba to CHAN_TYPE from FLOAT. At the same time, make sure the span->array->ChanType is changed, too. Signed-off-by: Yuanhan Liu --- src/mesa/swrast/s_texcombine.c |5 + 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/src/mesa/swrast/s_te

[Mesa-dev] [PATCH 1/2] swrast: simplify the prototype of function texture_combine

2011-11-17 Thread Yuanhan Liu
Parameter n and rgbaChan are both from structure span, thus using span as paramter to simplify the prototype. Function texture_combine is only used by _swrast_texture_span, so I guess it's safe to do so. This patch is mainly for the next patch. Signed-off-by: Yuanhan Liu --- src/mesa/swrast/s_t

[Mesa-dev] [PATCH 0/2] Patches to try to fix draw-pixel-with-textures in swrast

2011-11-17 Thread Yuanhan Liu
The two patches tries to fix an issue that happened while calling glDrawPixels with texture enabled. Here I attached a piglit testcase for this issue. Yuanhan Liu (2): swrast: simplify the prototype of function texture_combine swrast: fix unmatched span->array->ChanType src/mesa/swrast

[Mesa-dev] [PATCH 38/41] i965: Implement the actual tables for texture alignment units.

2011-11-17 Thread Chad Versace
From: Kenneth Graunke I implemented functions for horizontal/vertical alignment units separately because I find it easier to read that way...especially with all the corner-cases. [chad] Cherry picked from commit 9babf8ae308223e70f7c867076a5d62f2cd70a32 branch valign git://git.freedes

[Mesa-dev] [PATCH 41/41] i965: Document where Piglit test glean/fbo breaks due to HiZ

2011-11-17 Thread Chad Versace
I found the line of code that breaks the test, but don't know how to easily fix it. Signed-off-by: Chad Versace --- src/mesa/drivers/dri/i965/brw_context.c |3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i

[Mesa-dev] [PATCH 40/41] i965/gen6: Enable HiZ by default

2011-11-17 Thread Chad Versace
Regresses one Piglit test: glean/fbo. I'm not enabling HiZ for gen7 yet because it causes a mysterious performance regression. Signed-off-by: Chad Versace --- src/mesa/drivers/dri/intel/intel_screen.c |8 ++-- 1 files changed, 2 insertions(+), 6 deletions(-) diff --git a/src/mesa/drive

[Mesa-dev] [PATCH 39/41] intel: Use separate stencil whenever possible

2011-11-17 Thread Chad Versace
For depthstencil renderbuffers, we were using separate stencil only if the hardware required it. Since the performance gains from HiZ is so high, we should always use separate stencil if the hardware supports it. Signed-off-by: Chad Versace --- src/mesa/drivers/dri/intel/intel_fbo.c |2 +- 1

[Mesa-dev] [PATCH 37/41] i965: Set vertical alignment in SURFACE_STATE batch

2011-11-17 Thread Chad Versace
Signed-off-by: Chad Versace --- src/mesa/drivers/dri/i965/brw_defines.h |9 + src/mesa/drivers/dri/i965/brw_wm_surface_state.c |8 ++-- 2 files changed, 11 insertions(+), 6 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH 36/41] intel: Store miptree alignment units in the miptree

2011-11-17 Thread Chad Versace
This allows us to replace all the calls to intel_get_texture_alignment_unit() with a single call at miptree creation. Signed-off-by: Chad Versace --- src/mesa/drivers/dri/i965/brw_tex_layout.c | 26 +++ src/mesa/drivers/dri/intel/intel_mipmap_tree.c |9 +++ src/

[Mesa-dev] [PATCH 35/41] intel: Enable HiZ for texture renderbuffers

2011-11-17 Thread Chad Versace
When a depth texture is first attached to framebuffer, allocate a HiZ miptree for it. Signed-off-by: Chad Versace --- src/mesa/drivers/dri/intel/intel_fbo.c |7 +++ 1 files changed, 7 insertions(+), 0 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/d

[Mesa-dev] [PATCH 34/41] intel: Resolve buffers in intel_map_renderbuffer()

2011-11-17 Thread Chad Versace
Signed-off-by: Chad Versace --- src/mesa/drivers/dri/intel/intel_fbo.c |5 + 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c index 5b2a7ac..0b6b227 100644 --- a/src/mesa/drivers/dri/intel/intel

[Mesa-dev] [PATCH 33/41] intel: Resolve buffers in intel_map_texture_image()

2011-11-17 Thread Chad Versace
Signed-off-by: Chad Versace --- src/mesa/drivers/dri/intel/intel_tex.c |5 + 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_tex.c b/src/mesa/drivers/dri/intel/intel_tex.c index 505e617..9884a57 100644 --- a/src/mesa/drivers/dri/intel/intel

[Mesa-dev] [PATCH 32/41] intel: Mark needed resolves when first enabling HiZ on a miptree

2011-11-17 Thread Chad Versace
Signed-off-by: Chad Versace --- src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 21 - 1 files changed, 20 insertions(+), 1 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c index 3540997..9ebeefc 1006

[Mesa-dev] [PATCH 31/41] i965: Mark that depth buffer needs depth resolve after drawing

2011-11-17 Thread Chad Versace
After brw_try_draw_prims() emits a batch, mark that the depth buffer needs a depth resolve if the buffer was written to and if it has an accompanying HiZ buffer. Signed-off-by: Chad Versace --- src/mesa/drivers/dri/i965/brw_draw.c | 23 +++ 1 files changed, 23 insertions(+)

[Mesa-dev] [PATCH 30/41] intel: Resolve buffers in intelSpanRenderStart

2011-11-17 Thread Chad Versace
Resolve all buffers that will be mapped by intelSpanRenderStart. This comprises resolving the depth buffer of each enabled texture and of the read and draw buffers. Signed-off-by: Chad Versace --- src/mesa/drivers/dri/intel/intel_span.c | 40 ++- 1 files changed, 39

[Mesa-dev] [PATCH 29/41] intel: Refactor intelSpanRenderStart

2011-11-17 Thread Chad Versace
Factor the mapping loops from intelSpanRenderStart() into intel_span_map_buffers(). This in preparation for the next commit, which resolves the buffers before mapping. Signed-off-by: Chad Versace --- src/mesa/drivers/dri/intel/intel_span.c | 41 +++ 1 files changed,

[Mesa-dev] [PATCH 28/41] i965: Resolve buffers before drawing

2011-11-17 Thread Chad Versace
Before emitting primitives in brw_try_draw_prims(), resolve the depth buffer's HiZ buffer and resolve the depth buffer of each enabled depth texture. Signed-off-by: Chad Versace --- src/mesa/drivers/dri/i965/brw_draw.c | 73 ++ 1 files changed, 73 insertions(+),

[Mesa-dev] [PATCH 27/41] i965: Prevent recursive calls to FLUSH_VERTICES

2011-11-17 Thread Chad Versace
To do so, we must resolve all buffers on entering a glBegin/glEnd block. For the detailed explanation, see the Doxygen comments in this patch. Signed-off-by: Chad Versace --- src/mesa/drivers/dri/i965/brw_context.c | 73 +++ 1 files changed, 73 insertions(+), 0 dele

[Mesa-dev] [PATCH 26/41] i965/gen6: Manipulate state batches for HiZ meta-ops

2011-11-17 Thread Chad Versace
A lot of the state manipulation is handled by the meta-op state setup. However, some batches need manual intervention. Signed-off-by: Chad Versace --- src/mesa/drivers/dri/i965/brw_draw.c |9 - src/mesa/drivers/dri/i965/gen6_clip_state.c | 17 + src/mesa/

[Mesa-dev] [PATCH 25/41] i965/gen6: Complete stubs for HiZ buffer resolves

2011-11-17 Thread Chad Versace
Some state batches also need to be manipulated. That's done in the next commit. Signed-off-by: Chad Versace --- src/mesa/drivers/dri/i965/gen6_hiz.c | 305 +- 1 files changed, 303 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen6_hiz.c b

[Mesa-dev] [PATCH 24/41] i965: Add HiZ operation state to brw_context

2011-11-17 Thread Chad Versace
brw_context::hiz contains state needed to perform HiZ meta-ops and indicates if a HiZ operation is currently in progress. Signed-off-by: Chad Versace --- src/mesa/drivers/dri/i965/brw_context.h | 35 +++ 1 files changed, 35 insertions(+), 0 deletions(-) diff --git

[Mesa-dev] [PATCH 23/41] intel: Add resolve functions for renderbuffers

2011-11-17 Thread Chad Versace
Add the following functions: intel_renderbuffer_resolve_hiz intel_renderbuffer_resolve_depth Signed-off-by: Chad Versace --- src/mesa/drivers/dri/intel/intel_fbo.c | 63 src/mesa/drivers/dri/intel/intel_fbo.h | 31 2 files changed, 94 i

[Mesa-dev] [PATCH 22/41] intel: Add resolve functions for miptrees

2011-11-17 Thread Chad Versace
Add functions that - set a miptree slice as needing a resolve - resolve a single slice of a miptree - resolve all slices of a miptree Signed-off-by: Chad Versace --- src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 118 +++- src/mesa/drivers/dri/intel/intel_mipmap_t

[Mesa-dev] [PATCH 21/41] intel: Add field intel_mipmap_tree::hiz_map

2011-11-17 Thread Chad Versace
This is a map of miptree slices to needed resolves. Signed-off-by: Chad Versace --- src/mesa/drivers/dri/intel/intel_mipmap_tree.h | 13 + 1 files changed, 13 insertions(+), 0 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.h b/src/mesa/drivers/dri/intel/in

[Mesa-dev] [PATCH 20/41] intel: Define struct intel_resolve_map

2011-11-17 Thread Chad Versace
This is a map of miptree slices to needed resolves, implemented as a linked list. A future commit will embed such a list in intel_mipmap_tree. If you think I'm crazy to put a list in a miptree, read the Doxygen in this patch for intel_resolve_map. Signed-off-by: Chad Versace --- src/mesa/driver

[Mesa-dev] [PATCH 19/41] intel: Change signature of HiZ resolve functions

2011-11-17 Thread Chad Versace
Now that intel_renderbuffer::region has been replaced with a miptree, the HiZ functions region parameter must be replaced with a miptree parameter. Change the return type from bool to void. Rename the 'depth' parameter to 'layer', because it will correspond to irb->mt_layer. Signed-off-by: Chad

[Mesa-dev] [PATCH 18/41] intel: Remove unused HiZ functions

2011-11-17 Thread Chad Versace
Remove the following functions: i830_hiz_resolve_noop i915_hiz_resolve_noop brw_hiz_resolve_noop My original strategy for how intel->vtbl.resolve_*buffer was used has substantially changed. The above functions are no longer called in the current strategy. Signed-off-by: Chad Versace ---

[Mesa-dev] [PATCH 17/41] intel: Replace intel_mipmap_tree::hiz_region with a miptree

2011-11-17 Thread Chad Versace
This is required to correctly implement HiZ for mipmapped and multi-layered textures. Signed-off-by: Chad Versace --- src/mesa/drivers/dri/i965/brw_misc_state.c |5 +++-- src/mesa/drivers/dri/intel/intel_context.c | 20 ++-- src/mesa/drivers/dri/intel/intel_fbo.c

[Mesa-dev] [PATCH 16/41] intel: Replace intel_texture_image::stencil_irb with intel_mipmap_tree::stencil_mt

2011-11-17 Thread Chad Versace
For depthstencil textures using separate stencil, we embedded a stencil buffer in intel_texture_image. The intention was that the embedded stencil buffer would be the golden copy of the texture's stencil bits. When necessary, we scattered/gathered the stencil bits between the texture miptree and th

[Mesa-dev] [PATCH 15/41] intel: Refactor intel_render_texture()

2011-11-17 Thread Chad Versace
This is in preparation for properly implementing glFramebufferTexture*() for mipmapped depthstencil textures. The FIXME comments deleted by this patch give a rough explanation of what was broken. This refactor does the following: - In intel_update_wrapper() and intel_wrap_texture(), prepare to

[Mesa-dev] [PATCH 14/41] intel: Define intel_miptree_check_level_layer()

2011-11-17 Thread Chad Versace
This is a small helper function that asserts that a given level and layer are valid for a miptree. I will be extensively using it in the future miptree HiZ functions. Signed-off-by: Chad Versace --- src/mesa/drivers/dri/intel/intel_mipmap_tree.h | 13 + 1 files changed, 13 insertio

[Mesa-dev] [PATCH 13/41] intel: Remove unneeded params from intel_renderbuffer_set_draw_offset()

2011-11-17 Thread Chad Versace
Since the renderbuffer tracks the miptree level and layer that it wraps, the 'tex_image' and 'zoffset' params are no longer needed to calculate the draw offsets. Not only are they no longer needed, but their presence would prevent calculating the renderbuffer draw offsets in situations where there

[Mesa-dev] [PATCH 12/41] intel: Track the miptree layer wrapped by a renderbuffer

2011-11-17 Thread Chad Versace
Add two fields to intel_renderbuffer: mt_level mt_layer Multiple renderbuffers may simultaneously wrap a single texture and each provide a different view into that texture. [Consider glFramebufferTextureLayer()]. The new fields indicate which slice of the miptree is wrapped by the renderb

[Mesa-dev] [PATCH 11/41] intel: Kill intel_mipmap_level::nr_images

2011-11-17 Thread Chad Versace
For all texture targets except GL_TEXTURE_CUBE_MAP, the 'nr_images' and 'depth' fields of intel_mipmap_level were identical. In the exceptional case, nr_images == 6 and depth == 1. It is simple to determine if a texture is a cube or not, so the presence of two fields here was not helpful. Worse,

[Mesa-dev] [PATCH 10/41] intel: Refactor intel_miptree_copy_teximage()

2011-11-17 Thread Chad Versace
Extract the body of the inner loop into a new function, intel_miptree_copy_slice(). This is in preparation for adding support for separate stencil and HiZ to intel_miptree_copy_teximage(). When copying a slice of a depthstencil miptree that uses separate stencil, we will also need to copy the corr

[Mesa-dev] [PATCH 09/41] intel: Refactor intel_mipmap_level offsets

2011-11-17 Thread Chad Versace
Add a new field, intel_mipmap_level::slice, and move the offset fields into it. Also add some much needed documentation for these fields. Before this patch, a separate array was allocated for the intel_mipmap_level::{x,y}_offsets. This was just silly; it incurred an extra call to malloc and dimin

[Mesa-dev] [PATCH 08/41] intel: Replace intel_renderbuffer::region with a miptree

2011-11-17 Thread Chad Versace
Essentially, this patch just globally substitutes `irb->region` with `irb->mt->region` and then does some minor cleanups to avoid segfaults and other problems. This is in preparation for 1. Fixing scatter/gather for mipmapped separate stencil textures. 2. Supporting HiZ for mipmapped depth tex

[Mesa-dev] [PATCH 07/41] intel: Define intel_miptree_create_for_renderbuffer()

2011-11-17 Thread Chad Versace
This function creates a miptree that is suitable as storage for a non-texture renderbuffer. Signed-off-by: Chad Versace --- src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 21 + src/mesa/drivers/dri/intel/intel_mipmap_tree.h | 15 +++ 2 files changed, 36 inse

[Mesa-dev] [PATCH 06/41] intel: Move inline functions from intel_fbo.h to .c

2011-11-17 Thread Chad Versace
Move the following inline functions: intel_get_rb_region intel_framebuffer_has_hiz A future commit will replace the renderbuffer's region with a miptree. This small refactor will eliminate the need for intel_fbo.h to include intel_mipmap_tree.h on that commit. I'd like to avoid the situati

[Mesa-dev] [PATCH 05/41] intel: Kill intel_framebuffer_get_hiz_region()

2011-11-17 Thread Chad Versace
The only user of intel_framebuffer_get_hiz_region() was intel_framebuffer_has_hiz(). So I folded the body of the former into the latter. Signed-off-by: Chad Versace --- src/mesa/drivers/dri/intel/intel_fbo.h | 20 +++- 1 files changed, 3 insertions(+), 17 deletions(-) diff --g

[Mesa-dev] [PATCH 04/41] intel: Temporarily disable HiZ for textures

2011-11-17 Thread Chad Versace
A great refactor thrashing begins after this commit for HiZ and separate stencil. Removing code for texture HiZ will make that refactoring easier, because then we don't have to maintain that code during the refactor. To disable HiZ for textures, I've removed the hook in intel_update_wrapper() tha

[Mesa-dev] [PATCH 03/41] intel: Always gather stencil buffer in intel_map_renderbuffer_separate_s8z24()

2011-11-17 Thread Chad Versace
The function gathered the stencil buffer into the depth buffer only when the map mode contained the read bit. But we must do the gather even if the map mode is write-only. If we do not, then, when the depth buffer's stencil bits are scattered into the stencil buffer by intel_unmap_renderbuffer(), s

[Mesa-dev] [PATCH 02/41] intel: Fix swrast_render_start() for depthstencil buffers with separate stencil

2011-11-17 Thread Chad Versace
1. Don't map the depthstencil buffer twice Place a guard in intel_renderbuffer_map() to prevent a renderbuffer from being mapped twice. This happened if a single buffer was attached to the framebuffer's depth and stencil attachment points. (Interestingly, because intel_map_renderbuffe

[Mesa-dev] [PATCH 01/41] intel: Don't use special stencil span accessors

2011-11-17 Thread Chad Versace
The special stencil span accessors, as set by intel_span_init_funcs. perform software W detiling. Since intel_renderbuffer_map() now uses MapRenderbuffer, rb->Data points to an *untiled* stencil buffer. Fixes several Piglit tests on gen7. CC: Eric Anholt Signed-off-by: Chad Versace --- src/mes

[Mesa-dev] [PATCH 00/41] i965/gen6: Enable HiZ by default

2011-11-17 Thread Chad Versace
Rejoice, the long journey is complete. At least for gen6. Regresses one Piglit test: glean/fbo. I'm not enabling HiZ for gen7 yet because it causes a mysterious performance regression. Chad Versace (40): intel: Don't use special stencil span accessors intel: Fix swrast_render_start() for dep

Re: [Mesa-dev] [PATCH 04/15] i965: Don't require spans (swrast) support to consider a format FBO complete.

2011-11-17 Thread Eric Anholt
On Thu, 17 Nov 2011 12:53:01 -0800, Ian Romanick wrote: > On 11/15/2011 05:55 PM, Eric Anholt wrote: > > We don't want to go writing GetRow/PutRow for every format required by > > GL 3.0, when it's very hard to get those functions called, and in > > every case we want to make swrast do direct mapp

[Mesa-dev] [PATCH] st/mesa: rewrite the primitive restart fallback code

2011-11-17 Thread Brian Paul
Previously we were mapping/unmapping the index buffer each time we found the restart index in the buffer. This is bad when the restart index is frequently used. Now just map the index buffer once, scan it to produce a list of sub-primitives, unmap the buffer, then draw the sub-primitives. Also,

Re: [Mesa-dev] [PATCH 01/15] i965: Add a table of the surface format information from the PRM.

2011-11-17 Thread Ian Romanick
On 11/15/2011 05:55 PM, Eric Anholt wrote: This will be used to drive chosing formats and determining framebuffer completeness, instead of the bunch of ad-hoc checks we have had until now. I can't comment much on the content of the table, but I can say that I like the way the table is made.

Re: [Mesa-dev] [PATCH 04/15] i965: Don't require spans (swrast) support to consider a format FBO complete.

2011-11-17 Thread Ian Romanick
On 11/15/2011 05:55 PM, Eric Anholt wrote: We don't want to go writing GetRow/PutRow for every format required by GL 3.0, when it's very hard to get those functions called, and in every case we want to make swrast do direct mapping through MapRenderbuffer anyway. This causes MESA_FORMAT_R11_G11_

[Mesa-dev] Mesa 7.11.1 release

2011-11-17 Thread Ian Romanick
Mesa 7.11.1 has been released. Mesa 7.11.1 is a bug fix release which fixes bugs found since the 7.11 release. The tag in the GIT repository for Mesa 7.11.1 is 'mesa-7.11.1'. Mesa 7.11.1 is available for download at ftp://freedesktop.org/pub/mesa/7.11.1/ md5sums: ac0181a4076770fb657c1169af43

Re: [Mesa-dev] [PATCH 11/15] mesa: Add fallback from RGB_FLOAT16 to RGBA_FLOAT16 before RGBA_FLOAT32.

2011-11-17 Thread Eric Anholt
On Wed, 16 Nov 2011 01:51:31 -0800 (PST), Jose Fonseca wrote: > Neither DX9 or DX10 expose equivalent to GL_RGB16F_ARB: > - http://msdn.microsoft.com/en-us/library/bb172558.aspx (D3D9) > - http://msdn.microsoft.com/en-us/library/bb173059.aspx (D3D10) > > So probably no hardware ever will support

Re: [Mesa-dev] [PATCH 01/15] i965: Add a table of the surface format information from the PRM.

2011-11-17 Thread Eric Anholt
On Wed, 16 Nov 2011 00:21:59 -0800, Kenneth Graunke wrote: > On 11/15/2011 05:55 PM, Eric Anholt wrote: > > This will be used to drive chosing formats and determining framebuffer > > completeness, instead of the bunch of ad-hoc checks we have had until > > now. > > --- > > src/mesa/drivers/dri/i

Re: [Mesa-dev] [PATCH 3/3] mesa: Track fixed-function fragment shader as a shader

2011-11-17 Thread Eric Anholt
On Wed, 16 Nov 2011 11:08:23 -0800, "Ian Romanick" wrote: > From: Ian Romanick > > Previously the fixed-function fragment shader was tracked as a > gl_program. This means that it shows up in the driver as a Mesa IR > program instead of as a GLSL IR program. If a driver doesn't generate > Mesa

Re: [Mesa-dev] [PATCH] read_rgba_pixels: Don't force clamping if the renderbuffer is already clamped.

2011-11-17 Thread Michel Dänzer
On Don, 2011-11-17 at 13:45 +0100, Theiss, Ingo wrote: > > Hi Michel, > > with this patch (b11c167...) I get a regression compared to (4517153...) with > piglit test 'texture-al -auto'. > > texture-al: failure with format GL_ALPHA: > expected color = 1, 0.5, 0, 1 > result color = 3, 0.5019

[Mesa-dev] [PATCH] mesa-demos: Add blinking-teapot demo.

2011-11-17 Thread vlj
blinking-teapot is an UBO demo. --- src/glsl/CMakeLists.txt |1 + src/glsl/Makefile.am |2 + src/glsl/blinking-teapot.c| 207 + src/glsl/blinking-teapot.frag | 31 ++ src/glsl/blinking-teapot.vert | 16 +++ 5 files chan

Re: [Mesa-dev] [PATCH] read_rgba_pixels: Don't force clamping if the renderbuffer is already clamped.

2011-11-17 Thread Theiss, Ingo
Am Mittwoch, 16. November 2011 17:44 CET, Michel Dänzer schrieb: > From: Michel Dänzer > > Signed-off-by: Michel Dänzer > --- > src/mesa/main/readpix.c |3 ++- > 1 files changed, 2 insertions(+), 1 deletions(-) > > diff --git a/src/mesa/main/readpix.c b/src/mesa/main/readpix.c > ind

Re: [Mesa-dev] [PATCH] r600g: don't change the order of writes in merge_inst_group

2011-11-17 Thread Tilman Sauerbeck
Vadim Girlin [2011-11-17 03:33]: > Merge may produce incorrect order of operations for r600-eg: > > x: inst1 R0.x, ... ; //from current group > ... > t: inst0 R0.x, ... ; //from previous group, same destination > > Result of inst1 will be lost. > > So compare destinations and