From: Chia-I Wu
Return true for NATIVE_PARAM_PREMULTIPLIED_ALPHA when all formats with
alpha support premultiplied alpha. Currently, it means when argb32 and
argb32_pre are both supported.
---
.../state_trackers/egl/wayland/native_drm.c|8 ++--
.../state_trackers/egl/wayland/nat
From: Chia-I Wu
When wl_drm is avaiable and enabled, handle "format" events and return
configs for the supported formats. Otherwise, assume all formats of
wl_shm are supported.
---
.../state_trackers/egl/wayland/native_drm.c| 70 +++-
.../state_trackers/egl/wayland/nat
From: Chia-I Wu
EGL does not export this capability of a display server. But wayland
makes use of EGL_VG_ALPHA_FORMAT to achieve it.
So, when the native display returns true for the parameter, st/egl will
set EGL_VG_ALPHA_FORMAT_PRE_BIT for all EGLConfig's with non-zero
EGL_ALPHA_SIZE. EGL_VG_
From: Chia-I Wu
Return TRUE if the display supports premultiplied alpha.
---
src/gallium/state_trackers/egl/common/native.h | 11 ++-
1 files changed, 10 insertions(+), 1 deletions(-)
diff --git a/src/gallium/state_trackers/egl/common/native.h
b/src/gallium/state_trackers/egl/common/
From: Chia-I Wu
Replace the parameters of native_surface::present by a struct,
native_present_control. Using a struct allows us to add more control
options without having to update each backend every time.
---
.../state_trackers/egl/android/native_android.cpp | 10 --
.../state_track
This series fixes st/egl wayland backend for recent wayland changes.
The first three patches prepare native.h to support display servers
that have premultiplied alpha.
The last two patches update wayland backend to report premultiplied
alpha support and honor it.
__
This patch is just for RFC, as I am not sure it's the right way to setup
the edge flag enable bit in Vertex Element struture. Setting up this
bit, according to Bspec, need do:
1. Edge flags are supported for the following primitives
3DPRIM_TRILIST*
3DPRIM_TRISTRIP*
3DPRIM_T
Store hw_prim info in brw context for other references. This patch is
mainly for the next patch.
Signed-off-by: Yuanhan Liu
---
src/mesa/drivers/dri/i965/brw_context.h |1 +
src/mesa/drivers/dri/i965/brw_draw.c| 17 +++--
2 files changed, 8 insertions(+), 10 deletions(-)
d
On Sun, Sep 4, 2011 at 3:01 PM, Chia-I Wu wrote:
> This was a part of a bigger series posted here
>
> http://lists.freedesktop.org/archives/mesa-dev/2011-August/011450.html
>
> Changes since v1
>
> - rename __DRI_IMAGE_FORMAT_RGBA_REV to __DRI_IMAGE_FORMAT_ABGR
> - add a check in intel_
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 09/06/2011 01:51 PM, Paul Berry wrote:
> This patch series modifies the GLSL front-end to implement all the
> proper behaviors for gl_ClipDistance, namely:
>
> - gl_ClipDistance is predeclared as unsized in both the vertex and
> fragment shader.
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 09/07/2011 10:44 AM, Jose Fonseca wrote:
> - Original Message -
>> On 09/07/2011 09:40 AM, Eric Anholt wrote:
>>> On Tue, 6 Sep 2011 21:45:29 -0700 (PDT),
>>> v...@kemper.freedesktop.org (Vinson Lee) wrote:
Module: Mesa
Branch: ma
On 09/07/2011 12:51 PM, Eric Anholt wrote:
> Previously, it would produce:
>
> Failed to compile FS: 0:6(7): error: non-lvalue in assignment
>
> and now it produces:
>
> Failed to compile FS: 0:5(7): error: whole array assignment is not
> allowed in GLSL 1.10 or GLSL ES 1.00.
>
> Al
On 09/07/2011 01:14 PM, Stéphane Marchesin wrote:
---
src/mesa/state_tracker/st_cb_fbo.c | 15 ---
src/mesa/state_tracker/st_cb_fbo.h | 14 +-
2 files changed, 1 insertions(+), 28 deletions(-)
Reviewed-by: Brian Paul
___
Now instead of env INTEL_NEW_VS=1 to get it, you need INTEL_OLD_VS=1
to not get it. While it's not quite to the same codegen efficiency as
the old backend, it is not regressing piglit on G965 and G45, and
actually fixing bugs on gen6, and the remaining codegen quality
regressions all appear tracta
Fixes glsl-vs-uniform-array-4.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=33742
---
src/mesa/drivers/dri/i965/brw_vec4.cpp | 85 +++
src/mesa/drivers/dri/i965/brw_vec4.h|1 +
src/mesa/drivers/dri/i965/brw_vec4_emit.cpp |1 +
3 files change
We don't expect uniform accesses to generally go away from being dead
code at this point, and we will want to have uniforms packed before
spilling them out to pull constants when we are forced to do that.
---
src/mesa/drivers/dri/i965/brw_vec4_emit.cpp |2 +-
1 files changed, 1 insertions(+),
Fixes assertion failure from double-free in oglc
glsl-arrayobject constructor.declaration.structure
---
.../drivers/dri/i965/brw_vec4_reg_allocate.cpp |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
b/src/mesa/driver
With the core GLSL fixups I just sent out plus this patch series, I
think it's ready to turn on by default. piglit is non-regressing, and
the oglconform I've tested is overall better (but not perfect), and I
think it will fix one actual bug report.
Performance is likely to be lower on some applic
The offset to the arrays after the first was mis-scaled, so we'd go
access off the end of the surface and read 0s. Fixes
glsl-vs-uniform-array-3.
---
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/
While we had nice debug output for most of the instruction stream, it
was terminated by a series of anonymous MOVs and a send.
---
src/mesa/drivers/dri/i965/brw_vec4.h |1 +
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp |5 -
2 files changed, 5 insertions(+), 1 deletions(-)
Previously, it would produce:
Failed to compile FS: 0:6(7): error: non-lvalue in assignment
and now it produces:
Failed to compile FS: 0:5(7): error: whole array assignment is not
allowed in GLSL 1.10 or GLSL ES 1.00.
Also, add spec quotation to the two places we have code for array
On 09/07/2011 11:44 AM, Jose Fonseca wrote:
- Original Message -
On 09/07/2011 09:40 AM, Eric Anholt wrote:
On Tue, 6 Sep 2011 21:45:29 -0700 (PDT),
v...@kemper.freedesktop.org (Vinson Lee) wrote:
Module: Mesa
Branch: master
Commit: 6edef25a4b41583e1c285653fc0b84a316e9743d
URL:
h
Fixes piglit link-uniform-array-size.
---
src/glsl/ast_to_hir.cpp |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp
index 9e7496b..6ef763c 100644
--- a/src/glsl/ast_to_hir.cpp
+++ b/src/glsl/ast_to_hir.cpp
@@ -723,6 +723,7 @@
We were splitting on each side of an unlinked program, and the two
sides lost track of which variables they referenced, resulting in
assertion failure during validation. Fixes piglit
link-struct-uniform-usage.
---
src/glsl/glsl_parser_extras.cpp |2 +-
1 files changed, 1 insertions(+), 1 dele
Previously, it would produce:
Failed to compile FS: 0:6(7): error: non-lvalue in assignment
and now it produces:
Failed to compile FS: 0:5(7): error: whole array assignment is not
allowed in GLSL 1.10 or GLSL ES 1.00.
Also, add spec quotation to the two places we have code for array
We just want to mark the whole thing used, not mark from each element
the whole size in use. Fixes undefined URB entry writes on i965,
which blew up with debugging enabled.
---
src/glsl/ir_set_program_inouts.cpp |6 ++
1 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/src/gls
---
src/mesa/state_tracker/st_cb_fbo.c | 15 ---
src/mesa/state_tracker/st_cb_fbo.h | 14 +-
2 files changed, 1 insertions(+), 28 deletions(-)
diff --git a/src/mesa/state_tracker/st_cb_fbo.c
b/src/mesa/state_tracker/st_cb_fbo.c
index 5b9e203..d43f67a 100644
--- a/src/
- Original Message -
> Am 07.09.2011 07:33, schrieb Stéphane Marchesin:
> > 2011/9/2 Jose Fonseca :
> >> - Original Message -
> >>> Hi,
> >>>
> >>> While debugging some code I ran across the following situation:
> >>>
> >>> - pipe_context c1 is created
> >>> - pipe_surface s1 is c
- Original Message -
> Am 07.09.2011 02:00, schrieb Stéphane Marchesin:
> > 2011/9/6 Roland Scheidegger :
> >> Am 07.09.2011 00:01, schrieb Stéphane Marchesin:
> >>> 2011/9/3 Jose Fonseca :
>
>
> - Original Message -
> > 2011/9/2 Stéphane Marchesin :
> >> 20
- Original Message -
> On 09/07/2011 09:40 AM, Eric Anholt wrote:
> > On Tue, 6 Sep 2011 21:45:29 -0700 (PDT),
> > v...@kemper.freedesktop.org (Vinson Lee) wrote:
> >> Module: Mesa
> >> Branch: master
> >> Commit: 6edef25a4b41583e1c285653fc0b84a316e9743d
> >> URL:
> >>
> >> http://cgit
I've pushed the first and last patches (disassembly and u2f), and am
NAK'ing the rest of the series. Apparently I completely failed at
testing Gen4/5, and they don't work at all. (Sigh.)
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://li
https://bugs.freedesktop.org/show_bug.cgi?id=40633
--- Comment #3 from Chia-I Wu 2011-09-07 10:32:07 PDT ---
I've made the minimal changes to fix the build issue. Wayland clients should
work again by removing EGL_VG_ALPHA_FORMAT_PRE_BIT bit from window.c and
simple-egl.c. If the step is skipped
Am 07.09.2011 07:33, schrieb Stéphane Marchesin:
> 2011/9/2 Jose Fonseca :
>> - Original Message -
>>> Hi,
>>>
>>> While debugging some code I ran across the following situation:
>>>
>>> - pipe_context c1 is created
>>> - pipe_surface s1 is created
>>> - strb-> surface is set to s1 (s1's re
On 02.09.2011 18:09, Bryan Cain wrote:
> They are needed by glsl_to_tgsi for an efficient implementation using native
> integers.
UCMP:
NVC0 and R600 have a hardware op for this, so it would be really nice to
have for selection.
UARL:
The normal ARL expects a float source so this saves a ridiculo
Am 07.09.2011 02:00, schrieb Stéphane Marchesin:
> 2011/9/6 Roland Scheidegger :
>> Am 07.09.2011 00:01, schrieb Stéphane Marchesin:
>>> 2011/9/3 Jose Fonseca :
- Original Message -
> 2011/9/2 Stéphane Marchesin :
>> 2011/9/2 Jose Fonseca :
>>> - Original Mess
On 09/07/2011 09:40 AM, Eric Anholt wrote:
On Tue, 6 Sep 2011 21:45:29 -0700 (PDT), v...@kemper.freedesktop.org (Vinson
Lee) wrote:
Module: Mesa
Branch: master
Commit: 6edef25a4b41583e1c285653fc0b84a316e9743d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6edef25a4b41583e1c285653fc0
On Tue, 6 Sep 2011 21:45:29 -0700 (PDT), v...@kemper.freedesktop.org (Vinson
Lee) wrote:
> Module: Mesa
> Branch: master
> Commit: 6edef25a4b41583e1c285653fc0b84a316e9743d
> URL:
> http://cgit.freedesktop.org/mesa/mesa/commit/?id=6edef25a4b41583e1c285653fc0b84a316e9743d
>
> Author: Vinson Le
On Wed, 7 Sep 2011 07:39:09 -0700, Kenneth Graunke
wrote:
> While my last series was accepted, the new VS and a whole ton of work
> landed first. Beyond rebasing, v2 adds intdiv/intmod support to the VS
> as well.
Other than the comment about the MRF write, and me not reviewing the
unindenting
On Wed, 7 Sep 2011 07:39:11 -0700, Kenneth Graunke
wrote:
> This mirrors the structure Eric used in the new VS backend, and seems
> simpler. In particular, the math1/math2 split will avoid having to
> figure out how many operands there are, as this is already known by the
> caller.
>
> Signed-
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
This might seem totally random, but it's kind of related, honest :)
I was trying to get Paul's uint tests to run, but piglit_Uniform1ui is
dying. I think i
The MATH instruction unfortunately only operates on GRF registers with
an HStride of 1, so we often need to create a temporary GRF. For
integer division and modulus, we need to use an integer register.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp |3 +++
The opcodes and strings were reversed. Quotient means division, and
modulus means remainder.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_disasm.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c
b/src/mesa/d
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_shader.cpp |1 -
1 files changed, 0 insertions(+), 1 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp
b/src/mesa/drivers/dri/i965/brw_shader.cpp
index c938c75..974905d 100644
--- a/src/mesa/drivers/dri/i965/b
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_vec4_emit.cpp|2 ++
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 21 ++---
2 files changed, 20 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
b/src/mesa/drivers
The MATH instruction unfortunately only operates on GRF registers with
an HStride of 1, so we often need to create a temporary GRF. For
integer division and modulus, we need to use an integer register.
Signed-off-by: Kenneth Graunke
Reviewed-by: Ian Romanick
Reviewed-by: Eric Anholt
---
src/m
Signed-off-by: Kenneth Graunke
Reviewed-by: Ian Romanick [v1]
Reviewed-by: Eric Anholt [v1]
---
src/mesa/drivers/dri/i965/brw_defines.h|2 ++
src/mesa/drivers/dri/i965/brw_eu_emit.c|2 ++
src/mesa/drivers/dri/i965/brw_fs.cpp | 12 +++-
src
This mirrors the structure Eric used in the new VS backend, and seems
simpler. In particular, the math1/math2 split will avoid having to
figure out how many operands there are, as this is already known by the
caller.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs.cpp |
While my last series was accepted, the new VS and a whole ton of work
landed first. Beyond rebasing, v2 adds intdiv/intmod support to the VS
as well.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/
https://bugs.freedesktop.org/show_bug.cgi?id=40682
Brian Paul changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|
https://bugs.freedesktop.org/show_bug.cgi?id=40682
fdele...@free.fr changed:
What|Removed |Added
Severity|normal |blocker
Priority|medium
https://bugs.freedesktop.org/show_bug.cgi?id=40682
Summary: No makefile for src/mesa/drivers/dri/intel
Product: Mesa
Version: 7.11
Platform: Other
OS/Version: All
Status: NEW
Severity: normal
Priority: medium
https://bugs.freedesktop.org/show_bug.cgi?id=40633
Chia-I Wu changed:
What|Removed |Added
CC||benjaminfranzke@googlemail.
https://bugs.freedesktop.org/show_bug.cgi?id=40633
Marcin Slusarz changed:
What|Removed |Added
CC||sarv...@gmail.com
--- Comment #1 from M
https://bugs.freedesktop.org/show_bug.cgi?id=40668
Marcin Slusarz changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|
54 matches
Mail list logo
