@@ -236,6 +238,82 @@ using MachineFunctionPassManager =
PassManager;
/// preserve.
PreservedAnalyses getMachineFunctionPassPreservedAnalyses();
+/// For migrating to new pass manager
+/// Provides a common interface to fetch analyses instead of doing it twice in
+/// the *Leg
cdevadas wrote:
> Can you add a test? Does enough of the pipeline work to use a stop-after line
> in one of the existing tests?
Not really. A few more passes to be ported before we can use stop-after
regalloc in an existing lit test.
https://github.com/llvm/llvm-project/pull/118462
_
https://github.com/cdevadas approved this pull request.
https://github.com/llvm/llvm-project/pull/122049
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
https://github.com/cdevadas created
https://github.com/llvm/llvm-project/pull/125702
None
>From 5e5b8548b647a7b6fdd0e10eda22fef9bb341159 Mon Sep 17 00:00:00 2001
From: Christudasan Devadasan
Date: Fri, 31 Jan 2025 11:13:31 +0530
Subject: [PATCH] [CodeGen][MachineScheduler] Remove the unimpleme
https://github.com/cdevadas updated
https://github.com/llvm/llvm-project/pull/125798
>From fb306f5cd7859d6fbd82b761c8ef339485eeaa59 Mon Sep 17 00:00:00 2001
From: Christudasan Devadasan
Date: Wed, 5 Feb 2025 01:24:06 +0530
Subject: [PATCH 1/2] Added missing namespace comment and some formatting
cdevadas wrote:
### Merge activity
* **Feb 5, 12:58 AM EST**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/125703).
https://github.com/llvm/llvm-project/pull/125703
___
cdevadas wrote:
### Merge activity
* **Feb 5, 12:58 AM EST**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/125701).
https://github.com/llvm/llvm-project/pull/125701
___
cdevadas wrote:
### Merge activity
* **Feb 5, 12:58 AM EST**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/125702).
https://github.com/llvm/llvm-project/pull/125702
___
cdevadas wrote:
### Merge activity
* **Feb 5, 12:58 AM EST**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/125798).
https://github.com/llvm/llvm-project/pull/125798
___
https://github.com/cdevadas updated
https://github.com/llvm/llvm-project/pull/125703
>From 35a3a800bf08d30bc1311ad8146ac7759ed1f090 Mon Sep 17 00:00:00 2001
From: Christudasan Devadasan
Date: Thu, 16 Jan 2025 10:26:09 +0530
Subject: [PATCH 1/2] CodeGen][NewPM] Port MachineScheduler to NPM.
---
cdevadas wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/125702?utm_source=stack-comment-downstack-mergeability-warning"
https://github.com/cdevadas created
https://github.com/llvm/llvm-project/pull/125701
None
>From effa5e3fb1b50bf6530c2c0f0bb6b953224c4ea9 Mon Sep 17 00:00:00 2001
From: Christudasan Devadasan
Date: Tue, 4 Feb 2025 20:18:10 +0530
Subject: [PATCH] [MachineVerifier][NewPM] Add method to run MF thr
cdevadas wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/125703?utm_source=stack-comment-downstack-mergeability-warning"
cdevadas wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/125701?utm_source=stack-comment-downstack-mergeability-warning"
https://github.com/cdevadas created
https://github.com/llvm/llvm-project/pull/125703
None
>From 35a3a800bf08d30bc1311ad8146ac7759ed1f090 Mon Sep 17 00:00:00 2001
From: Christudasan Devadasan
Date: Thu, 16 Jan 2025 10:26:09 +0530
Subject: [PATCH] CodeGen][NewPM] Port MachineScheduler to NPM.
-
https://github.com/cdevadas created
https://github.com/llvm/llvm-project/pull/125798
Added missing namespace comment and some formatting (NFC).
CodeGen][NewPM] Port PostRAScheduler to NPM.
>From 3963f49ae0fe16cfb61940a4e73543d1169c28e7 Mon Sep 17 00:00:00 2001
From: Christudasan Devadasan
Dat
cdevadas wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/125798?utm_source=stack-comment-downstack-mergeability-warning"
https://github.com/cdevadas ready_for_review
https://github.com/llvm/llvm-project/pull/125798
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
https://github.com/cdevadas edited
https://github.com/llvm/llvm-project/pull/125798
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
https://github.com/cdevadas edited
https://github.com/llvm/llvm-project/pull/125798
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
@@ -2126,6 +2127,28 @@ void
AMDGPUCodeGenPassBuilder::addPostRegAlloc(AddMachinePass &addPass) const {
Base::addPostRegAlloc(addPass);
}
+static const char RegAllocNPMNotSupportedMessage[] =
+"-regalloc-npm not supported with amdgcn. Use -sgpr-regalloc-npm, "
+"-wwm
@@ -48,10 +48,17 @@
using namespace llvm;
-static cl::opt
-RegAlloc("regalloc-npm",
- cl::desc("Register allocator to use for new pass manager"),
- cl::Hidden, cl::init("default"));
+static cl::opt RegAlloc(
cdevadas wrote:
This c
@@ -1,4 +1,5 @@
# RUN: llc -mtriple=amdgcn -mcpu=gfx1100
-run-pass=si-optimize-exec-masking-pre-ra,greedy -verify-machineinstrs -o - %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1100
-passes=si-optimize-exec-masking-pre-ra,greedy -verify-machineinstrs -o - %s
cdevad
@@ -340,15 +348,29 @@ bool
SIOptimizeExecMaskingPreRA::optimizeElseBranch(MachineBasicBlock &MBB) {
return true;
}
-bool SIOptimizeExecMaskingPreRA::runOnMachineFunction(MachineFunction &MF) {
+PreservedAnalyses
+SIOptimizeExecMaskingPreRAPass::run(MachineFunction &MF,
+
@@ -20,7 +20,7 @@
namespace llvm {
enum class RunOutliner { TargetDefault, AlwaysOutline, NeverOutline };
-enum class RegAllocType { Default, Basic, Fast, Greedy, PBQP };
+enum class RegAllocType { Unset, Default, Basic, Fast, Greedy, PBQP };
cdevadas wrote:
@@ -1315,6 +1315,20 @@ parseBoundsCheckingOptions(StringRef Params) {
return Mode;
}
+Expected
+parseRegAllocGreedyFilterFunc(PassBuilder &PB, StringRef Params) {
+ if (Params.empty() || Params == "all") {
+return RAGreedyPass::Options();
+ }
+ std::optional Filter =
https://github.com/cdevadas edited
https://github.com/llvm/llvm-project/pull/117544
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
@@ -1,4 +1,5 @@
# RUN: llc -mtriple=amdgcn -verify-machineinstrs
-run-pass=register-coalescer,rename-independent-subregs -o - %s | FileCheck
-check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn -verify-machineinstrs
-passes=register-coalescer,rename-independent-subregs -o - %s | F
https://github.com/cdevadas approved this pull request.
https://github.com/llvm/llvm-project/pull/125192
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
@@ -387,7 +386,7 @@ class LLVM_LIBRARY_VISIBILITY SplitEditor {
/// removeBackCopies - Remove the copy instructions that defines the values
/// in the vector in the complement interval.
- void removeBackCopies(SmallVectorImpl &Copies);
+ void removeBackCopies(SmallVector
https://github.com/cdevadas commented:
Do you have any real change in SplitKit.h as part of this PR?
https://github.com/llvm/llvm-project/pull/119540
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin
https://github.com/cdevadas edited
https://github.com/llvm/llvm-project/pull/119540
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
cdevadas wrote:
Currently, regalloc won't do subreg spilling. But it will be fixed in the
foreseeable future. What will happen if you write a test that spills the
`undef` subreg of a tuple?
Do you want to cover it anyway?
https://github.com/llvm/llvm-project/pull/119684
___
https://github.com/cdevadas approved this pull request.
https://github.com/llvm/llvm-project/pull/119684
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
@@ -176,13 +176,21 @@ MACHINE_FUNCTION_PASS("verify",
MachineTraceMetricsVerifi
#define MACHINE_FUNCTION_PASS_WITH_PARAMS(NAME, CLASS, CREATE_PASS, PARSER,
\
PARAMS)
#endif
+MACHINE_FUNCTION_PASS_WITH_PARAMS(
+"machine-sink", "
@@ -127,6 +130,8 @@ class MachineSinking : public MachineFunctionPass {
const MachineBranchProbabilityInfo *MBPI = nullptr;
AliasAnalysis *AA = nullptr;
RegisterClassInfo RegClassInfo;
+ Pass *LegacyPass;
+ MachineFunctionAnalysisManager *MFAM;
cdevadas
https://github.com/cdevadas approved this pull request.
https://github.com/llvm/llvm-project/pull/120556
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
@@ -711,28 +726,66 @@ void MachineSinking::FindCycleSinkCandidates(
}
}
-bool MachineSinking::runOnMachineFunction(MachineFunction &MF) {
+PreservedAnalyses
+MachineSinkingPass::run(MachineFunction &MF,
+MachineFunctionAnalysisManager &MFAM) {
+ Mach
@@ -187,6 +187,15 @@ MACHINE_FUNCTION_PASS_WITH_PARAMS(
return parseRegAllocFastPassOptions(*PB, Params);
},
"filter=reg-filter;no-clear-vregs")
+
+MACHINE_FUNCTION_PASS_WITH_PARAMS(
+"regallocgreedy", "RAGreedyPass",
cdevadas wrote:
What's t
https://github.com/cdevadas created
https://github.com/llvm/llvm-project/pull/123045
None
>From 740d759821a443fdeb9d093cb9fc4fae81c0da4c Mon Sep 17 00:00:00 2001
From: Christudasan Devadasan
Date: Thu, 5 Dec 2024 12:07:40 +0530
Subject: [PATCH] [AMDGPU][NewPM] Port SILowerControlFlow pass into
cdevadas wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/123045?utm_source=stack-comment-downstack-mergeability-warning"
https://github.com/cdevadas ready_for_review
https://github.com/llvm/llvm-project/pull/123045
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
https://github.com/cdevadas updated
https://github.com/llvm/llvm-project/pull/123045
>From 740d759821a443fdeb9d093cb9fc4fae81c0da4c Mon Sep 17 00:00:00 2001
From: Christudasan Devadasan
Date: Thu, 5 Dec 2024 12:07:40 +0530
Subject: [PATCH 1/2] [AMDGPU][NewPM] Port SILowerControlFlow pass into N
cdevadas wrote:
I observed something while porting this pass.
The analysis LiveIntervals (LIS) uses the SlotIndexes (SI). There is no
explicit use of SI in this pass. If we have to preserve LIS, it required us to
preserve SI as well. When I initially failed to preserve SI, the following lit
te
cdevadas wrote:
> I don't know what the rules are for the new pass manager.
Thanks @jayfoad. The assertion would definitely hint to the users what's amiss
here. But the hang was quite baffling and difficult to track down. If
PassManager can't automatically determine the dependent analyses and
cdevadas wrote:
> Currently `LiveIntervals` and `SlotIndexes` are using the default
> `invalidate` implementation.
Ok, we should be able to fix it by overriding this instance in the LIS and SI.
However, the initial question is still valid. Can we have meaningful error
reporting when one fails
@@ -1412,6 +1412,20 @@ parseBoundsCheckingOptions(StringRef Params) {
return Options;
}
+Expected
+parseRegAllocGreedyFilterFunc(PassBuilder &PB, StringRef Params) {
+ if (Params.empty() || Params == "all") {
+return RAGreedyPass::Options();
+ }
+ std::optional Filter
@@ -1412,6 +1412,20 @@ parseBoundsCheckingOptions(StringRef Params) {
return Options;
}
+Expected
+parseRegAllocGreedyFilterFunc(PassBuilder &PB, StringRef Params) {
+ if (Params.empty() || Params == "all") {
+return RAGreedyPass::Options();
+ }
cdevad
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass si-pre-emit-peephole
-verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
-implicit-check-not=S_SET_GPR_IDX
+# RUN: llc -mt
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -verify-machineinstrs -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a
--amdgpu-s-branch-bits=5 -run-pass branch-relaxation %s -o - | FileCheck %s
+# RUN: llc -verify-machineinstrs -
@@ -0,0 +1,164 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030
-run-pass=amdgpu-regbank-combiner -verify-machineinstrs %s -o - | FileCheck %s
cdevadas wrote:
Drop the -verify-
@@ -0,0 +1,87 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030
-run-pass=amdgpu-regbank-combiner -verify-machineinstrs %s -o - | FileCheck %s
cdevadas wrote:
Ditto.
https://gi
https://github.com/cdevadas edited
https://github.com/llvm/llvm-project/pull/133050
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
@@ -51,6 +51,8 @@ struct CGPassBuilderOption {
bool EnableMachineFunctionSplitter = false;
bool EnableSinkAndFold = false;
bool EnableTailMerge = true;
+ /// Enable LoopTermFold immediately after LSR
cdevadas wrote:
Terminate the comment with a period.
https://github.com/cdevadas approved this pull request.
LGTM except for the comment.
https://github.com/llvm/llvm-project/pull/133050
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinf
https://github.com/cdevadas approved this pull request.
https://github.com/llvm/llvm-project/pull/138491
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
@@ -70,7 +70,6 @@ FUNCTION_PASS("scalarize-masked-mem-intrin",
ScalarizeMaskedMemIntrinPass())
FUNCTION_PASS("select-optimize", SelectOptimizePass(TM))
FUNCTION_PASS("sjlj-eh-prepare", SjLjEHPreparePass(TM))
FUNCTION_PASS("stack-protector", StackProtectorPass(TM))
-FUNCTION_PA
https://github.com/cdevadas approved this pull request.
https://github.com/llvm/llvm-project/pull/120557
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
@@ -419,25 +419,30 @@ body: |
...
-# FIXME:
-# ---
-# name:fold_v_mov_b64_64_to_unaligned
-# body: |
-# bb.0:
-# %0:vreg_64_align2 = V_MOV_B64_e32 1311768467750121200, implicit $exec
-# %1:vreg_64 = COPY killed %0
-# SI_RETURN
@@ -3473,14 +3473,19 @@ bool SIInstrInfo::foldImmediate(MachineInstr &UseMI,
MachineInstr &DefMI,
assert(UseMI.getOperand(1).getReg().isVirtual());
}
+MachineFunction *MF = UseMI.getParent()->getParent();
cdevadas wrote:
```suggestion
Machi
https://github.com/cdevadas approved this pull request.
https://github.com/llvm/llvm-project/pull/127481
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
https://github.com/cdevadas approved this pull request.
https://github.com/llvm/llvm-project/pull/127563
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
@@ -2,6 +2,8 @@
# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize64
-run-pass=si-late-branch-lowering -verify-machineinstrs %s -o - | FileCheck
-check-prefixes=GCN,GFX10 %s
# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64
-run-pass=si-late-branch
@@ -1,4 +1,5 @@
# RUN: llc -o - %s -mtriple=amdgcn -mcpu=fiji
-run-pass=si-late-branch-lowering -verify-machineinstrs | FileCheck
-check-prefix=GCN %s
+# RUN: llc -o - %s -mtriple=amdgcn -mcpu=fiji -passes=si-late-branch-lowering
-verify-machineinstrs | FileCheck -check-prefix
@@ -96,12 +108,20 @@ static bool isVMEMLoad(const MachineInstr &MI) {
return SIInstrInfo::isVMEM(MI) && MI.mayLoad();
}
-bool AMDGPUSetWavePriority::runOnMachineFunction(MachineFunction &MF) {
+PreservedAnalyses
+llvm::AMDGPUSetWavePriorityPass::run(MachineFunction &MF,
+
https://github.com/cdevadas approved this pull request.
https://github.com/llvm/llvm-project/pull/130064
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=si-pre-emit-peephole
-verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -passes=si-pre-emit-peep
@@ -1,6 +1,8 @@
# RUN: llc -mtriple=amdgcn -mcpu=carrizo -verify-machineinstrs -run-pass
post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GCN,XNACK %s
# RUN: llc -mtriple=amdgcn -mcpu=fiji -mattr=-xnack -verify-machineinstrs
-run-pass post-RA-hazard-rec %s -o - | FileC
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
UTC_ARGS: --version 5
# RUN: llc -mtriple=amdgcn -mcpu=gfx942 -verify-machineinstrs
-run-pass=post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn -
@@ -744,7 +753,15 @@ bool BranchRelaxation::relaxBranchInstructions() {
return Changed;
}
-bool BranchRelaxation::runOnMachineFunction(MachineFunction &mf) {
+PreservedAnalyses
+BranchRelaxationPass::run(MachineFunction &MF,
+ MachineFunctionAnalysis
https://github.com/cdevadas approved this pull request.
https://github.com/llvm/llvm-project/pull/130067
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
https://github.com/cdevadas approved this pull request.
https://github.com/llvm/llvm-project/pull/130068
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
https://github.com/cdevadas approved this pull request.
https://github.com/llvm/llvm-project/pull/130069
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
@@ -40,30 +41,45 @@ using namespace llvm;
STATISTIC(NumNoops, "Number of noops inserted");
namespace {
- class PostRAHazardRecognizer : public MachineFunctionPass {
+struct PostRAHazardRecognizer {
+ bool run(MachineFunction &MF);
+};
- public:
-static char ID;
-P
@@ -742,6 +730,36 @@ class SIInsertWaitcnts : public MachineFunctionPass {
WaitcntBrackets &ScoreBrackets);
};
+class SIInsertWaitcntsLegacy : public MachineFunctionPass {
+public:
+ static char ID;
+ SIInsertWaitcntsLegacy() : MachineFunctionPass
@@ -66,21 +69,44 @@ class RemoveLoadsIntoFakeUses : public MachineFunctionPass {
bool runOnMachineFunction(MachineFunction &MF) override;
};
-char RemoveLoadsIntoFakeUses::ID = 0;
-char &llvm::RemoveLoadsIntoFakeUsesID = RemoveLoadsIntoFakeUses::ID;
+struct RemoveLoadsIntoFa
@@ -276,16 +288,49 @@ void VirtRegRewriter::getAnalysisUsage(AnalysisUsage &AU)
const {
MachineFunctionPass::getAnalysisUsage(AU);
}
-bool VirtRegRewriter::runOnMachineFunction(MachineFunction &fn) {
+bool VirtRegRewriterLegacy::runOnMachineFunction(MachineFunction &MF) {
+
https://github.com/cdevadas approved this pull request.
No tests for this pass?
https://github.com/llvm/llvm-project/pull/129857
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llv
https://github.com/cdevadas approved this pull request.
https://github.com/llvm/llvm-project/pull/130060
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs -run-pass
si-insert-hard-clauses %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs -
https://github.com/cdevadas approved this pull request.
https://github.com/llvm/llvm-project/pull/130065
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
https://github.com/cdevadas approved this pull request.
https://github.com/llvm/llvm-project/pull/129866
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
@@ -20,34 +20,53 @@
#include "llvm/IR/MDBuilder.h"
#include "llvm/InitializePasses.h"
#include "llvm/Pass.h"
+#include "llvm/Transforms/Instrumentation/SanitizerBinaryMetadata.h"
#include
using namespace llvm;
namespace {
-class MachineSanitizerBinaryMetadata : public M
https://github.com/cdevadas approved this pull request.
https://github.com/llvm/llvm-project/pull/130063
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
https://github.com/cdevadas approved this pull request.
No tests?
https://github.com/llvm/llvm-project/pull/130070
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commi
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs -run-pass
si-insert-hard-clauses %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs -
@@ -410,7 +417,15 @@ bool SIPreEmitPeephole::removeExeczBranch(MachineInstr &MI,
return true;
}
-bool SIPreEmitPeephole::runOnMachineFunction(MachineFunction &MF) {
+PreservedAnalyses
+llvm::SIPreEmitPeepholePass::run(MachineFunction &MF,
+ Ma
https://github.com/cdevadas approved this pull request.
https://github.com/llvm/llvm-project/pull/130062
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
https://github.com/cdevadas approved this pull request.
https://github.com/llvm/llvm-project/pull/130066
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
@@ -58,15 +55,30 @@ class AMDGPUSetWavePriority : public MachineFunctionPass {
const SIInstrInfo *TII;
};
+class AMDGPUSetWavePriorityLegacy : public MachineFunctionPass {
+public:
+ static char ID;
+
+ AMDGPUSetWavePriorityLegacy() : MachineFunctionPass(ID) {}
+
+ String
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs
-run-pass=si-insert-waitcnts %s -o - | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-mac
@@ -1,4 +1,6 @@
# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -start-before=greedy,0
-stop-after=virtregrewriter,2 -verify-machineinstrs -o - %s | FileCheck
--check-prefixes=GCN,GFX90A %s
+
+# RUN: llc -enable-new-pm -mtriple=amdgcn -mcpu=gfx90a -start-before=greedy,0
-stop-after=vi
@@ -193,12 +193,12 @@ MACHINE_FUNCTION_PASS_WITH_PARAMS(
},
"filter=reg-filter;no-clear-vregs")
+// 'all' is the default filter
cdevadas wrote:
```suggestion
// 'all' is the default filter.
```
https://github.com/llvm/llvm-project/pull/120557
___
https://github.com/cdevadas approved this pull request.
LGTM with a nit.
https://github.com/llvm/llvm-project/pull/120557
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branc
https://github.com/cdevadas edited
https://github.com/llvm/llvm-project/pull/120557
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
https://github.com/cdevadas approved this pull request.
https://github.com/llvm/llvm-project/pull/128151
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
@@ -189,30 +198,19 @@ class MachineSinking : public MachineFunctionPass {
bool EnableSinkAndFold;
public:
- static char ID; // Pass identification
-
- MachineSinking() : MachineFunctionPass(ID) {
-initializeMachineSinkingPass(*PassRegistry::getPassRegistry());
- }
-
-
@@ -1005,7 +1007,8 @@ void RegAllocFastImpl::allocVirtRegUndef(MachineOperand
&MO) {
MO.setSubReg(0);
}
MO.setReg(PhysReg);
- MO.setIsRenamable(true);
+ if (!LRI->Error)
+MO.setIsRenamable(true);
cdevadas wrote:
```suggestion
MO.setIsRenamable
https://github.com/cdevadas edited
https://github.com/llvm/llvm-project/pull/129035
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
@@ -2,11 +2,17 @@
# RUN: llc -mtriple=amdgcn
--passes='regallocfast,regallocfast,regallocfast'
--print-pipeline-passes --filetype=null %s | FileCheck %s --check-prefix=PASS
# RUN: not llc -mtriple=amdgcn --passes='regallocfast'
--print-pipeline-passes --filetype=null %s 2>&1
101 - 200 of 222 matches
Mail list logo
