[llvm-branch-commits] [llvm] 67d0736 - Revert "[DebugInfo][LoopStrengthReduction] SCEV-based salvaging for LSR"

Author: Chris Jackson Date: 2021-07-29T00:04:50+01:00 New Revision: 67d0736b14c7888e63af16dcc71129ce07383010 URL: https://github.com/llvm/llvm-project/commit/67d0736b14c7888e63af16dcc71129ce07383010 DIFF: https://github.com/llvm/llvm-project/commit/67d0736b14c7888e63af16dcc71129ce07383010.diff

[llvm-branch-commits] [llvm] dd60b80 - [DebugInfo][LoopStrengthReduction] SCEV-based salvaging for LSR

Author: Chris Jackson Date: 2021-08-05T10:34:33+01:00 New Revision: dd60b80561ce637f8b97d709f38bc53c8d0c0510 URL: https://github.com/llvm/llvm-project/commit/dd60b80561ce637f8b97d709f38bc53c8d0c0510 DIFF: https://github.com/llvm/llvm-project/commit/dd60b80561ce637f8b97d709f38bc53c8d0c0510.diff

[llvm-branch-commits] [llvm] 692f875 - Follow-up to D105207, only salvage affine SCEVs to avoid a crash

Author: Jeremy Morse Date: 2021-08-05T10:35:08+01:00 New Revision: 692f875535db1d79e5cb9c3862a6cad0228d04e7 URL: https://github.com/llvm/llvm-project/commit/692f875535db1d79e5cb9c3862a6cad0228d04e7 DIFF: https://github.com/llvm/llvm-project/commit/692f875535db1d79e5cb9c3862a6cad0228d04e7.diff

[llvm-branch-commits] [llvm] 8988ce3 - [DebugInfo][LSR] Avoid crashes on large integer inputs

Author: Chris Jackson Date: 2021-08-05T10:38:19+01:00 New Revision: 8988ce302864ef3216e252af7d491482e71f79c7 URL: https://github.com/llvm/llvm-project/commit/8988ce302864ef3216e252af7d491482e71f79c7 DIFF: https://github.com/llvm/llvm-project/commit/8988ce302864ef3216e252af7d491482e71f79c7.diff

[llvm-branch-commits] [llvm] AMDGPU: Refactor isImmOperandLegal (PR #155607)

@@ -4572,33 +4572,42 @@ static bool compareMachineOp(const MachineOperand &Op0, } } -bool SIInstrInfo::isImmOperandLegal(const MCInstrDesc &InstDesc, unsigned OpNo, -const MachineOperand &MO) const { - const MCOperandInfo &OpInfo = InstDe

[llvm-branch-commits] [llvm] AMDGPU: Refactor isImmOperandLegal (PR #155607)

@@ -4572,33 +4572,42 @@ static bool compareMachineOp(const MachineOperand &Op0, } } -bool SIInstrInfo::isImmOperandLegal(const MCInstrDesc &InstDesc, unsigned OpNo, -const MachineOperand &MO) const { - const MCOperandInfo &OpInfo = InstDe